stv0991.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <bootstage.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <miiphy.h>
  11. #include <net.h>
  12. #include <asm/arch/stv0991_periph.h>
  13. #include <asm/arch/stv0991_defs.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/gpio.h>
  16. #include <netdev.h>
  17. #include <asm/io.h>
  18. #include <dm/platform_data/serial_pl01x.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. struct gpio_regs *const gpioa_regs =
  21. (struct gpio_regs *) GPIOA_BASE_ADDR;
  22. #ifndef CONFIG_OF_CONTROL
  23. static const struct pl01x_serial_plat serial_plat = {
  24. .base = 0x80406000,
  25. .type = TYPE_PL011,
  26. .clock = 2700 * 1000,
  27. };
  28. U_BOOT_DRVINFO(stv09911_serials) = {
  29. .name = "serial_pl01x",
  30. .plat = &serial_plat,
  31. };
  32. #endif
  33. #ifdef CONFIG_SHOW_BOOT_PROGRESS
  34. void show_boot_progress(int progress)
  35. {
  36. printf("%i\n", progress);
  37. }
  38. #endif
  39. void enable_eth_phy(void)
  40. {
  41. /* Set GPIOA_06 pad HIGH (Appli board)*/
  42. writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
  43. writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
  44. }
  45. int board_eth_enable(void)
  46. {
  47. stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
  48. clock_setup(ETH_CLOCK_CFG);
  49. enable_eth_phy();
  50. return 0;
  51. }
  52. int board_qspi_enable(void)
  53. {
  54. stv0991_pinmux_config(QSPI_CS_CLK_PAD);
  55. clock_setup(QSPI_CLOCK_CFG);
  56. return 0;
  57. }
  58. /*
  59. * Miscellaneous platform dependent initialisations
  60. */
  61. int board_init(void)
  62. {
  63. board_eth_enable();
  64. board_qspi_enable();
  65. return 0;
  66. }
  67. int board_uart_init(void)
  68. {
  69. stv0991_pinmux_config(UART_GPIOC_30_31);
  70. clock_setup(UART_CLOCK_CFG);
  71. return 0;
  72. }
  73. #ifdef CONFIG_BOARD_EARLY_INIT_F
  74. int board_early_init_f(void)
  75. {
  76. board_uart_init();
  77. return 0;
  78. }
  79. #endif
  80. int dram_init(void)
  81. {
  82. gd->ram_size = PHYS_SDRAM_1_SIZE;
  83. return 0;
  84. }
  85. int dram_init_banksize(void)
  86. {
  87. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  88. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  89. return 0;
  90. }
  91. #ifdef CONFIG_CMD_NET
  92. int board_eth_init(struct bd_info *bis)
  93. {
  94. int ret = 0;
  95. #if defined(CONFIG_ETH_DESIGNWARE)
  96. u32 interface = PHY_INTERFACE_MODE_MII;
  97. if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
  98. ret++;
  99. #endif
  100. return ret;
  101. }
  102. #endif