cm_fx6.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Compulab CM-FX6 board
  4. *
  5. * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  6. *
  7. * Author: Nikita Kiryanov <nikita@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <ahci.h>
  11. #include <dm.h>
  12. #include <dwc_ahsata.h>
  13. #include <env.h>
  14. #include <fsl_esdhc_imx.h>
  15. #include <init.h>
  16. #include <miiphy.h>
  17. #include <mtd_node.h>
  18. #include <net.h>
  19. #include <netdev.h>
  20. #include <errno.h>
  21. #include <usb.h>
  22. #include <fdt_support.h>
  23. #include <sata.h>
  24. #include <splash.h>
  25. #include <asm/arch/crm_regs.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/arch/iomux.h>
  28. #include <asm/arch/mxc_hdmi.h>
  29. #include <asm/mach-imx/mxc_i2c.h>
  30. #include <asm/mach-imx/sata.h>
  31. #include <asm/mach-imx/video.h>
  32. #include <asm/io.h>
  33. #include <asm/gpio.h>
  34. #include <dm/platform_data/serial_mxc.h>
  35. #include <dm/device-internal.h>
  36. #include <jffs2/load_kernel.h>
  37. #include <linux/delay.h>
  38. #include "common.h"
  39. #include "../common/eeprom.h"
  40. #include "../common/common.h"
  41. DECLARE_GLOBAL_DATA_PTR;
  42. #ifdef CONFIG_SPLASH_SCREEN
  43. static struct splash_location cm_fx6_splash_locations[] = {
  44. {
  45. .name = "sf",
  46. .storage = SPLASH_STORAGE_SF,
  47. .flags = SPLASH_STORAGE_RAW,
  48. .offset = 0x100000,
  49. },
  50. {
  51. .name = "mmc_fs",
  52. .storage = SPLASH_STORAGE_MMC,
  53. .flags = SPLASH_STORAGE_FS,
  54. .devpart = "2:1",
  55. },
  56. {
  57. .name = "usb_fs",
  58. .storage = SPLASH_STORAGE_USB,
  59. .flags = SPLASH_STORAGE_FS,
  60. .devpart = "0:1",
  61. },
  62. {
  63. .name = "sata_fs",
  64. .storage = SPLASH_STORAGE_SATA,
  65. .flags = SPLASH_STORAGE_FS,
  66. .devpart = "0:1",
  67. },
  68. };
  69. int splash_screen_prepare(void)
  70. {
  71. return splash_source_load(cm_fx6_splash_locations,
  72. ARRAY_SIZE(cm_fx6_splash_locations));
  73. }
  74. #endif
  75. #ifdef CONFIG_IMX_HDMI
  76. static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  77. {
  78. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  79. imx_setup_hdmi();
  80. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  81. imx_enable_hdmi_phy();
  82. }
  83. static struct display_info_t preset_hdmi_1024X768 = {
  84. .bus = -1,
  85. .addr = 0,
  86. .pixfmt = IPU_PIX_FMT_RGB24,
  87. .enable = cm_fx6_enable_hdmi,
  88. .mode = {
  89. .name = "HDMI",
  90. .refresh = 60,
  91. .xres = 1024,
  92. .yres = 768,
  93. .pixclock = 40385,
  94. .left_margin = 220,
  95. .right_margin = 40,
  96. .upper_margin = 21,
  97. .lower_margin = 7,
  98. .hsync_len = 60,
  99. .vsync_len = 10,
  100. .sync = FB_SYNC_EXT,
  101. .vmode = FB_VMODE_NONINTERLACED,
  102. }
  103. };
  104. static void cm_fx6_setup_display(void)
  105. {
  106. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  107. enable_ipu_clock();
  108. clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  109. }
  110. int board_video_skip(void)
  111. {
  112. int ret;
  113. struct display_info_t *preset;
  114. char const *panel = env_get("displaytype");
  115. if (!panel) /* Also accept panel for backward compatibility */
  116. panel = env_get("panel");
  117. if (!panel)
  118. return -ENOENT;
  119. if (!strcmp(panel, "HDMI"))
  120. preset = &preset_hdmi_1024X768;
  121. else
  122. return -EINVAL;
  123. ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
  124. if (ret) {
  125. printf("Can't init display %s: %d\n", preset->mode.name, ret);
  126. return ret;
  127. }
  128. preset->enable(preset);
  129. printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
  130. preset->mode.yres);
  131. return 0;
  132. }
  133. #else
  134. static inline void cm_fx6_setup_display(void) {}
  135. #endif /* CONFIG_VIDEO_IPUV3 */
  136. int ipu_displays_init(void)
  137. {
  138. return board_video_skip();
  139. }
  140. #ifdef CONFIG_DWC_AHSATA
  141. static int cm_fx6_issd_gpios[] = {
  142. /* The order of the GPIOs in the array is important! */
  143. CM_FX6_SATA_LDO_EN,
  144. CM_FX6_SATA_PHY_SLP,
  145. CM_FX6_SATA_NRSTDLY,
  146. CM_FX6_SATA_PWREN,
  147. CM_FX6_SATA_NSTANDBY1,
  148. CM_FX6_SATA_NSTANDBY2,
  149. };
  150. static void cm_fx6_sata_power(int on)
  151. {
  152. int i;
  153. if (!on) { /* tell the iSSD that the power will be removed */
  154. gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
  155. mdelay(10);
  156. }
  157. for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  158. gpio_direction_output(cm_fx6_issd_gpios[i], on);
  159. udelay(100);
  160. }
  161. if (!on) /* for compatibility lower the power loss interrupt */
  162. gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  163. }
  164. static iomux_v3_cfg_t const sata_pads[] = {
  165. /* SATA PWR */
  166. IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  167. IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  168. IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  169. IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  170. /* SATA CTRL */
  171. IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  172. IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  173. IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  174. IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  175. IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  176. };
  177. static int cm_fx6_setup_issd(void)
  178. {
  179. int ret, i;
  180. SETUP_IOMUX_PADS(sata_pads);
  181. for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  182. ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
  183. if (ret)
  184. return ret;
  185. }
  186. ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
  187. if (ret)
  188. return ret;
  189. return 0;
  190. }
  191. #define CM_FX6_SATA_INIT_RETRIES 10
  192. #else
  193. static int cm_fx6_setup_issd(void) { return 0; }
  194. #endif
  195. #ifdef CONFIG_SYS_I2C_MXC
  196. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  197. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  198. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  199. I2C_PADS(i2c0_pads,
  200. PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  201. PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  202. IMX_GPIO_NR(3, 21),
  203. PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  204. PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  205. IMX_GPIO_NR(3, 28));
  206. I2C_PADS(i2c1_pads,
  207. PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  208. PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  209. IMX_GPIO_NR(4, 12),
  210. PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  211. PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  212. IMX_GPIO_NR(4, 13));
  213. I2C_PADS(i2c2_pads,
  214. PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  215. PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  216. IMX_GPIO_NR(1, 3),
  217. PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  218. PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  219. IMX_GPIO_NR(1, 6));
  220. static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
  221. {
  222. int ret;
  223. ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
  224. if (ret)
  225. printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
  226. return ret;
  227. }
  228. static int cm_fx6_setup_i2c(void)
  229. {
  230. int ret = 0, err;
  231. /* i2c<x>_pads are wierd macro variables; we can't use an array */
  232. err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
  233. if (err)
  234. ret = err;
  235. err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
  236. if (err)
  237. ret = err;
  238. err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
  239. if (err)
  240. ret = err;
  241. return ret;
  242. }
  243. #else
  244. static int cm_fx6_setup_i2c(void) { return 0; }
  245. #endif
  246. #ifdef CONFIG_USB_EHCI_MX6
  247. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  248. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  249. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  250. #define MX6_USBNC_BASEADDR 0x2184800
  251. #define USBNC_USB_H1_PWR_POL (1 << 9)
  252. static int cm_fx6_setup_usb_host(void)
  253. {
  254. int err;
  255. err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
  256. if (err)
  257. return err;
  258. SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
  259. SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
  260. return 0;
  261. }
  262. static int cm_fx6_setup_usb_otg(void)
  263. {
  264. int err;
  265. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  266. err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
  267. if (err) {
  268. printf("USB OTG pwr gpio request failed: %d\n", err);
  269. return err;
  270. }
  271. SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
  272. SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
  273. MUX_PAD_CTRL(WEAK_PULLDOWN));
  274. clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
  275. /* disable ext. charger detect, or it'll affect signal quality at dp. */
  276. return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
  277. }
  278. int board_usb_phy_mode(int port)
  279. {
  280. return USB_INIT_HOST;
  281. }
  282. int board_ehci_hcd_init(int port)
  283. {
  284. int ret;
  285. u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
  286. /* Only 1 host controller in use. port 0 is OTG & needs no attention */
  287. if (port != 1)
  288. return 0;
  289. /* Set PWR polarity to match power switch's enable polarity */
  290. setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
  291. ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
  292. if (ret)
  293. return ret;
  294. udelay(10);
  295. ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
  296. if (ret)
  297. return ret;
  298. mdelay(1);
  299. return 0;
  300. }
  301. int board_ehci_power(int port, int on)
  302. {
  303. if (port == 0)
  304. return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
  305. return 0;
  306. }
  307. #else
  308. static int cm_fx6_setup_usb_otg(void) { return 0; }
  309. static int cm_fx6_setup_usb_host(void) { return 0; }
  310. #endif
  311. #ifdef CONFIG_FEC_MXC
  312. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  313. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  314. static int mx6_rgmii_rework(struct phy_device *phydev)
  315. {
  316. unsigned short val;
  317. /* Ar8031 phy SmartEEE feature cause link status generates glitch,
  318. * which cause ethernet link down/up issue, so disable SmartEEE
  319. */
  320. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
  321. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
  322. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
  323. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  324. val &= ~(0x1 << 8);
  325. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  326. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  327. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  328. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  329. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  330. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  331. val &= 0xffe3;
  332. val |= 0x18;
  333. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  334. /* introduce tx clock delay */
  335. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  336. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  337. val |= 0x0100;
  338. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  339. return 0;
  340. }
  341. int board_phy_config(struct phy_device *phydev)
  342. {
  343. mx6_rgmii_rework(phydev);
  344. if (phydev->drv->config)
  345. return phydev->drv->config(phydev);
  346. return 0;
  347. }
  348. static iomux_v3_cfg_t const enet_pads[] = {
  349. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  350. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  351. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  352. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  353. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  354. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  355. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  356. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  357. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  358. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  359. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  360. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  361. IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  362. IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  363. IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
  364. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  365. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  366. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  367. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  368. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  369. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  370. };
  371. static int handle_mac_address(char *env_var, uint eeprom_bus)
  372. {
  373. unsigned char enetaddr[6];
  374. int rc;
  375. rc = eth_env_get_enetaddr(env_var, enetaddr);
  376. if (rc)
  377. return 0;
  378. rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
  379. if (rc)
  380. return rc;
  381. if (!is_valid_ethaddr(enetaddr))
  382. return -1;
  383. return eth_env_set_enetaddr(env_var, enetaddr);
  384. }
  385. #define SB_FX6_I2C_EEPROM_BUS 0
  386. #define NO_MAC_ADDR "No MAC address found for %s\n"
  387. int board_eth_init(struct bd_info *bis)
  388. {
  389. int err;
  390. if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
  391. printf(NO_MAC_ADDR, "primary NIC");
  392. if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
  393. printf(NO_MAC_ADDR, "secondary NIC");
  394. SETUP_IOMUX_PADS(enet_pads);
  395. /* phy reset */
  396. err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
  397. if (err)
  398. printf("Etnernet NRST gpio request failed: %d\n", err);
  399. gpio_direction_output(CM_FX6_ENET_NRST, 0);
  400. udelay(500);
  401. gpio_set_value(CM_FX6_ENET_NRST, 1);
  402. enable_enet_clk(1);
  403. return cpu_eth_init(bis);
  404. }
  405. #endif
  406. #ifdef CONFIG_NAND_MXS
  407. static iomux_v3_cfg_t const nand_pads[] = {
  408. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  409. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  410. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  411. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  412. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  413. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  414. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  415. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  416. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  417. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  418. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  419. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  420. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  421. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  422. };
  423. static void cm_fx6_setup_gpmi_nand(void)
  424. {
  425. SETUP_IOMUX_PADS(nand_pads);
  426. /* Enable clock roots */
  427. enable_usdhc_clk(1, 3);
  428. enable_usdhc_clk(1, 4);
  429. setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
  430. MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
  431. MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
  432. }
  433. #else
  434. static void cm_fx6_setup_gpmi_nand(void) {}
  435. #endif
  436. #ifdef CONFIG_MXC_SPI
  437. int cm_fx6_setup_ecspi(void)
  438. {
  439. cm_fx6_set_ecspi_iomux();
  440. return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
  441. }
  442. #else
  443. int cm_fx6_setup_ecspi(void) { return 0; }
  444. #endif
  445. #ifdef CONFIG_OF_BOARD_SETUP
  446. #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
  447. static const struct node_info nodes[] = {
  448. /*
  449. * Both entries target the same flash chip. The st,m25p compatible
  450. * is used in the vendor device trees, while upstream uses (the
  451. * documented) jedec,spi-nor compatible.
  452. */
  453. { "st,m25p", MTD_DEV_TYPE_NOR, },
  454. { "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
  455. };
  456. int ft_board_setup(void *blob, struct bd_info *bd)
  457. {
  458. u32 baseboard_rev;
  459. int nodeoffset;
  460. uint8_t enetaddr[6];
  461. char baseboard_name[16];
  462. int err;
  463. fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
  464. /* MAC addr */
  465. if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
  466. fdt_find_and_setprop(blob,
  467. "/soc/aips-bus@02100000/ethernet@02188000",
  468. "local-mac-address", enetaddr, 6, 1);
  469. }
  470. if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
  471. fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
  472. enetaddr, 6, 1);
  473. }
  474. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  475. baseboard_rev = cl_eeprom_get_board_rev(0);
  476. err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
  477. if (err || baseboard_rev == 0)
  478. return 0; /* Assume not an early revision SB-FX6m baseboard */
  479. if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
  480. nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
  481. fdt_delprop(blob, nodeoffset, "cd-gpios");
  482. fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
  483. NULL, 0, 1);
  484. fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
  485. NULL, 0, 1);
  486. }
  487. return 0;
  488. }
  489. #endif
  490. int board_init(void)
  491. {
  492. int ret;
  493. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  494. cm_fx6_setup_gpmi_nand();
  495. ret = cm_fx6_setup_ecspi();
  496. if (ret)
  497. printf("Warning: ECSPI setup failed: %d\n", ret);
  498. ret = cm_fx6_setup_usb_otg();
  499. if (ret)
  500. printf("Warning: USB OTG setup failed: %d\n", ret);
  501. ret = cm_fx6_setup_usb_host();
  502. if (ret)
  503. printf("Warning: USB host setup failed: %d\n", ret);
  504. /*
  505. * cm-fx6 may have iSSD not assembled and in this case it has
  506. * bypasses for a (m)SATA socket on the baseboard. The socketed
  507. * device is not controlled by those GPIOs. So just print a warning
  508. * if the setup fails.
  509. */
  510. ret = cm_fx6_setup_issd();
  511. if (ret)
  512. printf("Warning: iSSD setup failed: %d\n", ret);
  513. /* Warn on failure but do not abort boot */
  514. ret = cm_fx6_setup_i2c();
  515. if (ret)
  516. printf("Warning: I2C setup failed: %d\n", ret);
  517. cm_fx6_setup_display();
  518. /* This should be done in the MMC driver when MX6 has a clock driver */
  519. #ifdef CONFIG_FSL_ESDHC_IMX
  520. if (IS_ENABLED(CONFIG_BLK)) {
  521. int i;
  522. cm_fx6_set_usdhc_iomux();
  523. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
  524. enable_usdhc_clk(1, i);
  525. }
  526. #endif
  527. return 0;
  528. }
  529. int board_late_init(void)
  530. {
  531. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  532. char baseboard_name[16];
  533. int err;
  534. if (is_mx6dq())
  535. env_set("board_rev", "MX6Q");
  536. else if (is_mx6dl())
  537. env_set("board_rev", "MX6DL");
  538. err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
  539. if (err)
  540. return 0;
  541. if (!strncmp("SB-FX6m", baseboard_name, 7))
  542. env_set("board_name", "Utilite");
  543. #endif
  544. return 0;
  545. }
  546. int checkboard(void)
  547. {
  548. puts("Board: CM-FX6\n");
  549. return 0;
  550. }
  551. int misc_init_r(void)
  552. {
  553. cl_print_pcb_info();
  554. return 0;
  555. }
  556. int dram_init_banksize(void)
  557. {
  558. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  559. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  560. switch (gd->ram_size) {
  561. case 0x10000000: /* DDR_16BIT_256MB */
  562. gd->bd->bi_dram[0].size = 0x10000000;
  563. gd->bd->bi_dram[1].size = 0;
  564. break;
  565. case 0x20000000: /* DDR_32BIT_512MB */
  566. gd->bd->bi_dram[0].size = 0x20000000;
  567. gd->bd->bi_dram[1].size = 0;
  568. break;
  569. case 0x40000000:
  570. if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
  571. gd->bd->bi_dram[0].size = 0x20000000;
  572. gd->bd->bi_dram[1].size = 0x20000000;
  573. } else { /* DDR_64BIT_1GB */
  574. gd->bd->bi_dram[0].size = 0x40000000;
  575. gd->bd->bi_dram[1].size = 0;
  576. }
  577. break;
  578. case 0x80000000: /* DDR_64BIT_2GB */
  579. gd->bd->bi_dram[0].size = 0x40000000;
  580. gd->bd->bi_dram[1].size = 0x40000000;
  581. break;
  582. case 0xEFF00000: /* DDR_64BIT_4GB */
  583. gd->bd->bi_dram[0].size = 0x70000000;
  584. gd->bd->bi_dram[1].size = 0x7FF00000;
  585. break;
  586. }
  587. return 0;
  588. }
  589. int dram_init(void)
  590. {
  591. gd->ram_size = imx_ddr_size();
  592. switch (gd->ram_size) {
  593. case 0x10000000:
  594. case 0x20000000:
  595. case 0x40000000:
  596. case 0x80000000:
  597. break;
  598. case 0xF0000000:
  599. gd->ram_size -= 0x100000;
  600. break;
  601. default:
  602. printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
  603. return -1;
  604. }
  605. return 0;
  606. }
  607. u32 get_board_rev(void)
  608. {
  609. return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
  610. }
  611. static struct mxc_serial_plat cm_fx6_mxc_serial_plat = {
  612. .reg = (struct mxc_uart *)UART4_BASE,
  613. };
  614. U_BOOT_DRVINFO(cm_fx6_serial) = {
  615. .name = "serial_mxc",
  616. .plat = &cm_fx6_mxc_serial_plat,
  617. };
  618. #if CONFIG_IS_ENABLED(AHCI)
  619. static int sata_imx_probe(struct udevice *dev)
  620. {
  621. int i, err;
  622. /* Make sure this gpio has logical 0 value */
  623. gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  624. udelay(100);
  625. cm_fx6_sata_power(1);
  626. for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
  627. err = setup_sata();
  628. if (err) {
  629. printf("SATA setup failed: %d\n", err);
  630. return err;
  631. }
  632. udelay(100);
  633. err = dwc_ahsata_probe(dev);
  634. if (!err)
  635. break;
  636. /* There is no device on the SATA port */
  637. if (sata_dm_port_status(0, 0) == 0)
  638. break;
  639. /* There's a device, but link not established. Retry */
  640. device_remove(dev, DM_REMOVE_NORMAL);
  641. }
  642. return 0;
  643. }
  644. static int sata_imx_remove(struct udevice *dev)
  645. {
  646. cm_fx6_sata_power(0);
  647. mdelay(250);
  648. return 0;
  649. }
  650. struct ahci_ops sata_imx_ops = {
  651. .port_status = dwc_ahsata_port_status,
  652. .reset = dwc_ahsata_bus_reset,
  653. .scan = dwc_ahsata_scan,
  654. };
  655. static const struct udevice_id sata_imx_ids[] = {
  656. { .compatible = "fsl,imx6q-ahci" },
  657. { }
  658. };
  659. U_BOOT_DRIVER(sata_imx) = {
  660. .name = "dwc_ahci",
  661. .id = UCLASS_AHCI,
  662. .of_match = sata_imx_ids,
  663. .ops = &sata_imx_ops,
  664. .probe = sata_imx_probe,
  665. .remove = sata_imx_remove, /* reset bus to stop it */
  666. };
  667. #endif /* AHCI */