ddrcsr_boot.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include "starfive_ddr.h"
  10. #include <linux/delay.h>
  11. #define REGOFFSET(offset) ((offset) / 4)
  12. static struct ddr_reg_cfg ddr_csr_cfg[] = {
  13. {0x0, 0x0, 0x00000001, REGSETALL},
  14. {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)},
  15. {0xf00, 0x0, 0x40001010, (OFFSET_SEL | F_SET | REG2G)},
  16. {0xf00, 0x0, 0x40001010, (OFFSET_SEL | F_SET | REG1G)},
  17. {0xf04, 0x0, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)},
  18. {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG1G | REG2G)},
  19. {0xf10, 0x0, 0x00400000, (OFFSET_SEL | REGSETALL)},
  20. {0xf14, 0x0, 0x043fffff, (OFFSET_SEL | REGSETALL)},
  21. {0xf18, 0x0, 0x00000000, (OFFSET_SEL | REGSETALL)},
  22. {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG2G | REG4G | REG8G)},
  23. {0xf30, 0x0, 0x07000021, (OFFSET_SEL | F_SET | REG1G)},
  24. {0xf34, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)},
  25. {0x110, 0x0, 0xc0000001, (OFFSET_SEL | REGSETALL)},
  26. {0x114, 0x0, 0xffffffff, (OFFSET_SEL | REGSETALL)},
  27. {0x10c, 0x0, 0x00000505, REGSETALL},
  28. {0x11c, 0x0, 0x00000000, REGSETALL},
  29. {0x500, 0x0, 0x00000201, REGSETALL},
  30. {0x514, 0x0, 0x00000100, REGSETALL},
  31. {0x6a8, 0x0, 0x00040000, REGSETALL},
  32. {0xea8, 0x0, 0x00040000, REGSETALL},
  33. {0x504, 0x0, 0x40000000, REGSETALL}
  34. };
  35. static struct ddr_reg_cfg ddr_csr_cfg1[] = {
  36. {0x310, 0x0, 0x00020000, REGSETALL},
  37. {0x310, 0x0, 0x00020001, REGSETALL},
  38. {0x600, 0x0, 0x002e0176, REGSETALL},
  39. {0x604, 0x0, 0x002e0176, REGSETALL},
  40. {0x608, 0x0, 0x001700bb, REGSETALL},
  41. {0x60c, 0x0, 0x000b005d, REGSETALL},
  42. {0x610, 0x0, 0x0005002e, REGSETALL},
  43. {0x614, 0x0, 0x00020017, REGSETALL},
  44. {0x618, 0x0, 0x00020017, REGSETALL},
  45. {0x61c, 0x0, 0x00020017, REGSETALL},
  46. {0x678, 0x0, 0x00000019, REGSETALL},
  47. {0x100, 0x0, 0x000000f8, REGSETALL},
  48. {0x620, 0x0, 0x03030404, REGSETALL},
  49. {0x624, 0x0, 0x04030505, REGSETALL},
  50. {0x628, 0x0, 0x07030884, REGSETALL},
  51. {0x62c, 0x0, 0x13150401, REGSETALL},
  52. {0x630, 0x0, 0x17150604, REGSETALL},
  53. {0x634, 0x0, 0x00110000, REGSETALL},
  54. {0x638, 0x0, 0x200a0a08, REGSETALL},
  55. {0x63c, 0x0, 0x1730f803, REGSETALL},
  56. {0x640, 0x0, 0x000a0c00, REGSETALL},
  57. {0x644, 0x0, 0xa005000a, REGSETALL},
  58. {0x648, 0x0, 0x00000000, REGSETALL},
  59. {0x64c, 0x0, 0x00081306, REGSETALL},
  60. {0x650, 0x0, 0x04070304, REGSETALL},
  61. {0x654, 0x0, 0x00000404, REGSETALL},
  62. {0x658, 0x0, 0x00000060, REGSETALL},
  63. {0x65c, 0x0, 0x00030008, REGSETALL},
  64. {0x660, 0x0, 0x00000000, REGSETALL},
  65. {0x680, 0x0, 0x00000603, REGSETALL},
  66. {0x684, 0x0, 0x01000202, REGSETALL},
  67. {0x688, 0x0, 0x0413040d, REGSETALL},
  68. {0x68c, 0x0, 0x20002420, REGSETALL},
  69. {0x690, 0x0, 0x00140000, REGSETALL},
  70. {0x69c, 0x0, 0x01240074, REGSETALL},
  71. {0x6a0, 0x0, 0x00000000, REGSETALL},
  72. {0x6a4, 0x0, 0x20240c00, REGSETALL},
  73. {0x6a8, 0x0, 0x00040000, REGSETALL},
  74. {0x4, 0x0, 0x30010006, (F_SET | REG4G | REG8G)},
  75. {0x4, 0x0, 0x10010006, (F_SET | REG1G | REG2G)},
  76. {0xc, 0x0, 0x00000002, REGSETALL},
  77. {0x4, 0x0, 0x30020000, (F_SET | REG4G | REG8G)},
  78. {0x4, 0x0, 0x10020000, (F_SET | REG1G | REG2G)},
  79. {0xc, 0x0, 0x00000002, REGSETALL},
  80. {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
  81. {0x4, 0x0, 0x10030031, (F_SET | REG1G | REG2G)},
  82. {0xc, 0x0, 0x00000002, REGSETALL},
  83. {0x4, 0x0, 0x300b0033, (F_SET | REG4G | REG8G)},
  84. {0x4, 0x0, 0x100b0033, (F_SET | REG1G | REG2G)},
  85. {0xc, 0x0, 0x00000002, REGSETALL},
  86. {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
  87. {0x4, 0x0, 0x10160016, (F_SET | REG1G | REG2G)},
  88. {0xc, 0x0, 0x00000002, REGSETALL},
  89. {0x10, 0x0, 0x00000010, REGSETALL},
  90. {0x14, 0x0, 0x00000001, REGSETALL},
  91. };
  92. static struct ddr_reg_cfg ddr_csr_cfg2[] = {
  93. {0xb8, 0xf0ffffff, 0x3000000, REGCLRSETALL},
  94. {0x84, 0xFEFFFFFF, 0x0, REGCLRSETALL},
  95. {0xb0, 0xFFFEFFFF, 0x0, REGCLRSETALL},
  96. {0xb0, 0xFEFFFFFF, 0x0, REGCLRSETALL},
  97. {0xb4, 0xffffffff, 0x1, REGCLRSETALL},
  98. {0x248, 0xffffffff, 0x3000000, REGCLRSETALL},
  99. {0x24c, 0xffffffff, 0x300, REGCLRSETALL},
  100. {0x24c, 0xffffffff, 0x3000000, REGCLRSETALL},
  101. {0xb0, 0xffffffff, 0x100, REGCLRSETALL},
  102. {0xb8, 0xFFF0FFFF, 0x30000, REGCLRSETALL},
  103. {0x84, 0xFFFEFFFF, 0x0, REGCLRSETALL},
  104. {0xac, 0xFFFEFFFF, 0x0, REGCLRSETALL},
  105. {0xac, 0xFEFFFFFF, 0x0, REGCLRSETALL},
  106. {0xb0, 0xffffffff, 0x1, REGCLRSETALL},
  107. {0x248, 0xffffffff, 0x30000, REGCLRSETALL},
  108. {0x24c, 0xffffffff, 0x3, REGCLRSETALL},
  109. {0x24c, 0xffffffff, 0x30000, REGCLRSETALL},
  110. {0x250, 0xffffffff, 0x3000000, REGCLRSETALL},
  111. {0x254, 0xffffffff, 0x3000000, REGCLRSETALL},
  112. {0x258, 0xffffffff, 0x3000000, REGCLRSETALL},
  113. {0xac, 0xffffffff, 0x100, REGCLRSETALL},
  114. {0x10c, 0xFFFFF0FF, 0x300, REGCLRSETALL},
  115. {0x110, 0xFFFFFEFF, 0x0, REGCLRSETALL},
  116. {0x11c, 0xFFFEFFFF, 0x0, REGCLRSETALL},
  117. {0x11c, 0xFEFFFFFF, 0x0, REGCLRSETALL},
  118. {0x120, 0xffffffff, 0x100, REGCLRSETALL},
  119. {0x2d0, 0xffffffff, 0x300, REGCLRSETALL},
  120. {0x2dc, 0xffffffff, 0x300, REGCLRSETALL},
  121. {0x2e8, 0xffffffff, 0x300, REGCLRSETALL},
  122. };
  123. static struct ddr_reg_cfg ddr_csr_cfg3[] = {
  124. {0x100, 0x0, 0x000000e0, REGSETALL},
  125. {0x620, 0x0, 0x04041417, REGSETALL},
  126. {0x624, 0x0, 0x09110609, REGSETALL},
  127. {0x628, 0x0, 0x442d0994, REGSETALL},
  128. {0x62c, 0x0, 0x271e102b, REGSETALL},
  129. {0x630, 0x0, 0x291b140a, REGSETALL},
  130. {0x634, 0x0, 0x001c0000, REGSETALL},
  131. {0x638, 0x0, 0x200f0f08, REGSETALL},
  132. {0x63c, 0x0, 0x29420a06, REGSETALL},
  133. {0x640, 0x0, 0x019e1fc1, REGSETALL},
  134. {0x644, 0x0, 0x10cb0196, REGSETALL},
  135. {0x648, 0x0, 0x00000000, REGSETALL},
  136. {0x64c, 0x0, 0x00082714, REGSETALL},
  137. {0x650, 0x0, 0x16442f0d, REGSETALL},
  138. {0x654, 0x0, 0x00001916, REGSETALL},
  139. {0x658, 0x0, 0x00000060, REGSETALL},
  140. {0x65c, 0x0, 0x00600020, REGSETALL},
  141. {0x660, 0x0, 0x00000000, REGSETALL},
  142. {0x680, 0x0, 0x0c00040f, REGSETALL},
  143. {0x684, 0x0, 0x03000604, REGSETALL},
  144. {0x688, 0x0, 0x0515040d, REGSETALL},
  145. {0x68c, 0x0, 0x20002c20, REGSETALL},
  146. {0x690, 0x0, 0x00140000, REGSETALL},
  147. {0x69c, 0x0, 0x01240074, REGSETALL},
  148. {0x6a0, 0x0, 0x00000000, REGSETALL},
  149. {0x6a4, 0x0, 0x202c0c00, REGSETALL},
  150. {0x6a8, 0x0, 0x00040000, REGSETALL},
  151. {0x4, 0x0, 0x30010036, (F_SET | REG4G | REG8G)},
  152. {0x4, 0x0, 0x10010036, (F_SET | REG1G | REG2G)},
  153. {0xc, 0x0, 0x00000002, REGSETALL},
  154. {0x4, 0x0, 0x3002001b, (F_SET | REG4G | REG8G)},
  155. {0x4, 0x0, 0x1002001b, (F_SET | REG1G | REG2G)},
  156. {0xc, 0x0, 0x00000002, REGSETALL},
  157. {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
  158. {0x4, 0x0, 0x10030031, (F_SET | REG1G | REG2G)},
  159. {0xc, 0x0, 0x00000002, REGSETALL},
  160. {0x4, 0x0, 0x300b0066, (F_SET | REG4G)},
  161. {0x4, 0x0, 0x300b0036, (F_SET | REG8G)},
  162. {0x4, 0x0, 0x100b0066, (F_SET | REG1G | REG2G)},
  163. {0xc, 0x0, 0x00000002, REGSETALL},
  164. {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
  165. {0x4, 0x0, 0x10160016, (F_SET | REG1G | REG2G)},
  166. {0xc, 0x0, 0x00000002, REGSETALL},
  167. {0x410, 0x0, 0x00101010, REGSETALL},
  168. {0x420, 0x0, 0x0c181006, REGSETALL},
  169. {0x424, 0x0, 0x20200820, REGSETALL},
  170. {0x428, 0x0, 0x80000020, REGSETALL},
  171. {0x0, 0x0, 0x00000001, REGSETALL},
  172. {0x108, 0x0, 0x00003000, REGSETALL},
  173. {0x704, 0x0, 0x00000007, REGSETALL | OFFSET_SEL},
  174. {0x330, 0x0, 0x09313fff, (F_SET | REG4G | REG8G)},
  175. {0x330, 0x0, 0x09311fff, (F_SET | REG1G | REG2G)},
  176. {0x508, 0x0, 0x00000033, (F_SET | REG4G | REG8G)},
  177. {0x508, 0x0, 0x00000013, (F_SET | REG1G | REG2G)},
  178. {0x324, 0x0, 0x00002000, REGSETALL},
  179. {0x104, 0x0, 0x90000000, REGSETALL},
  180. {0x510, 0x0, 0x00000100, REGSETALL},
  181. {0x514, 0x0, 0x00000000, REGSETALL},
  182. {0x700, 0x0, 0x00000003, REGSETALL | OFFSET_SEL},
  183. {0x514, 0x0, 0x00000600, REGSETALL},
  184. {0x20, 0x0, 0x00000001, REGSETALL},
  185. };
  186. static void ddr_csr_set(u32 *csrreg, u32 *secreg, struct ddr_reg_cfg *data,
  187. u32 len, u32 mask)
  188. {
  189. u32 *addr;
  190. u32 i;
  191. for (i = 0; i < len; i++) {
  192. if (!(data[i].flag & mask))
  193. continue;
  194. if (data[i].flag & OFFSET_SEL)
  195. addr = secreg + REGOFFSET(data[i].offset);
  196. else
  197. addr = csrreg + REGOFFSET(data[i].offset);
  198. if (data[i].flag & F_CLRSET)
  199. DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
  200. else
  201. out_le32(addr, data[i].val);
  202. }
  203. }
  204. void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
  205. {
  206. u32 len;
  207. u32 val;
  208. u32 mask;
  209. switch (size) {
  210. case DDR_SIZE_1G:
  211. mask = REG1G;
  212. break;
  213. case DDR_SIZE_2G:
  214. mask = REG2G;
  215. break;
  216. case DDR_SIZE_4G:
  217. mask = REG4G;
  218. break;
  219. case DDR_SIZE_8G:
  220. mask = REG8G;
  221. break;
  222. case DDR_SIZE_16G:
  223. default:
  224. return;
  225. };
  226. len = sizeof(ddr_csr_cfg)/sizeof(struct ddr_reg_cfg);
  227. ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask);
  228. do {
  229. udelay(1);
  230. val = in_le32(csrreg + REGOFFSET(0x504));
  231. } while ((val & 0x80000000) != 0x80000000);
  232. out_le32(csrreg + REGOFFSET(0x504), 0x00000000);
  233. out_le32(csrreg + REGOFFSET(0x50c), 0x00000000);
  234. udelay(300);
  235. out_le32(csrreg + REGOFFSET(0x50c), 0x00000001);
  236. udelay(3000);
  237. switch (size) {
  238. case DDR_SIZE_1G:
  239. case DDR_SIZE_2G:
  240. out_le32(csrreg + REGOFFSET(0x10), 0x0000001c);
  241. break;
  242. case DDR_SIZE_8G:
  243. case DDR_SIZE_4G:
  244. out_le32(csrreg + REGOFFSET(0x10), 0x0000003c);
  245. break;
  246. case DDR_SIZE_16G:
  247. default:
  248. break;
  249. };
  250. out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
  251. udelay(4);
  252. len = sizeof(ddr_csr_cfg1)/sizeof(struct ddr_reg_cfg);
  253. ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask);
  254. udelay(4);
  255. out_le32(csrreg + REGOFFSET(0x10), 0x00000011);
  256. out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
  257. switch (size) {
  258. case DDR_SIZE_4G:
  259. case DDR_SIZE_8G:
  260. out_le32(csrreg + REGOFFSET(0x10), 0x00000020);
  261. out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
  262. udelay(4);
  263. out_le32(csrreg + REGOFFSET(0x10), 0x00000021);
  264. out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
  265. break;
  266. case DDR_SIZE_1G:
  267. case DDR_SIZE_2G:
  268. case DDR_SIZE_16G:
  269. default:
  270. break;
  271. };
  272. out_le32(csrreg + REGOFFSET(0x514), 0x00000000);
  273. do {
  274. udelay(1);
  275. val = in_le32(csrreg + REGOFFSET(0x518));
  276. } while ((val & 0x2) != 0x2);
  277. val = in_le32(csrreg + REGOFFSET(0x518));
  278. while ((val & 0x2) != 0x0) {
  279. val = in_le32(phyreg + 1);
  280. if ((val & 0x20) == 0x20) {
  281. switch (val & 0x0000001f) {
  282. case 0: //ddrc_clock=12M
  283. DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
  284. break;
  285. case 1: //ddrc_clock=200M
  286. DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV8);
  287. break;
  288. case 2: //ddrc_clock=800M
  289. DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
  290. break;
  291. default:
  292. break;
  293. };
  294. out_le32((phyreg + 2), 0x1);
  295. do {
  296. udelay(2);
  297. val = in_le32(phyreg + 2);
  298. } while ((val & 0x00000001) != 0x00000000);
  299. }
  300. udelay(1);
  301. val = in_le32(csrreg + REGOFFSET(0x518));
  302. };
  303. val = in_le32(phyreg + 2048 + 83);
  304. val = in_le32(phyreg + 2048 + 84);
  305. out_le32((phyreg + 2048 + 84), val & 0xF8000000);
  306. len = sizeof(ddr_csr_cfg2)/sizeof(struct ddr_reg_cfg);
  307. ddr_csr_set((phyreg + PHY_BASE_ADDR), secreg, ddr_csr_cfg2, len, mask);
  308. len = sizeof(ddr_csr_cfg3)/sizeof(struct ddr_reg_cfg);
  309. ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask);
  310. }