meson_gx_mmc.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <malloc.h>
  11. #include <pwrseq.h>
  12. #include <mmc.h>
  13. #include <asm/io.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch/sd_emmc.h>
  16. #include <linux/log2.h>
  17. static inline void *get_regbase(const struct mmc *mmc)
  18. {
  19. struct meson_mmc_platdata *pdata = mmc->priv;
  20. return pdata->regbase;
  21. }
  22. static inline uint32_t meson_read(struct mmc *mmc, int offset)
  23. {
  24. return readl(get_regbase(mmc) + offset);
  25. }
  26. static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
  27. {
  28. writel(val, get_regbase(mmc) + offset);
  29. }
  30. static void meson_mmc_config_clock(struct mmc *mmc)
  31. {
  32. uint32_t meson_mmc_clk = 0;
  33. unsigned int clk, clk_src, clk_div;
  34. if (!mmc->clock)
  35. return;
  36. /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
  37. if (mmc->clock > 16000000) {
  38. clk = SD_EMMC_CLKSRC_DIV2;
  39. clk_src = CLK_SRC_DIV2;
  40. } else {
  41. clk = SD_EMMC_CLKSRC_24M;
  42. clk_src = CLK_SRC_24M;
  43. }
  44. clk_div = DIV_ROUND_UP(clk, mmc->clock);
  45. /* 180 phase core clock */
  46. meson_mmc_clk |= CLK_CO_PHASE_180;
  47. /* 180 phase tx clock */
  48. meson_mmc_clk |= CLK_TX_PHASE_000;
  49. /* clock settings */
  50. meson_mmc_clk |= clk_src;
  51. meson_mmc_clk |= clk_div;
  52. meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
  53. }
  54. static int meson_dm_mmc_set_ios(struct udevice *dev)
  55. {
  56. struct mmc *mmc = mmc_get_mmc_dev(dev);
  57. uint32_t meson_mmc_cfg;
  58. meson_mmc_config_clock(mmc);
  59. meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
  60. meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
  61. if (mmc->bus_width == 1)
  62. meson_mmc_cfg |= CFG_BUS_WIDTH_1;
  63. else if (mmc->bus_width == 4)
  64. meson_mmc_cfg |= CFG_BUS_WIDTH_4;
  65. else if (mmc->bus_width == 8)
  66. meson_mmc_cfg |= CFG_BUS_WIDTH_8;
  67. else
  68. return -EINVAL;
  69. /* 512 bytes block length */
  70. meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
  71. meson_mmc_cfg |= CFG_BL_LEN_512;
  72. /* Response timeout 256 clk */
  73. meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
  74. meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
  75. /* Command-command gap 16 clk */
  76. meson_mmc_cfg &= ~CFG_RC_CC_MASK;
  77. meson_mmc_cfg |= CFG_RC_CC_16;
  78. meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
  79. return 0;
  80. }
  81. static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
  82. struct mmc_cmd *cmd)
  83. {
  84. uint32_t meson_mmc_cmd = 0, cfg;
  85. meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
  86. if (cmd->resp_type & MMC_RSP_PRESENT) {
  87. if (cmd->resp_type & MMC_RSP_136)
  88. meson_mmc_cmd |= CMD_CFG_RESP_128;
  89. if (cmd->resp_type & MMC_RSP_BUSY)
  90. meson_mmc_cmd |= CMD_CFG_R1B;
  91. if (!(cmd->resp_type & MMC_RSP_CRC))
  92. meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
  93. } else {
  94. meson_mmc_cmd |= CMD_CFG_NO_RESP;
  95. }
  96. if (data) {
  97. cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
  98. cfg &= ~CFG_BL_LEN_MASK;
  99. cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
  100. meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
  101. if (data->flags == MMC_DATA_WRITE)
  102. meson_mmc_cmd |= CMD_CFG_DATA_WR;
  103. meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
  104. data->blocks;
  105. }
  106. meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
  107. CMD_CFG_END_OF_CHAIN;
  108. meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
  109. }
  110. static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
  111. {
  112. struct meson_mmc_platdata *pdata = mmc->priv;
  113. unsigned int data_size;
  114. uint32_t data_addr = 0;
  115. if (data) {
  116. data_size = data->blocks * data->blocksize;
  117. if (data->flags == MMC_DATA_READ) {
  118. data_addr = (ulong) data->dest;
  119. invalidate_dcache_range(data_addr,
  120. data_addr + data_size);
  121. } else {
  122. pdata->w_buf = calloc(data_size, sizeof(char));
  123. data_addr = (ulong) pdata->w_buf;
  124. memcpy(pdata->w_buf, data->src, data_size);
  125. flush_dcache_range(data_addr, data_addr + data_size);
  126. }
  127. }
  128. meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
  129. }
  130. static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
  131. {
  132. if (cmd->resp_type & MMC_RSP_136) {
  133. cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
  134. cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
  135. cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
  136. cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
  137. } else {
  138. cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
  139. }
  140. }
  141. static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  142. struct mmc_data *data)
  143. {
  144. struct mmc *mmc = mmc_get_mmc_dev(dev);
  145. struct meson_mmc_platdata *pdata = mmc->priv;
  146. uint32_t status;
  147. ulong start;
  148. int ret = 0;
  149. /* max block size supported by chip is 512 byte */
  150. if (data && data->blocksize > 512)
  151. return -EINVAL;
  152. meson_mmc_setup_cmd(mmc, data, cmd);
  153. meson_mmc_setup_addr(mmc, data);
  154. meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
  155. /* use 10s timeout */
  156. start = get_timer(0);
  157. do {
  158. status = meson_read(mmc, MESON_SD_EMMC_STATUS);
  159. } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
  160. if (!(status & STATUS_END_OF_CHAIN))
  161. ret = -ETIMEDOUT;
  162. else if (status & STATUS_RESP_TIMEOUT)
  163. ret = -ETIMEDOUT;
  164. else if (status & STATUS_ERR_MASK)
  165. ret = -EIO;
  166. meson_mmc_read_response(mmc, cmd);
  167. if (data && data->flags == MMC_DATA_WRITE)
  168. free(pdata->w_buf);
  169. /* reset status bits */
  170. meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
  171. return ret;
  172. }
  173. static const struct dm_mmc_ops meson_dm_mmc_ops = {
  174. .send_cmd = meson_dm_mmc_send_cmd,
  175. .set_ios = meson_dm_mmc_set_ios,
  176. };
  177. static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
  178. {
  179. struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
  180. fdt_addr_t addr;
  181. addr = devfdt_get_addr(dev);
  182. if (addr == FDT_ADDR_T_NONE)
  183. return -EINVAL;
  184. pdata->regbase = (void *)addr;
  185. return 0;
  186. }
  187. static int meson_mmc_probe(struct udevice *dev)
  188. {
  189. struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
  190. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  191. struct mmc *mmc = &pdata->mmc;
  192. struct mmc_config *cfg = &pdata->cfg;
  193. struct clk_bulk clocks;
  194. uint32_t val;
  195. int ret;
  196. #ifdef CONFIG_PWRSEQ
  197. struct udevice *pwr_dev;
  198. #endif
  199. /* Enable the clocks feeding the MMC controller */
  200. ret = clk_get_bulk(dev, &clocks);
  201. if (ret)
  202. return ret;
  203. ret = clk_enable_bulk(&clocks);
  204. if (ret)
  205. return ret;
  206. cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
  207. MMC_VDD_31_32 | MMC_VDD_165_195;
  208. cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
  209. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  210. cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
  211. cfg->f_max = 100000000; /* 100 MHz */
  212. cfg->b_max = 511; /* max 512 - 1 blocks */
  213. cfg->name = dev->name;
  214. mmc->priv = pdata;
  215. upriv->mmc = mmc;
  216. mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
  217. #ifdef CONFIG_PWRSEQ
  218. /* Enable power if needed */
  219. ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
  220. &pwr_dev);
  221. if (!ret) {
  222. ret = pwrseq_set_power(pwr_dev, true);
  223. if (ret)
  224. return ret;
  225. }
  226. #endif
  227. /* reset all status bits */
  228. meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
  229. /* disable interrupts */
  230. meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
  231. /* enable auto clock mode */
  232. val = meson_read(mmc, MESON_SD_EMMC_CFG);
  233. val &= ~CFG_SDCLK_ALWAYS_ON;
  234. val |= CFG_AUTO_CLK;
  235. meson_write(mmc, val, MESON_SD_EMMC_CFG);
  236. return 0;
  237. }
  238. int meson_mmc_bind(struct udevice *dev)
  239. {
  240. struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
  241. return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
  242. }
  243. static const struct udevice_id meson_mmc_match[] = {
  244. { .compatible = "amlogic,meson-gx-mmc" },
  245. { .compatible = "amlogic,meson-axg-mmc" },
  246. { /* sentinel */ }
  247. };
  248. U_BOOT_DRIVER(meson_mmc) = {
  249. .name = "meson_gx_mmc",
  250. .id = UCLASS_MMC,
  251. .of_match = meson_mmc_match,
  252. .ops = &meson_dm_mmc_ops,
  253. .probe = meson_mmc_probe,
  254. .bind = meson_mmc_bind,
  255. .ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
  256. .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
  257. };
  258. #ifdef CONFIG_PWRSEQ
  259. static int meson_mmc_pwrseq_set_power(struct udevice *dev, bool enable)
  260. {
  261. struct gpio_desc reset;
  262. int ret;
  263. ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
  264. if (ret)
  265. return ret;
  266. dm_gpio_set_value(&reset, 1);
  267. udelay(1);
  268. dm_gpio_set_value(&reset, 0);
  269. udelay(200);
  270. return 0;
  271. }
  272. static const struct pwrseq_ops meson_mmc_pwrseq_ops = {
  273. .set_power = meson_mmc_pwrseq_set_power,
  274. };
  275. static const struct udevice_id meson_mmc_pwrseq_ids[] = {
  276. { .compatible = "mmc-pwrseq-emmc" },
  277. { }
  278. };
  279. U_BOOT_DRIVER(meson_mmc_pwrseq_drv) = {
  280. .name = "mmc_pwrseq_emmc",
  281. .id = UCLASS_PWRSEQ,
  282. .of_match = meson_mmc_pwrseq_ids,
  283. .ops = &meson_mmc_pwrseq_ops,
  284. };
  285. #endif