gxbb.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 - BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock-gx.h>
  9. #include <asm/io.h>
  10. #include <clk-uclass.h>
  11. #include <div64.h>
  12. #include <dm.h>
  13. #include <regmap.h>
  14. #include <syscon.h>
  15. #include <dt-bindings/clock/gxbb-clkc.h>
  16. #include "clk_meson.h"
  17. #include <linux/err.h>
  18. /* This driver support only basic clock tree operations :
  19. * - Can calculate clock frequency on a limited tree
  20. * - Can Read muxes and basic dividers (0-based only)
  21. * - Can enable/disable gates with limited propagation
  22. * - Can reparent without propagation, only on muxes
  23. * - Can set rates without reparenting
  24. * This driver is adapted to what is actually supported by U-Boot
  25. */
  26. /* Only the clocks ids we don't want to expose, such as the internal muxes
  27. * and dividers of composite clocks, will remain defined here.
  28. */
  29. #define CLKID_MPEG_SEL 10
  30. #define CLKID_MPEG_DIV 11
  31. #define CLKID_SAR_ADC_DIV 99
  32. #define CLKID_MALI_0_DIV 101
  33. #define CLKID_MALI_1_DIV 104
  34. #define CLKID_CTS_AMCLK_SEL 108
  35. #define CLKID_CTS_AMCLK_DIV 109
  36. #define CLKID_CTS_MCLK_I958_SEL 111
  37. #define CLKID_CTS_MCLK_I958_DIV 112
  38. #define CLKID_32K_CLK_SEL 115
  39. #define CLKID_32K_CLK_DIV 116
  40. #define CLKID_SD_EMMC_A_CLK0_SEL 117
  41. #define CLKID_SD_EMMC_A_CLK0_DIV 118
  42. #define CLKID_SD_EMMC_B_CLK0_SEL 120
  43. #define CLKID_SD_EMMC_B_CLK0_DIV 121
  44. #define CLKID_SD_EMMC_C_CLK0_SEL 123
  45. #define CLKID_SD_EMMC_C_CLK0_DIV 124
  46. #define CLKID_VPU_0_DIV 127
  47. #define CLKID_VPU_1_DIV 130
  48. #define CLKID_VAPB_0_DIV 134
  49. #define CLKID_VAPB_1_DIV 137
  50. #define CLKID_HDMI_PLL_PRE_MULT 141
  51. #define CLKID_MPLL0_DIV 142
  52. #define CLKID_MPLL1_DIV 143
  53. #define CLKID_MPLL2_DIV 144
  54. #define CLKID_MPLL_PREDIV 145
  55. #define CLKID_FCLK_DIV2_DIV 146
  56. #define CLKID_FCLK_DIV3_DIV 147
  57. #define CLKID_FCLK_DIV4_DIV 148
  58. #define CLKID_FCLK_DIV5_DIV 149
  59. #define CLKID_FCLK_DIV7_DIV 150
  60. #define CLKID_VDEC_1_SEL 151
  61. #define CLKID_VDEC_1_DIV 152
  62. #define CLKID_VDEC_HEVC_SEL 154
  63. #define CLKID_VDEC_HEVC_DIV 155
  64. #define XTAL_RATE 24000000
  65. struct meson_clk {
  66. struct regmap *map;
  67. };
  68. static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
  69. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  70. ulong current_rate);
  71. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  72. unsigned long parent_id);
  73. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
  74. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  75. ulong rate, ulong current_rate);
  76. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
  77. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  78. static struct meson_gate gates[] = {
  79. /* Everything Else (EE) domain gates */
  80. MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
  81. MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
  82. MESON_GATE(CLKID_ISA, HHI_GCLK_MPEG0, 5),
  83. MESON_GATE(CLKID_PL301, HHI_GCLK_MPEG0, 6),
  84. MESON_GATE(CLKID_PERIPHS, HHI_GCLK_MPEG0, 7),
  85. MESON_GATE(CLKID_SPICC, HHI_GCLK_MPEG0, 8),
  86. MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  87. MESON_GATE(CLKID_SAR_ADC, HHI_GCLK_MPEG0, 10),
  88. MESON_GATE(CLKID_SMART_CARD, HHI_GCLK_MPEG0, 11),
  89. MESON_GATE(CLKID_RNG0, HHI_GCLK_MPEG0, 12),
  90. MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  91. MESON_GATE(CLKID_SDHC, HHI_GCLK_MPEG0, 14),
  92. MESON_GATE(CLKID_STREAM, HHI_GCLK_MPEG0, 15),
  93. MESON_GATE(CLKID_ASYNC_FIFO, HHI_GCLK_MPEG0, 16),
  94. MESON_GATE(CLKID_SDIO, HHI_GCLK_MPEG0, 17),
  95. MESON_GATE(CLKID_ABUF, HHI_GCLK_MPEG0, 18),
  96. MESON_GATE(CLKID_HIU_IFACE, HHI_GCLK_MPEG0, 19),
  97. MESON_GATE(CLKID_ASSIST_MISC, HHI_GCLK_MPEG0, 23),
  98. MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 24),
  99. MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
  100. MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
  101. MESON_GATE(CLKID_SPI, HHI_GCLK_MPEG0, 30),
  102. MESON_GATE(CLKID_I2S_SPDIF, HHI_GCLK_MPEG1, 2),
  103. MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
  104. MESON_GATE(CLKID_DEMUX, HHI_GCLK_MPEG1, 4),
  105. MESON_GATE(CLKID_AIU_GLUE, HHI_GCLK_MPEG1, 6),
  106. MESON_GATE(CLKID_IEC958, HHI_GCLK_MPEG1, 7),
  107. MESON_GATE(CLKID_I2S_OUT, HHI_GCLK_MPEG1, 8),
  108. MESON_GATE(CLKID_AMCLK, HHI_GCLK_MPEG1, 9),
  109. MESON_GATE(CLKID_AIFIFO2, HHI_GCLK_MPEG1, 10),
  110. MESON_GATE(CLKID_MIXER, HHI_GCLK_MPEG1, 11),
  111. MESON_GATE(CLKID_MIXER_IFACE, HHI_GCLK_MPEG1, 12),
  112. MESON_GATE(CLKID_ADC, HHI_GCLK_MPEG1, 13),
  113. MESON_GATE(CLKID_BLKMV, HHI_GCLK_MPEG1, 14),
  114. MESON_GATE(CLKID_AIU, HHI_GCLK_MPEG1, 15),
  115. MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
  116. MESON_GATE(CLKID_G2D, HHI_GCLK_MPEG1, 20),
  117. MESON_GATE(CLKID_USB0, HHI_GCLK_MPEG1, 21),
  118. MESON_GATE(CLKID_USB1, HHI_GCLK_MPEG1, 22),
  119. MESON_GATE(CLKID_RESET, HHI_GCLK_MPEG1, 23),
  120. MESON_GATE(CLKID_NAND, HHI_GCLK_MPEG1, 24),
  121. MESON_GATE(CLKID_DOS_PARSER, HHI_GCLK_MPEG1, 25),
  122. MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 26),
  123. MESON_GATE(CLKID_VDIN1, HHI_GCLK_MPEG1, 28),
  124. MESON_GATE(CLKID_AHB_ARB0, HHI_GCLK_MPEG1, 29),
  125. MESON_GATE(CLKID_EFUSE, HHI_GCLK_MPEG1, 30),
  126. MESON_GATE(CLKID_BOOT_ROM, HHI_GCLK_MPEG1, 31),
  127. MESON_GATE(CLKID_AHB_DATA_BUS, HHI_GCLK_MPEG2, 1),
  128. MESON_GATE(CLKID_AHB_CTRL_BUS, HHI_GCLK_MPEG2, 2),
  129. MESON_GATE(CLKID_HDMI_INTR_SYNC, HHI_GCLK_MPEG2, 3),
  130. MESON_GATE(CLKID_HDMI_PCLK, HHI_GCLK_MPEG2, 4),
  131. MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
  132. MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9),
  133. MESON_GATE(CLKID_MMC_PCLK, HHI_GCLK_MPEG2, 11),
  134. MESON_GATE(CLKID_DVIN, HHI_GCLK_MPEG2, 12),
  135. MESON_GATE(CLKID_UART2, HHI_GCLK_MPEG2, 15),
  136. MESON_GATE(CLKID_SANA, HHI_GCLK_MPEG2, 22),
  137. MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
  138. MESON_GATE(CLKID_SEC_AHB_AHB3_BRIDGE, HHI_GCLK_MPEG2, 26),
  139. MESON_GATE(CLKID_CLK81_A53, HHI_GCLK_MPEG2, 29),
  140. MESON_GATE(CLKID_VCLK2_VENCI0, HHI_GCLK_OTHER, 1),
  141. MESON_GATE(CLKID_VCLK2_VENCI1, HHI_GCLK_OTHER, 2),
  142. MESON_GATE(CLKID_VCLK2_VENCP0, HHI_GCLK_OTHER, 3),
  143. MESON_GATE(CLKID_VCLK2_VENCP1, HHI_GCLK_OTHER, 4),
  144. MESON_GATE(CLKID_GCLK_VENCI_INT0, HHI_GCLK_OTHER, 8),
  145. MESON_GATE(CLKID_DAC_CLK, HHI_GCLK_OTHER, 10),
  146. MESON_GATE(CLKID_AOCLK_GATE, HHI_GCLK_OTHER, 14),
  147. MESON_GATE(CLKID_IEC958_GATE, HHI_GCLK_OTHER, 16),
  148. MESON_GATE(CLKID_ENC480P, HHI_GCLK_OTHER, 20),
  149. MESON_GATE(CLKID_RNG1, HHI_GCLK_OTHER, 21),
  150. MESON_GATE(CLKID_GCLK_VENCI_INT1, HHI_GCLK_OTHER, 22),
  151. MESON_GATE(CLKID_VCLK2_VENCLMCC, HHI_GCLK_OTHER, 24),
  152. MESON_GATE(CLKID_VCLK2_VENCL, HHI_GCLK_OTHER, 25),
  153. MESON_GATE(CLKID_VCLK_OTHER, HHI_GCLK_OTHER, 26),
  154. MESON_GATE(CLKID_EDP, HHI_GCLK_OTHER, 31),
  155. /* Always On (AO) domain gates */
  156. MESON_GATE(CLKID_AO_MEDIA_CPU, HHI_GCLK_AO, 0),
  157. MESON_GATE(CLKID_AO_AHB_SRAM, HHI_GCLK_AO, 1),
  158. MESON_GATE(CLKID_AO_AHB_BUS, HHI_GCLK_AO, 2),
  159. MESON_GATE(CLKID_AO_IFACE, HHI_GCLK_AO, 3),
  160. MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
  161. /* PLL Gates */
  162. /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
  163. MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
  164. MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29),
  165. MESON_GATE(CLKID_FCLK_DIV5, HHI_MPLL_CNTL6, 30),
  166. MESON_GATE(CLKID_FCLK_DIV7, HHI_MPLL_CNTL6, 31),
  167. MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14),
  168. MESON_GATE(CLKID_MPLL1, HHI_MPLL_CNTL8, 14),
  169. MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
  170. /* CLKID_CLK81 is critical for the system */
  171. /* Peripheral Gates */
  172. MESON_GATE(CLKID_SAR_ADC_CLK, HHI_SAR_CLK_CNTL, 8),
  173. MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
  174. MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
  175. MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
  176. MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
  177. MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
  178. MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
  179. MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
  180. MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
  181. };
  182. static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
  183. {
  184. struct meson_clk *priv = dev_get_priv(clk->dev);
  185. struct meson_gate *gate;
  186. debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
  187. /* Propagate through muxes */
  188. switch (id) {
  189. case CLKID_VPU:
  190. return meson_set_gate_by_id(clk,
  191. meson_mux_get_parent(clk, CLKID_VPU), on);
  192. case CLKID_VAPB_SEL:
  193. return meson_set_gate_by_id(clk,
  194. meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
  195. }
  196. if (id >= ARRAY_SIZE(gates))
  197. return -ENOENT;
  198. gate = &gates[id];
  199. if (gate->reg == 0)
  200. return 0;
  201. debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
  202. regmap_update_bits(priv->map, gate->reg,
  203. BIT(gate->bit), on ? BIT(gate->bit) : 0);
  204. /* Propagate to next gate(s) */
  205. switch (id) {
  206. case CLKID_VAPB:
  207. return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
  208. }
  209. return 0;
  210. }
  211. static int meson_clk_enable(struct clk *clk)
  212. {
  213. return meson_set_gate_by_id(clk, clk->id, true);
  214. }
  215. static int meson_clk_disable(struct clk *clk)
  216. {
  217. return meson_set_gate_by_id(clk, clk->id, false);
  218. }
  219. static struct parm meson_vpu_0_div_parm = {
  220. HHI_VPU_CLK_CNTL, 0, 7,
  221. };
  222. int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
  223. static struct parm meson_vpu_1_div_parm = {
  224. HHI_VPU_CLK_CNTL, 16, 7,
  225. };
  226. int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
  227. static struct parm meson_vapb_0_div_parm = {
  228. HHI_VAPBCLK_CNTL, 0, 7,
  229. };
  230. int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
  231. static struct parm meson_vapb_1_div_parm = {
  232. HHI_VAPBCLK_CNTL, 16, 7,
  233. };
  234. int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
  235. static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
  236. {
  237. struct meson_clk *priv = dev_get_priv(clk->dev);
  238. unsigned int rate, parent_rate;
  239. struct parm *parm;
  240. int parent;
  241. uint reg;
  242. switch (id) {
  243. case CLKID_VPU_0_DIV:
  244. parm = &meson_vpu_0_div_parm;
  245. parent = meson_vpu_0_div_parent;
  246. break;
  247. case CLKID_VPU_1_DIV:
  248. parm = &meson_vpu_1_div_parm;
  249. parent = meson_vpu_1_div_parent;
  250. break;
  251. case CLKID_VAPB_0_DIV:
  252. parm = &meson_vapb_0_div_parm;
  253. parent = meson_vapb_0_div_parent;
  254. break;
  255. case CLKID_VAPB_1_DIV:
  256. parm = &meson_vapb_1_div_parm;
  257. parent = meson_vapb_1_div_parent;
  258. break;
  259. default:
  260. return -ENOENT;
  261. }
  262. regmap_read(priv->map, parm->reg_off, &reg);
  263. reg = PARM_GET(parm->width, parm->shift, reg);
  264. debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
  265. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  266. if (IS_ERR_VALUE(parent_rate))
  267. return parent_rate;
  268. debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
  269. rate = parent_rate / (reg + 1);
  270. debug("%s: rate of %ld is %d\n", __func__, id, rate);
  271. return rate;
  272. }
  273. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  274. ulong current_rate)
  275. {
  276. struct meson_clk *priv = dev_get_priv(clk->dev);
  277. unsigned int new_div = -EINVAL;
  278. unsigned long parent_rate;
  279. struct parm *parm;
  280. int parent;
  281. int ret;
  282. if (current_rate == rate)
  283. return 0;
  284. debug("%s: setting rate of %ld from %ld to %ld\n",
  285. __func__, id, current_rate, rate);
  286. switch (id) {
  287. case CLKID_VPU_0_DIV:
  288. parm = &meson_vpu_0_div_parm;
  289. parent = meson_vpu_0_div_parent;
  290. break;
  291. case CLKID_VPU_1_DIV:
  292. parm = &meson_vpu_1_div_parm;
  293. parent = meson_vpu_1_div_parent;
  294. break;
  295. case CLKID_VAPB_0_DIV:
  296. parm = &meson_vapb_0_div_parm;
  297. parent = meson_vapb_0_div_parent;
  298. break;
  299. case CLKID_VAPB_1_DIV:
  300. parm = &meson_vapb_1_div_parm;
  301. parent = meson_vapb_1_div_parent;
  302. break;
  303. default:
  304. return -ENOENT;
  305. }
  306. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  307. if (IS_ERR_VALUE(parent_rate))
  308. return parent_rate;
  309. debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
  310. /* If can't divide, set parent instead */
  311. if (!parent_rate || rate > parent_rate)
  312. return meson_clk_set_rate_by_id(clk, parent, rate,
  313. current_rate);
  314. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  315. debug("%s: new div of %ld is %d\n", __func__, id, new_div);
  316. /* If overflow, try to set parent rate and retry */
  317. if (!new_div || new_div > (1 << parm->width)) {
  318. ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
  319. if (IS_ERR_VALUE(ret))
  320. return ret;
  321. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  322. if (IS_ERR_VALUE(parent_rate))
  323. return parent_rate;
  324. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  325. debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
  326. if (!new_div || new_div > (1 << parm->width))
  327. return -EINVAL;
  328. }
  329. debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
  330. regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
  331. (new_div - 1) << parm->shift);
  332. debug("%s: new rate of %ld is %ld\n",
  333. __func__, id, meson_div_get_rate(clk, id));
  334. return 0;
  335. }
  336. static struct parm meson_vpu_mux_parm = {
  337. HHI_VPU_CLK_CNTL, 31, 1,
  338. };
  339. int meson_vpu_mux_parents[] = {
  340. CLKID_VPU_0,
  341. CLKID_VPU_1,
  342. };
  343. static struct parm meson_vpu_0_mux_parm = {
  344. HHI_VPU_CLK_CNTL, 9, 2,
  345. };
  346. static struct parm meson_vpu_1_mux_parm = {
  347. HHI_VPU_CLK_CNTL, 25, 2,
  348. };
  349. static int meson_vpu_0_1_mux_parents[] = {
  350. CLKID_FCLK_DIV4,
  351. CLKID_FCLK_DIV3,
  352. CLKID_FCLK_DIV5,
  353. CLKID_FCLK_DIV7,
  354. };
  355. static struct parm meson_vapb_sel_mux_parm = {
  356. HHI_VAPBCLK_CNTL, 31, 1,
  357. };
  358. int meson_vapb_sel_mux_parents[] = {
  359. CLKID_VAPB_0,
  360. CLKID_VAPB_1,
  361. };
  362. static struct parm meson_vapb_0_mux_parm = {
  363. HHI_VAPBCLK_CNTL, 9, 2,
  364. };
  365. static struct parm meson_vapb_1_mux_parm = {
  366. HHI_VAPBCLK_CNTL, 25, 2,
  367. };
  368. static int meson_vapb_0_1_mux_parents[] = {
  369. CLKID_FCLK_DIV4,
  370. CLKID_FCLK_DIV3,
  371. CLKID_FCLK_DIV5,
  372. CLKID_FCLK_DIV7,
  373. };
  374. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
  375. {
  376. struct meson_clk *priv = dev_get_priv(clk->dev);
  377. struct parm *parm;
  378. int *parents;
  379. uint reg;
  380. switch (id) {
  381. case CLKID_VPU:
  382. parm = &meson_vpu_mux_parm;
  383. parents = meson_vpu_mux_parents;
  384. break;
  385. case CLKID_VPU_0_SEL:
  386. parm = &meson_vpu_0_mux_parm;
  387. parents = meson_vpu_0_1_mux_parents;
  388. break;
  389. case CLKID_VPU_1_SEL:
  390. parm = &meson_vpu_1_mux_parm;
  391. parents = meson_vpu_0_1_mux_parents;
  392. break;
  393. case CLKID_VAPB_SEL:
  394. parm = &meson_vapb_sel_mux_parm;
  395. parents = meson_vapb_sel_mux_parents;
  396. break;
  397. case CLKID_VAPB_0_SEL:
  398. parm = &meson_vapb_0_mux_parm;
  399. parents = meson_vapb_0_1_mux_parents;
  400. break;
  401. case CLKID_VAPB_1_SEL:
  402. parm = &meson_vapb_1_mux_parm;
  403. parents = meson_vapb_0_1_mux_parents;
  404. break;
  405. default:
  406. return -ENOENT;
  407. }
  408. regmap_read(priv->map, parm->reg_off, &reg);
  409. reg = PARM_GET(parm->width, parm->shift, reg);
  410. debug("%s: parent of %ld is %d (%d)\n",
  411. __func__, id, parents[reg], reg);
  412. return parents[reg];
  413. }
  414. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  415. unsigned long parent_id)
  416. {
  417. unsigned long cur_parent = meson_mux_get_parent(clk, id);
  418. struct meson_clk *priv = dev_get_priv(clk->dev);
  419. unsigned int new_index = -EINVAL;
  420. struct parm *parm;
  421. int *parents;
  422. int i;
  423. if (IS_ERR_VALUE(cur_parent))
  424. return cur_parent;
  425. debug("%s: setting parent of %ld from %ld to %ld\n",
  426. __func__, id, cur_parent, parent_id);
  427. if (cur_parent == parent_id)
  428. return 0;
  429. switch (id) {
  430. case CLKID_VPU:
  431. parm = &meson_vpu_mux_parm;
  432. parents = meson_vpu_mux_parents;
  433. break;
  434. case CLKID_VPU_0_SEL:
  435. parm = &meson_vpu_0_mux_parm;
  436. parents = meson_vpu_0_1_mux_parents;
  437. break;
  438. case CLKID_VPU_1_SEL:
  439. parm = &meson_vpu_1_mux_parm;
  440. parents = meson_vpu_0_1_mux_parents;
  441. break;
  442. case CLKID_VAPB_SEL:
  443. parm = &meson_vapb_sel_mux_parm;
  444. parents = meson_vapb_sel_mux_parents;
  445. break;
  446. case CLKID_VAPB_0_SEL:
  447. parm = &meson_vapb_0_mux_parm;
  448. parents = meson_vapb_0_1_mux_parents;
  449. break;
  450. case CLKID_VAPB_1_SEL:
  451. parm = &meson_vapb_1_mux_parm;
  452. parents = meson_vapb_0_1_mux_parents;
  453. break;
  454. default:
  455. /* Not a mux */
  456. return -ENOENT;
  457. }
  458. for (i = 0 ; i < (1 << parm->width) ; ++i) {
  459. if (parents[i] == parent_id)
  460. new_index = i;
  461. }
  462. if (IS_ERR_VALUE(new_index))
  463. return new_index;
  464. debug("%s: new index of %ld is %d\n", __func__, id, new_index);
  465. regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
  466. new_index << parm->shift);
  467. debug("%s: new parent of %ld is %ld\n",
  468. __func__, id, meson_mux_get_parent(clk, id));
  469. return 0;
  470. }
  471. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
  472. {
  473. int parent = meson_mux_get_parent(clk, id);
  474. if (IS_ERR_VALUE(parent))
  475. return parent;
  476. return meson_clk_get_rate_by_id(clk, parent);
  477. }
  478. static unsigned long meson_clk81_get_rate(struct clk *clk)
  479. {
  480. struct meson_clk *priv = dev_get_priv(clk->dev);
  481. unsigned long parent_rate;
  482. uint reg;
  483. int parents[] = {
  484. -1,
  485. -1,
  486. CLKID_FCLK_DIV7,
  487. CLKID_MPLL1,
  488. CLKID_MPLL2,
  489. CLKID_FCLK_DIV4,
  490. CLKID_FCLK_DIV3,
  491. CLKID_FCLK_DIV5
  492. };
  493. /* mux */
  494. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  495. reg = (reg >> 12) & 7;
  496. switch (reg) {
  497. case 0:
  498. parent_rate = XTAL_RATE;
  499. break;
  500. case 1:
  501. return -ENOENT;
  502. default:
  503. parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
  504. }
  505. /* divider */
  506. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  507. reg = reg & ((1 << 7) - 1);
  508. /* clk81 divider is zero based */
  509. return parent_rate / (reg + 1);
  510. }
  511. static long mpll_rate_from_params(unsigned long parent_rate,
  512. unsigned long sdm,
  513. unsigned long n2)
  514. {
  515. unsigned long divisor = (SDM_DEN * n2) + sdm;
  516. if (n2 < N2_MIN)
  517. return -EINVAL;
  518. return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  519. }
  520. static struct parm meson_mpll0_parm[3] = {
  521. {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
  522. {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
  523. };
  524. static struct parm meson_mpll1_parm[3] = {
  525. {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
  526. {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
  527. };
  528. static struct parm meson_mpll2_parm[3] = {
  529. {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
  530. {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
  531. };
  532. /*
  533. * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  534. * scaling capabilities. MPLL rates are calculated as:
  535. *
  536. * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  537. */
  538. static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
  539. {
  540. struct meson_clk *priv = dev_get_priv(clk->dev);
  541. struct parm *psdm, *pn2;
  542. unsigned long sdm, n2;
  543. unsigned long parent_rate;
  544. uint reg;
  545. switch (id) {
  546. case CLKID_MPLL0:
  547. psdm = &meson_mpll0_parm[0];
  548. pn2 = &meson_mpll0_parm[1];
  549. break;
  550. case CLKID_MPLL1:
  551. psdm = &meson_mpll1_parm[0];
  552. pn2 = &meson_mpll1_parm[1];
  553. break;
  554. case CLKID_MPLL2:
  555. psdm = &meson_mpll2_parm[0];
  556. pn2 = &meson_mpll2_parm[1];
  557. break;
  558. default:
  559. return -ENOENT;
  560. }
  561. parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
  562. if (IS_ERR_VALUE(parent_rate))
  563. return parent_rate;
  564. regmap_read(priv->map, psdm->reg_off, &reg);
  565. sdm = PARM_GET(psdm->width, psdm->shift, reg);
  566. regmap_read(priv->map, pn2->reg_off, &reg);
  567. n2 = PARM_GET(pn2->width, pn2->shift, reg);
  568. return mpll_rate_from_params(parent_rate, sdm, n2);
  569. }
  570. static struct parm meson_fixed_pll_parm[3] = {
  571. {HHI_MPLL_CNTL, 0, 9}, /* pm */
  572. {HHI_MPLL_CNTL, 9, 5}, /* pn */
  573. {HHI_MPLL_CNTL, 16, 2}, /* pod */
  574. };
  575. static struct parm meson_sys_pll_parm[3] = {
  576. {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
  577. {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
  578. {HHI_SYS_PLL_CNTL, 10, 2}, /* pod */
  579. };
  580. static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
  581. {
  582. struct meson_clk *priv = dev_get_priv(clk->dev);
  583. struct parm *pm, *pn, *pod;
  584. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  585. u16 n, m, od;
  586. uint reg;
  587. switch (id) {
  588. case CLKID_FIXED_PLL:
  589. pm = &meson_fixed_pll_parm[0];
  590. pn = &meson_fixed_pll_parm[1];
  591. pod = &meson_fixed_pll_parm[2];
  592. break;
  593. case CLKID_SYS_PLL:
  594. pm = &meson_sys_pll_parm[0];
  595. pn = &meson_sys_pll_parm[1];
  596. pod = &meson_sys_pll_parm[2];
  597. break;
  598. default:
  599. return -ENOENT;
  600. }
  601. regmap_read(priv->map, pn->reg_off, &reg);
  602. n = PARM_GET(pn->width, pn->shift, reg);
  603. regmap_read(priv->map, pm->reg_off, &reg);
  604. m = PARM_GET(pm->width, pm->shift, reg);
  605. regmap_read(priv->map, pod->reg_off, &reg);
  606. od = PARM_GET(pod->width, pod->shift, reg);
  607. return ((parent_rate_mhz * m / n) >> od) * 1000000;
  608. }
  609. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
  610. {
  611. ulong rate;
  612. switch (id) {
  613. case CLKID_FIXED_PLL:
  614. case CLKID_SYS_PLL:
  615. rate = meson_pll_get_rate(clk, id);
  616. break;
  617. case CLKID_FCLK_DIV2:
  618. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
  619. break;
  620. case CLKID_FCLK_DIV3:
  621. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
  622. break;
  623. case CLKID_FCLK_DIV4:
  624. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
  625. break;
  626. case CLKID_FCLK_DIV5:
  627. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
  628. break;
  629. case CLKID_FCLK_DIV7:
  630. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
  631. break;
  632. case CLKID_MPLL0:
  633. case CLKID_MPLL1:
  634. case CLKID_MPLL2:
  635. rate = meson_mpll_get_rate(clk, id);
  636. break;
  637. case CLKID_CLK81:
  638. rate = meson_clk81_get_rate(clk);
  639. break;
  640. case CLKID_VPU_0:
  641. rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
  642. break;
  643. case CLKID_VPU_1:
  644. rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
  645. break;
  646. case CLKID_VAPB:
  647. rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
  648. break;
  649. case CLKID_VAPB_0:
  650. rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
  651. break;
  652. case CLKID_VAPB_1:
  653. rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
  654. break;
  655. case CLKID_VPU_0_DIV:
  656. case CLKID_VPU_1_DIV:
  657. case CLKID_VAPB_0_DIV:
  658. case CLKID_VAPB_1_DIV:
  659. rate = meson_div_get_rate(clk, id);
  660. break;
  661. case CLKID_VPU:
  662. case CLKID_VPU_0_SEL:
  663. case CLKID_VPU_1_SEL:
  664. case CLKID_VAPB_SEL:
  665. case CLKID_VAPB_0_SEL:
  666. case CLKID_VAPB_1_SEL:
  667. rate = meson_mux_get_rate(clk, id);
  668. break;
  669. default:
  670. if (gates[id].reg != 0) {
  671. /* a clock gate */
  672. rate = meson_clk81_get_rate(clk);
  673. break;
  674. }
  675. return -ENOENT;
  676. }
  677. debug("clock %lu has rate %lu\n", id, rate);
  678. return rate;
  679. }
  680. static ulong meson_clk_get_rate(struct clk *clk)
  681. {
  682. return meson_clk_get_rate_by_id(clk, clk->id);
  683. }
  684. static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
  685. {
  686. return meson_mux_set_parent(clk, clk->id, parent->id);
  687. }
  688. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  689. ulong rate, ulong current_rate)
  690. {
  691. if (current_rate == rate)
  692. return 0;
  693. switch (id) {
  694. /* Fixed clocks */
  695. case CLKID_FIXED_PLL:
  696. case CLKID_SYS_PLL:
  697. case CLKID_FCLK_DIV2:
  698. case CLKID_FCLK_DIV3:
  699. case CLKID_FCLK_DIV4:
  700. case CLKID_FCLK_DIV5:
  701. case CLKID_FCLK_DIV7:
  702. case CLKID_MPLL0:
  703. case CLKID_MPLL1:
  704. case CLKID_MPLL2:
  705. case CLKID_CLK81:
  706. return -EINVAL;
  707. case CLKID_VPU:
  708. return meson_clk_set_rate_by_id(clk,
  709. meson_mux_get_parent(clk, CLKID_VPU), rate,
  710. current_rate);
  711. case CLKID_VAPB:
  712. case CLKID_VAPB_SEL:
  713. return meson_clk_set_rate_by_id(clk,
  714. meson_mux_get_parent(clk, CLKID_VAPB_SEL),
  715. rate, current_rate);
  716. case CLKID_VPU_0:
  717. return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
  718. current_rate);
  719. case CLKID_VPU_1:
  720. return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
  721. current_rate);
  722. case CLKID_VAPB_0:
  723. return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
  724. current_rate);
  725. case CLKID_VAPB_1:
  726. return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
  727. current_rate);
  728. case CLKID_VPU_0_DIV:
  729. case CLKID_VPU_1_DIV:
  730. case CLKID_VAPB_0_DIV:
  731. case CLKID_VAPB_1_DIV:
  732. return meson_div_set_rate(clk, id, rate, current_rate);
  733. default:
  734. return -ENOENT;
  735. }
  736. return -EINVAL;
  737. }
  738. static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
  739. {
  740. ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
  741. int ret;
  742. if (IS_ERR_VALUE(current_rate))
  743. return current_rate;
  744. debug("%s: setting rate of %ld from %ld to %ld\n",
  745. __func__, clk->id, current_rate, rate);
  746. ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
  747. if (IS_ERR_VALUE(ret))
  748. return ret;
  749. debug("clock %lu has new rate %lu\n", clk->id,
  750. meson_clk_get_rate_by_id(clk, clk->id));
  751. return 0;
  752. }
  753. static int meson_clk_probe(struct udevice *dev)
  754. {
  755. struct meson_clk *priv = dev_get_priv(dev);
  756. priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
  757. if (IS_ERR(priv->map))
  758. return PTR_ERR(priv->map);
  759. /*
  760. * Depending on the boot src, the state of the MMC clock might
  761. * be different. Reset it to make sure we won't get stuck
  762. */
  763. regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
  764. regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
  765. debug("meson-clk: probed\n");
  766. return 0;
  767. }
  768. static struct clk_ops meson_clk_ops = {
  769. .disable = meson_clk_disable,
  770. .enable = meson_clk_enable,
  771. .get_rate = meson_clk_get_rate,
  772. .set_parent = meson_clk_set_parent,
  773. .set_rate = meson_clk_set_rate,
  774. };
  775. static const struct udevice_id meson_clk_ids[] = {
  776. { .compatible = "amlogic,gxbb-clkc" },
  777. { .compatible = "amlogic,gxl-clkc" },
  778. { }
  779. };
  780. U_BOOT_DRIVER(meson_clk) = {
  781. .name = "meson_clk",
  782. .id = UCLASS_CLK,
  783. .of_match = meson_clk_ids,
  784. .priv_auto_alloc_size = sizeof(struct meson_clk),
  785. .ops = &meson_clk_ops,
  786. .probe = meson_clk_probe,
  787. };