g12a.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 - BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock-g12a.h>
  9. #include <asm/io.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <div64.h>
  15. #include <dt-bindings/clock/g12a-clkc.h>
  16. #include <linux/err.h>
  17. #include <linux/kernel.h>
  18. #include "clk_meson.h"
  19. /* This driver support only basic clock tree operations :
  20. * - Can calculate clock frequency on a limited tree
  21. * - Can Read muxes and basic dividers (0-based only)
  22. * - Can enable/disable gates with limited propagation
  23. * - Can reparent without propagation, only on muxes
  24. * - Can set rates without reparenting
  25. * This driver is adapted to what is actually supported by U-Boot
  26. */
  27. /* Only the clocks ids we don't want to expose, such as the internal muxes
  28. * and dividers of composite clocks, will remain defined here.
  29. */
  30. #define CLKID_MPEG_SEL 8
  31. #define CLKID_MPEG_DIV 9
  32. #define CLKID_SD_EMMC_A_CLK0_SEL 63
  33. #define CLKID_SD_EMMC_A_CLK0_DIV 64
  34. #define CLKID_SD_EMMC_B_CLK0_SEL 65
  35. #define CLKID_SD_EMMC_B_CLK0_DIV 66
  36. #define CLKID_SD_EMMC_C_CLK0_SEL 67
  37. #define CLKID_SD_EMMC_C_CLK0_DIV 68
  38. #define CLKID_MPLL0_DIV 69
  39. #define CLKID_MPLL1_DIV 70
  40. #define CLKID_MPLL2_DIV 71
  41. #define CLKID_MPLL3_DIV 72
  42. #define CLKID_MPLL_PREDIV 73
  43. #define CLKID_FCLK_DIV2_DIV 75
  44. #define CLKID_FCLK_DIV3_DIV 76
  45. #define CLKID_FCLK_DIV4_DIV 77
  46. #define CLKID_FCLK_DIV5_DIV 78
  47. #define CLKID_FCLK_DIV7_DIV 79
  48. #define CLKID_FCLK_DIV2P5_DIV 100
  49. #define CLKID_FIXED_PLL_DCO 101
  50. #define CLKID_SYS_PLL_DCO 102
  51. #define CLKID_GP0_PLL_DCO 103
  52. #define CLKID_HIFI_PLL_DCO 104
  53. #define CLKID_VPU_0_DIV 111
  54. #define CLKID_VPU_1_DIV 114
  55. #define CLKID_VAPB_0_DIV 118
  56. #define CLKID_VAPB_1_DIV 121
  57. #define CLKID_HDMI_PLL_DCO 125
  58. #define CLKID_HDMI_PLL_OD 126
  59. #define CLKID_HDMI_PLL_OD2 127
  60. #define CLKID_VID_PLL_SEL 130
  61. #define CLKID_VID_PLL_DIV 131
  62. #define CLKID_VCLK_SEL 132
  63. #define CLKID_VCLK2_SEL 133
  64. #define CLKID_VCLK_INPUT 134
  65. #define CLKID_VCLK2_INPUT 135
  66. #define CLKID_VCLK_DIV 136
  67. #define CLKID_VCLK2_DIV 137
  68. #define CLKID_VCLK_DIV2_EN 140
  69. #define CLKID_VCLK_DIV4_EN 141
  70. #define CLKID_VCLK_DIV6_EN 142
  71. #define CLKID_VCLK_DIV12_EN 143
  72. #define CLKID_VCLK2_DIV2_EN 144
  73. #define CLKID_VCLK2_DIV4_EN 145
  74. #define CLKID_VCLK2_DIV6_EN 146
  75. #define CLKID_VCLK2_DIV12_EN 147
  76. #define CLKID_CTS_ENCI_SEL 158
  77. #define CLKID_CTS_ENCP_SEL 159
  78. #define CLKID_CTS_VDAC_SEL 160
  79. #define CLKID_HDMI_TX_SEL 161
  80. #define CLKID_HDMI_SEL 166
  81. #define CLKID_HDMI_DIV 167
  82. #define CLKID_MALI_0_DIV 170
  83. #define CLKID_MALI_1_DIV 173
  84. #define CLKID_XTAL 0x10000000
  85. #define XTAL_RATE 24000000
  86. struct meson_clk {
  87. struct regmap *map;
  88. };
  89. static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
  90. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  91. ulong current_rate);
  92. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  93. unsigned long parent_id);
  94. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
  95. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  96. ulong rate, ulong current_rate);
  97. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
  98. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  99. #define NUM_CLKS 178
  100. static struct meson_gate gates[NUM_CLKS] = {
  101. /* Everything Else (EE) domain gates */
  102. MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
  103. MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  104. MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  105. MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
  106. MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
  107. MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
  108. MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
  109. MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
  110. MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
  111. MESON_GATE(CLKID_HTX_PCLK, HHI_GCLK_MPEG2, 4),
  112. MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
  113. MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
  114. /* Peripheral Gates */
  115. MESON_GATE(CLKID_FCLK_DIV2, HHI_FIX_PLL_CNTL1, 24),
  116. MESON_GATE(CLKID_FCLK_DIV3, HHI_FIX_PLL_CNTL1, 20),
  117. MESON_GATE(CLKID_FCLK_DIV4, HHI_FIX_PLL_CNTL1, 21),
  118. MESON_GATE(CLKID_FCLK_DIV5, HHI_FIX_PLL_CNTL1, 22),
  119. MESON_GATE(CLKID_FCLK_DIV7, HHI_FIX_PLL_CNTL1, 23),
  120. MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
  121. MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
  122. MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
  123. MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
  124. MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
  125. MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
  126. MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
  127. MESON_GATE(CLKID_HDMI, HHI_HDMI_CLK_CNTL, 8),
  128. };
  129. static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
  130. {
  131. struct meson_clk *priv = dev_get_priv(clk->dev);
  132. struct meson_gate *gate;
  133. debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
  134. /* Propagate through muxes */
  135. switch (id) {
  136. case CLKID_VPU:
  137. return meson_set_gate_by_id(clk,
  138. meson_mux_get_parent(clk, CLKID_VPU), on);
  139. case CLKID_VAPB_SEL:
  140. return meson_set_gate_by_id(clk,
  141. meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
  142. }
  143. if (id >= ARRAY_SIZE(gates))
  144. return -ENOENT;
  145. gate = &gates[id];
  146. if (gate->reg == 0)
  147. return 0;
  148. debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
  149. regmap_update_bits(priv->map, gate->reg,
  150. BIT(gate->bit), on ? BIT(gate->bit) : 0);
  151. /* Propagate to next gate(s) */
  152. switch (id) {
  153. case CLKID_VAPB:
  154. return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
  155. case CLKID_VAPB_0:
  156. return meson_set_gate_by_id(clk,
  157. meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
  158. case CLKID_VAPB_1:
  159. return meson_set_gate_by_id(clk,
  160. meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
  161. case CLKID_VPU_0:
  162. return meson_set_gate_by_id(clk,
  163. meson_mux_get_parent(clk, CLKID_VPU_0_SEL), on);
  164. case CLKID_VPU_1:
  165. return meson_set_gate_by_id(clk,
  166. meson_mux_get_parent(clk, CLKID_VPU_1_SEL), on);
  167. }
  168. return 0;
  169. }
  170. static int meson_clk_enable(struct clk *clk)
  171. {
  172. return meson_set_gate_by_id(clk, clk->id, true);
  173. }
  174. static int meson_clk_disable(struct clk *clk)
  175. {
  176. return meson_set_gate_by_id(clk, clk->id, false);
  177. }
  178. static struct parm meson_vpu_0_div_parm = {
  179. HHI_VPU_CLK_CNTL, 0, 7,
  180. };
  181. int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
  182. static struct parm meson_vpu_1_div_parm = {
  183. HHI_VPU_CLK_CNTL, 16, 7,
  184. };
  185. int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
  186. static struct parm meson_vapb_0_div_parm = {
  187. HHI_VAPBCLK_CNTL, 0, 7,
  188. };
  189. int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
  190. static struct parm meson_vapb_1_div_parm = {
  191. HHI_VAPBCLK_CNTL, 16, 7,
  192. };
  193. int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
  194. static struct parm meson_hdmi_div_parm = {
  195. HHI_HDMI_CLK_CNTL, 0, 7,
  196. };
  197. int meson_hdmi_div_parent = CLKID_HDMI_SEL;
  198. static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
  199. {
  200. struct meson_clk *priv = dev_get_priv(clk->dev);
  201. unsigned int rate, parent_rate;
  202. struct parm *parm;
  203. int parent;
  204. uint reg;
  205. switch (id) {
  206. case CLKID_VPU_0_DIV:
  207. parm = &meson_vpu_0_div_parm;
  208. parent = meson_vpu_0_div_parent;
  209. break;
  210. case CLKID_VPU_1_DIV:
  211. parm = &meson_vpu_1_div_parm;
  212. parent = meson_vpu_1_div_parent;
  213. break;
  214. case CLKID_VAPB_0_DIV:
  215. parm = &meson_vapb_0_div_parm;
  216. parent = meson_vapb_0_div_parent;
  217. break;
  218. case CLKID_VAPB_1_DIV:
  219. parm = &meson_vapb_1_div_parm;
  220. parent = meson_vapb_1_div_parent;
  221. break;
  222. case CLKID_HDMI_DIV:
  223. parm = &meson_hdmi_div_parm;
  224. parent = meson_hdmi_div_parent;
  225. break;
  226. default:
  227. return -ENOENT;
  228. }
  229. regmap_read(priv->map, parm->reg_off, &reg);
  230. reg = PARM_GET(parm->width, parm->shift, reg);
  231. debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
  232. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  233. if (IS_ERR_VALUE(parent_rate))
  234. return parent_rate;
  235. debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
  236. rate = parent_rate / (reg + 1);
  237. debug("%s: rate of %ld is %d\n", __func__, id, rate);
  238. return rate;
  239. }
  240. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  241. ulong current_rate)
  242. {
  243. struct meson_clk *priv = dev_get_priv(clk->dev);
  244. unsigned int new_div = -EINVAL;
  245. unsigned long parent_rate;
  246. struct parm *parm;
  247. int parent;
  248. int ret;
  249. if (current_rate == rate)
  250. return 0;
  251. debug("%s: setting rate of %ld from %ld to %ld\n",
  252. __func__, id, current_rate, rate);
  253. switch (id) {
  254. case CLKID_VPU_0_DIV:
  255. parm = &meson_vpu_0_div_parm;
  256. parent = meson_vpu_0_div_parent;
  257. break;
  258. case CLKID_VPU_1_DIV:
  259. parm = &meson_vpu_1_div_parm;
  260. parent = meson_vpu_1_div_parent;
  261. break;
  262. case CLKID_VAPB_0_DIV:
  263. parm = &meson_vapb_0_div_parm;
  264. parent = meson_vapb_0_div_parent;
  265. break;
  266. case CLKID_VAPB_1_DIV:
  267. parm = &meson_vapb_1_div_parm;
  268. parent = meson_vapb_1_div_parent;
  269. break;
  270. case CLKID_HDMI_DIV:
  271. parm = &meson_hdmi_div_parm;
  272. parent = meson_hdmi_div_parent;
  273. break;
  274. default:
  275. return -ENOENT;
  276. }
  277. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  278. if (IS_ERR_VALUE(parent_rate))
  279. return parent_rate;
  280. debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
  281. /* If can't divide, set parent instead */
  282. if (!parent_rate || rate > parent_rate)
  283. return meson_clk_set_rate_by_id(clk, parent, rate,
  284. current_rate);
  285. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  286. debug("%s: new div of %ld is %d\n", __func__, id, new_div);
  287. /* If overflow, try to set parent rate and retry */
  288. if (!new_div || new_div > (1 << parm->width)) {
  289. ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
  290. if (IS_ERR_VALUE(ret))
  291. return ret;
  292. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  293. if (IS_ERR_VALUE(parent_rate))
  294. return parent_rate;
  295. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  296. debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
  297. if (!new_div || new_div > (1 << parm->width))
  298. return -EINVAL;
  299. }
  300. debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
  301. regmap_update_bits(priv->map, parm->reg_off,
  302. SETPMASK(parm->width, parm->shift),
  303. (new_div - 1) << parm->shift);
  304. debug("%s: new rate of %ld is %ld\n",
  305. __func__, id, meson_div_get_rate(clk, id));
  306. return 0;
  307. }
  308. static struct parm meson_vpu_mux_parm = {
  309. HHI_VPU_CLK_CNTL, 31, 1,
  310. };
  311. int meson_vpu_mux_parents[] = {
  312. CLKID_VPU_0,
  313. CLKID_VPU_1,
  314. };
  315. static struct parm meson_vpu_0_mux_parm = {
  316. HHI_VPU_CLK_CNTL, 9, 3,
  317. };
  318. static struct parm meson_vpu_1_mux_parm = {
  319. HHI_VPU_CLK_CNTL, 25, 3,
  320. };
  321. static int meson_vpu_0_1_mux_parents[] = {
  322. CLKID_FCLK_DIV3,
  323. CLKID_FCLK_DIV4,
  324. CLKID_FCLK_DIV5,
  325. CLKID_FCLK_DIV7,
  326. -ENOENT,
  327. -ENOENT,
  328. -ENOENT,
  329. -ENOENT,
  330. };
  331. static struct parm meson_vapb_sel_mux_parm = {
  332. HHI_VAPBCLK_CNTL, 31, 1,
  333. };
  334. int meson_vapb_sel_mux_parents[] = {
  335. CLKID_VAPB_0,
  336. CLKID_VAPB_1,
  337. };
  338. static struct parm meson_vapb_0_mux_parm = {
  339. HHI_VAPBCLK_CNTL, 9, 2,
  340. };
  341. static struct parm meson_vapb_1_mux_parm = {
  342. HHI_VAPBCLK_CNTL, 25, 2,
  343. };
  344. static int meson_vapb_0_1_mux_parents[] = {
  345. CLKID_FCLK_DIV4,
  346. CLKID_FCLK_DIV3,
  347. CLKID_FCLK_DIV5,
  348. CLKID_FCLK_DIV7,
  349. };
  350. static struct parm meson_hdmi_mux_parm = {
  351. HHI_HDMI_CLK_CNTL, 9, 2,
  352. };
  353. static int meson_hdmi_mux_parents[] = {
  354. CLKID_XTAL,
  355. CLKID_FCLK_DIV4,
  356. CLKID_FCLK_DIV3,
  357. CLKID_FCLK_DIV5,
  358. };
  359. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
  360. {
  361. struct meson_clk *priv = dev_get_priv(clk->dev);
  362. struct parm *parm;
  363. int *parents;
  364. uint reg;
  365. switch (id) {
  366. case CLKID_VPU:
  367. parm = &meson_vpu_mux_parm;
  368. parents = meson_vpu_mux_parents;
  369. break;
  370. case CLKID_VPU_0_SEL:
  371. parm = &meson_vpu_0_mux_parm;
  372. parents = meson_vpu_0_1_mux_parents;
  373. break;
  374. case CLKID_VPU_1_SEL:
  375. parm = &meson_vpu_1_mux_parm;
  376. parents = meson_vpu_0_1_mux_parents;
  377. break;
  378. case CLKID_VAPB_SEL:
  379. parm = &meson_vapb_sel_mux_parm;
  380. parents = meson_vapb_sel_mux_parents;
  381. break;
  382. case CLKID_VAPB_0_SEL:
  383. parm = &meson_vapb_0_mux_parm;
  384. parents = meson_vapb_0_1_mux_parents;
  385. break;
  386. case CLKID_VAPB_1_SEL:
  387. parm = &meson_vapb_1_mux_parm;
  388. parents = meson_vapb_0_1_mux_parents;
  389. break;
  390. case CLKID_HDMI_SEL:
  391. parm = &meson_hdmi_mux_parm;
  392. parents = meson_hdmi_mux_parents;
  393. break;
  394. default:
  395. return -ENOENT;
  396. }
  397. regmap_read(priv->map, parm->reg_off, &reg);
  398. reg = PARM_GET(parm->width, parm->shift, reg);
  399. debug("%s: parent of %ld is %d (%d)\n",
  400. __func__, id, parents[reg], reg);
  401. return parents[reg];
  402. }
  403. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  404. unsigned long parent_id)
  405. {
  406. unsigned long cur_parent = meson_mux_get_parent(clk, id);
  407. struct meson_clk *priv = dev_get_priv(clk->dev);
  408. unsigned int new_index = -EINVAL;
  409. struct parm *parm;
  410. int *parents;
  411. int i;
  412. if (IS_ERR_VALUE(cur_parent))
  413. return cur_parent;
  414. debug("%s: setting parent of %ld from %ld to %ld\n",
  415. __func__, id, cur_parent, parent_id);
  416. if (cur_parent == parent_id)
  417. return 0;
  418. switch (id) {
  419. case CLKID_VPU:
  420. parm = &meson_vpu_mux_parm;
  421. parents = meson_vpu_mux_parents;
  422. break;
  423. case CLKID_VPU_0_SEL:
  424. parm = &meson_vpu_0_mux_parm;
  425. parents = meson_vpu_0_1_mux_parents;
  426. break;
  427. case CLKID_VPU_1_SEL:
  428. parm = &meson_vpu_1_mux_parm;
  429. parents = meson_vpu_0_1_mux_parents;
  430. break;
  431. case CLKID_VAPB_SEL:
  432. parm = &meson_vapb_sel_mux_parm;
  433. parents = meson_vapb_sel_mux_parents;
  434. break;
  435. case CLKID_VAPB_0_SEL:
  436. parm = &meson_vapb_0_mux_parm;
  437. parents = meson_vapb_0_1_mux_parents;
  438. break;
  439. case CLKID_VAPB_1_SEL:
  440. parm = &meson_vapb_1_mux_parm;
  441. parents = meson_vapb_0_1_mux_parents;
  442. break;
  443. case CLKID_HDMI_SEL:
  444. parm = &meson_hdmi_mux_parm;
  445. parents = meson_hdmi_mux_parents;
  446. break;
  447. default:
  448. /* Not a mux */
  449. return -ENOENT;
  450. }
  451. for (i = 0 ; i < (1 << parm->width) ; ++i) {
  452. if (parents[i] == parent_id)
  453. new_index = i;
  454. }
  455. if (IS_ERR_VALUE(new_index))
  456. return new_index;
  457. debug("%s: new index of %ld is %d\n", __func__, id, new_index);
  458. regmap_update_bits(priv->map, parm->reg_off,
  459. SETPMASK(parm->width, parm->shift),
  460. new_index << parm->shift);
  461. debug("%s: new parent of %ld is %ld\n",
  462. __func__, id, meson_mux_get_parent(clk, id));
  463. return 0;
  464. }
  465. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
  466. {
  467. int parent = meson_mux_get_parent(clk, id);
  468. if (IS_ERR_VALUE(parent))
  469. return parent;
  470. return meson_clk_get_rate_by_id(clk, parent);
  471. }
  472. static unsigned long meson_clk81_get_rate(struct clk *clk)
  473. {
  474. struct meson_clk *priv = dev_get_priv(clk->dev);
  475. unsigned long parent_rate;
  476. uint reg;
  477. int parents[] = {
  478. CLKID_XTAL,
  479. -1,
  480. CLKID_FCLK_DIV7,
  481. CLKID_MPLL1,
  482. CLKID_MPLL2,
  483. CLKID_FCLK_DIV4,
  484. CLKID_FCLK_DIV3,
  485. CLKID_FCLK_DIV5
  486. };
  487. /* mux */
  488. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  489. reg = (reg >> 12) & 7;
  490. switch (reg) {
  491. case 1:
  492. return -ENOENT;
  493. default:
  494. parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
  495. }
  496. /* divider */
  497. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  498. reg = reg & ((1 << 7) - 1);
  499. return parent_rate / reg;
  500. }
  501. static long mpll_rate_from_params(unsigned long parent_rate,
  502. unsigned long sdm,
  503. unsigned long n2)
  504. {
  505. unsigned long divisor = (SDM_DEN * n2) + sdm;
  506. if (n2 < N2_MIN)
  507. return -EINVAL;
  508. return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  509. }
  510. static struct parm meson_mpll0_parm[2] = {
  511. {HHI_MPLL_CNTL1, 0, 14}, /* psdm */
  512. {HHI_MPLL_CNTL1, 20, 9}, /* pn2 */
  513. };
  514. static struct parm meson_mpll1_parm[2] = {
  515. {HHI_MPLL_CNTL3, 0, 14}, /* psdm */
  516. {HHI_MPLL_CNTL3, 20, 9}, /* pn2 */
  517. };
  518. static struct parm meson_mpll2_parm[2] = {
  519. {HHI_MPLL_CNTL5, 0, 14}, /* psdm */
  520. {HHI_MPLL_CNTL5, 20, 9}, /* pn2 */
  521. };
  522. /*
  523. * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  524. * scaling capabilities. MPLL rates are calculated as:
  525. *
  526. * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  527. */
  528. static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
  529. {
  530. struct meson_clk *priv = dev_get_priv(clk->dev);
  531. struct parm *psdm, *pn2;
  532. unsigned long sdm, n2;
  533. unsigned long parent_rate;
  534. uint reg;
  535. switch (id) {
  536. case CLKID_MPLL0:
  537. psdm = &meson_mpll0_parm[0];
  538. pn2 = &meson_mpll0_parm[1];
  539. break;
  540. case CLKID_MPLL1:
  541. psdm = &meson_mpll1_parm[0];
  542. pn2 = &meson_mpll1_parm[1];
  543. break;
  544. case CLKID_MPLL2:
  545. psdm = &meson_mpll2_parm[0];
  546. pn2 = &meson_mpll2_parm[1];
  547. break;
  548. default:
  549. return -ENOENT;
  550. }
  551. parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
  552. if (IS_ERR_VALUE(parent_rate))
  553. return parent_rate;
  554. regmap_read(priv->map, psdm->reg_off, &reg);
  555. sdm = PARM_GET(psdm->width, psdm->shift, reg);
  556. regmap_read(priv->map, pn2->reg_off, &reg);
  557. n2 = PARM_GET(pn2->width, pn2->shift, reg);
  558. return mpll_rate_from_params(parent_rate, sdm, n2);
  559. }
  560. static struct parm meson_fixed_pll_parm[4] = {
  561. {HHI_FIX_PLL_CNTL0, 0, 9}, /* pm */
  562. {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
  563. {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
  564. {HHI_FIX_PLL_CNTL1, 0, 17}, /* pfrac */
  565. };
  566. static struct parm meson_sys_pll_parm[3] = {
  567. {HHI_SYS_PLL_CNTL0, 0, 9}, /* pm */
  568. {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
  569. {HHI_SYS_PLL_CNTL0, 16, 3}, /* pod */
  570. };
  571. static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
  572. {
  573. struct meson_clk *priv = dev_get_priv(clk->dev);
  574. struct parm *pm, *pn, *pod, *pfrac = NULL;
  575. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  576. u16 n, m, od, frac;
  577. ulong rate;
  578. uint reg;
  579. /*
  580. * FIXME: Between the unit conversion and the missing frac, we know
  581. * rate will be slightly off ...
  582. */
  583. switch (id) {
  584. case CLKID_FIXED_PLL:
  585. pm = &meson_fixed_pll_parm[0];
  586. pn = &meson_fixed_pll_parm[1];
  587. pod = &meson_fixed_pll_parm[2];
  588. pfrac = &meson_fixed_pll_parm[3];
  589. break;
  590. case CLKID_SYS_PLL:
  591. pm = &meson_sys_pll_parm[0];
  592. pn = &meson_sys_pll_parm[1];
  593. pod = &meson_sys_pll_parm[2];
  594. break;
  595. default:
  596. return -ENOENT;
  597. }
  598. regmap_read(priv->map, pn->reg_off, &reg);
  599. n = PARM_GET(pn->width, pn->shift, reg);
  600. regmap_read(priv->map, pm->reg_off, &reg);
  601. m = PARM_GET(pm->width, pm->shift, reg);
  602. regmap_read(priv->map, pod->reg_off, &reg);
  603. od = PARM_GET(pod->width, pod->shift, reg);
  604. rate = parent_rate_mhz * m;
  605. if (pfrac) {
  606. ulong frac_rate;
  607. regmap_read(priv->map, pfrac->reg_off, &reg);
  608. frac = PARM_GET(pfrac->width - 1, pfrac->shift, reg);
  609. frac_rate = DIV_ROUND_UP_ULL((u64)parent_rate_mhz * frac,
  610. 1 << (pfrac->width - 2));
  611. if (frac & BIT(pfrac->width - 1))
  612. rate -= frac_rate;
  613. else
  614. rate += frac_rate;
  615. }
  616. return (DIV_ROUND_UP_ULL(rate, n) >> od) * 1000000;
  617. }
  618. static struct parm meson_pcie_pll_parm[3] = {
  619. {HHI_PCIE_PLL_CNTL0, 0, 8}, /* pm */
  620. {HHI_PCIE_PLL_CNTL0, 10, 5}, /* pn */
  621. {HHI_PCIE_PLL_CNTL0, 16, 5}, /* pod */
  622. };
  623. static ulong meson_pcie_pll_get_rate(struct clk *clk)
  624. {
  625. struct meson_clk *priv = dev_get_priv(clk->dev);
  626. struct parm *pm, *pn, *pod;
  627. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  628. u16 n, m, od;
  629. uint reg;
  630. pm = &meson_pcie_pll_parm[0];
  631. pn = &meson_pcie_pll_parm[1];
  632. pod = &meson_pcie_pll_parm[2];
  633. regmap_read(priv->map, pn->reg_off, &reg);
  634. n = PARM_GET(pn->width, pn->shift, reg);
  635. regmap_read(priv->map, pm->reg_off, &reg);
  636. m = PARM_GET(pm->width, pm->shift, reg);
  637. regmap_read(priv->map, pod->reg_off, &reg);
  638. od = PARM_GET(pod->width, pod->shift, reg);
  639. return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
  640. }
  641. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
  642. {
  643. ulong rate;
  644. switch (id) {
  645. case CLKID_XTAL:
  646. rate = XTAL_RATE;
  647. break;
  648. case CLKID_FIXED_PLL:
  649. case CLKID_SYS_PLL:
  650. rate = meson_pll_get_rate(clk, id);
  651. break;
  652. case CLKID_FCLK_DIV2:
  653. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
  654. break;
  655. case CLKID_FCLK_DIV3:
  656. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
  657. break;
  658. case CLKID_FCLK_DIV4:
  659. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
  660. break;
  661. case CLKID_FCLK_DIV5:
  662. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
  663. break;
  664. case CLKID_FCLK_DIV7:
  665. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
  666. break;
  667. case CLKID_MPLL0:
  668. case CLKID_MPLL1:
  669. case CLKID_MPLL2:
  670. rate = meson_mpll_get_rate(clk, id);
  671. break;
  672. case CLKID_CLK81:
  673. rate = meson_clk81_get_rate(clk);
  674. break;
  675. case CLKID_PCIE_PLL:
  676. rate = meson_pcie_pll_get_rate(clk);
  677. break;
  678. case CLKID_VPU_0:
  679. rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
  680. break;
  681. case CLKID_VPU_1:
  682. rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
  683. break;
  684. case CLKID_VAPB:
  685. rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
  686. break;
  687. case CLKID_VAPB_0:
  688. rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
  689. break;
  690. case CLKID_VAPB_1:
  691. rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
  692. break;
  693. case CLKID_HDMI:
  694. rate = meson_div_get_rate(clk, CLKID_HDMI_DIV);
  695. break;
  696. case CLKID_VPU_0_DIV:
  697. case CLKID_VPU_1_DIV:
  698. case CLKID_VAPB_0_DIV:
  699. case CLKID_VAPB_1_DIV:
  700. case CLKID_HDMI_DIV:
  701. rate = meson_div_get_rate(clk, id);
  702. break;
  703. case CLKID_VPU:
  704. case CLKID_VPU_0_SEL:
  705. case CLKID_VPU_1_SEL:
  706. case CLKID_VAPB_SEL:
  707. case CLKID_VAPB_0_SEL:
  708. case CLKID_VAPB_1_SEL:
  709. case CLKID_HDMI_SEL:
  710. rate = meson_mux_get_rate(clk, id);
  711. break;
  712. default:
  713. if (gates[id].reg != 0) {
  714. /* a clock gate */
  715. rate = meson_clk81_get_rate(clk);
  716. break;
  717. }
  718. return -ENOENT;
  719. }
  720. debug("clock %lu has rate %lu\n", id, rate);
  721. return rate;
  722. }
  723. static ulong meson_clk_get_rate(struct clk *clk)
  724. {
  725. return meson_clk_get_rate_by_id(clk, clk->id);
  726. }
  727. static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)
  728. {
  729. struct meson_clk *priv = dev_get_priv(clk->dev);
  730. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
  731. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
  732. regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
  733. regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
  734. regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
  735. regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
  736. regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
  737. regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
  738. udelay(20);
  739. regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
  740. udelay(10);
  741. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
  742. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
  743. udelay(10);
  744. regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
  745. regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
  746. 0x1f << 16, 9 << 16);
  747. return 100000000;
  748. }
  749. static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
  750. {
  751. return meson_mux_set_parent(clk, clk->id, parent->id);
  752. }
  753. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  754. ulong rate, ulong current_rate)
  755. {
  756. if (current_rate == rate)
  757. return 0;
  758. switch (id) {
  759. /* Fixed clocks */
  760. case CLKID_FIXED_PLL:
  761. case CLKID_SYS_PLL:
  762. case CLKID_FCLK_DIV2:
  763. case CLKID_FCLK_DIV3:
  764. case CLKID_FCLK_DIV4:
  765. case CLKID_FCLK_DIV5:
  766. case CLKID_FCLK_DIV7:
  767. case CLKID_MPLL0:
  768. case CLKID_MPLL1:
  769. case CLKID_MPLL2:
  770. case CLKID_CLK81:
  771. if (current_rate != rate)
  772. return -EINVAL;
  773. case CLKID_PCIE_PLL:
  774. return meson_pcie_pll_set_rate(clk, rate);
  775. return 0;
  776. case CLKID_VPU:
  777. return meson_clk_set_rate_by_id(clk,
  778. meson_mux_get_parent(clk, CLKID_VPU), rate,
  779. current_rate);
  780. case CLKID_VAPB:
  781. case CLKID_VAPB_SEL:
  782. return meson_clk_set_rate_by_id(clk,
  783. meson_mux_get_parent(clk, CLKID_VAPB_SEL),
  784. rate, current_rate);
  785. case CLKID_VPU_0:
  786. return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
  787. current_rate);
  788. case CLKID_VPU_1:
  789. return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
  790. current_rate);
  791. case CLKID_VAPB_0:
  792. return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
  793. current_rate);
  794. case CLKID_VAPB_1:
  795. return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
  796. current_rate);
  797. case CLKID_VPU_0_DIV:
  798. case CLKID_VPU_1_DIV:
  799. case CLKID_VAPB_0_DIV:
  800. case CLKID_VAPB_1_DIV:
  801. case CLKID_HDMI_DIV:
  802. return meson_div_set_rate(clk, id, rate, current_rate);
  803. case CLKID_HDMI:
  804. return meson_clk_set_rate_by_id(clk, CLKID_HDMI_DIV,
  805. rate, current_rate);
  806. default:
  807. return -ENOENT;
  808. }
  809. return -EINVAL;
  810. }
  811. static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
  812. {
  813. ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
  814. int ret;
  815. if (IS_ERR_VALUE(current_rate))
  816. return current_rate;
  817. debug("%s: setting rate of %ld from %ld to %ld\n",
  818. __func__, clk->id, current_rate, rate);
  819. ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
  820. if (IS_ERR_VALUE(ret))
  821. return ret;
  822. debug("clock %lu has new rate %lu\n", clk->id,
  823. meson_clk_get_rate_by_id(clk, clk->id));
  824. return 0;
  825. }
  826. static int meson_clk_probe(struct udevice *dev)
  827. {
  828. struct meson_clk *priv = dev_get_priv(dev);
  829. priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
  830. if (IS_ERR(priv->map))
  831. return PTR_ERR(priv->map);
  832. /*
  833. * Depending on the boot src, the state of the MMC clock might
  834. * be different. Reset it to make sure we won't get stuck
  835. */
  836. regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
  837. regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
  838. debug("meson-clk-g12a: probed\n");
  839. return 0;
  840. }
  841. static struct clk_ops meson_clk_ops = {
  842. .disable = meson_clk_disable,
  843. .enable = meson_clk_enable,
  844. .get_rate = meson_clk_get_rate,
  845. .set_parent = meson_clk_set_parent,
  846. .set_rate = meson_clk_set_rate,
  847. };
  848. static const struct udevice_id meson_clk_ids[] = {
  849. { .compatible = "amlogic,g12a-clkc" },
  850. { .compatible = "amlogic,g12b-clkc" },
  851. { .compatible = "amlogic,sm1-clkc" },
  852. { }
  853. };
  854. U_BOOT_DRIVER(meson_clk_g12a) = {
  855. .name = "meson_clk_g12a",
  856. .id = UCLASS_CLK,
  857. .of_match = meson_clk_ids,
  858. .priv_auto_alloc_size = sizeof(struct meson_clk),
  859. .ops = &meson_clk_ops,
  860. .probe = meson_clk_probe,
  861. };