axg.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 - BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock-axg.h>
  9. #include <asm/io.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <div64.h>
  15. #include <dt-bindings/clock/axg-clkc.h>
  16. #include "clk_meson.h"
  17. #include <linux/err.h>
  18. #define XTAL_RATE 24000000
  19. struct meson_clk {
  20. struct regmap *map;
  21. };
  22. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  23. static struct meson_gate gates[] = {
  24. /* Everything Else (EE) domain gates */
  25. MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
  26. MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  27. MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  28. MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 15),
  29. MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
  30. MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
  31. MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
  32. MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
  33. /* Always On (AO) domain gates */
  34. MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
  35. /* PLL Gates */
  36. /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
  37. MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
  38. /* CLKID_CLK81 is critical for the system */
  39. /* Peripheral Gates */
  40. MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
  41. MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
  42. };
  43. static int meson_set_gate(struct clk *clk, bool on)
  44. {
  45. struct meson_clk *priv = dev_get_priv(clk->dev);
  46. struct meson_gate *gate;
  47. if (clk->id >= ARRAY_SIZE(gates))
  48. return -ENOENT;
  49. gate = &gates[clk->id];
  50. if (gate->reg == 0)
  51. return 0;
  52. regmap_update_bits(priv->map, gate->reg,
  53. BIT(gate->bit), on ? BIT(gate->bit) : 0);
  54. return 0;
  55. }
  56. static int meson_clk_enable(struct clk *clk)
  57. {
  58. return meson_set_gate(clk, true);
  59. }
  60. static int meson_clk_disable(struct clk *clk)
  61. {
  62. return meson_set_gate(clk, false);
  63. }
  64. static unsigned long meson_clk81_get_rate(struct clk *clk)
  65. {
  66. struct meson_clk *priv = dev_get_priv(clk->dev);
  67. unsigned long parent_rate;
  68. uint reg;
  69. int parents[] = {
  70. -1,
  71. -1,
  72. CLKID_FCLK_DIV7,
  73. CLKID_MPLL1,
  74. CLKID_MPLL2,
  75. CLKID_FCLK_DIV4,
  76. CLKID_FCLK_DIV3,
  77. CLKID_FCLK_DIV5
  78. };
  79. /* mux */
  80. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  81. reg = (reg >> 12) & 7;
  82. switch (reg) {
  83. case 0:
  84. parent_rate = XTAL_RATE;
  85. break;
  86. case 1:
  87. return -ENOENT;
  88. default:
  89. parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
  90. }
  91. /* divider */
  92. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  93. reg = reg & ((1 << 7) - 1);
  94. return parent_rate / reg;
  95. }
  96. static long mpll_rate_from_params(unsigned long parent_rate,
  97. unsigned long sdm,
  98. unsigned long n2)
  99. {
  100. unsigned long divisor = (SDM_DEN * n2) + sdm;
  101. if (n2 < N2_MIN)
  102. return -EINVAL;
  103. return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  104. }
  105. static struct parm meson_mpll0_parm[3] = {
  106. {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
  107. {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
  108. };
  109. static struct parm meson_mpll1_parm[3] = {
  110. {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
  111. {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
  112. };
  113. static struct parm meson_mpll2_parm[3] = {
  114. {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
  115. {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
  116. };
  117. /*
  118. * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  119. * scaling capabilities. MPLL rates are calculated as:
  120. *
  121. * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  122. */
  123. static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
  124. {
  125. struct meson_clk *priv = dev_get_priv(clk->dev);
  126. struct parm *psdm, *pn2;
  127. unsigned long sdm, n2;
  128. unsigned long parent_rate;
  129. uint reg;
  130. switch (id) {
  131. case CLKID_MPLL0:
  132. psdm = &meson_mpll0_parm[0];
  133. pn2 = &meson_mpll0_parm[1];
  134. break;
  135. case CLKID_MPLL1:
  136. psdm = &meson_mpll1_parm[0];
  137. pn2 = &meson_mpll1_parm[1];
  138. break;
  139. case CLKID_MPLL2:
  140. psdm = &meson_mpll2_parm[0];
  141. pn2 = &meson_mpll2_parm[1];
  142. break;
  143. default:
  144. return -ENOENT;
  145. }
  146. parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
  147. if (IS_ERR_VALUE(parent_rate))
  148. return parent_rate;
  149. regmap_read(priv->map, psdm->reg_off, &reg);
  150. sdm = PARM_GET(psdm->width, psdm->shift, reg);
  151. regmap_read(priv->map, pn2->reg_off, &reg);
  152. n2 = PARM_GET(pn2->width, pn2->shift, reg);
  153. return mpll_rate_from_params(parent_rate, sdm, n2);
  154. }
  155. static struct parm meson_fixed_pll_parm[3] = {
  156. {HHI_MPLL_CNTL, 0, 9}, /* pm */
  157. {HHI_MPLL_CNTL, 9, 5}, /* pn */
  158. {HHI_MPLL_CNTL, 16, 2}, /* pod */
  159. };
  160. static struct parm meson_sys_pll_parm[3] = {
  161. {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
  162. {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
  163. {HHI_SYS_PLL_CNTL, 16, 2}, /* pod */
  164. };
  165. static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
  166. {
  167. struct meson_clk *priv = dev_get_priv(clk->dev);
  168. struct parm *pm, *pn, *pod;
  169. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  170. u16 n, m, od;
  171. uint reg;
  172. switch (id) {
  173. case CLKID_FIXED_PLL:
  174. pm = &meson_fixed_pll_parm[0];
  175. pn = &meson_fixed_pll_parm[1];
  176. pod = &meson_fixed_pll_parm[2];
  177. break;
  178. case CLKID_SYS_PLL:
  179. pm = &meson_sys_pll_parm[0];
  180. pn = &meson_sys_pll_parm[1];
  181. pod = &meson_sys_pll_parm[2];
  182. break;
  183. default:
  184. return -ENOENT;
  185. }
  186. regmap_read(priv->map, pn->reg_off, &reg);
  187. n = PARM_GET(pn->width, pn->shift, reg);
  188. regmap_read(priv->map, pm->reg_off, &reg);
  189. m = PARM_GET(pm->width, pm->shift, reg);
  190. regmap_read(priv->map, pod->reg_off, &reg);
  191. od = PARM_GET(pod->width, pod->shift, reg);
  192. return ((parent_rate_mhz * m / n) >> od) * 1000000;
  193. }
  194. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
  195. {
  196. ulong rate;
  197. switch (id) {
  198. case CLKID_FIXED_PLL:
  199. case CLKID_SYS_PLL:
  200. rate = meson_pll_get_rate(clk, id);
  201. break;
  202. case CLKID_FCLK_DIV2:
  203. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
  204. break;
  205. case CLKID_FCLK_DIV3:
  206. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
  207. break;
  208. case CLKID_FCLK_DIV4:
  209. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
  210. break;
  211. case CLKID_FCLK_DIV5:
  212. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
  213. break;
  214. case CLKID_FCLK_DIV7:
  215. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
  216. break;
  217. case CLKID_MPLL0:
  218. case CLKID_MPLL1:
  219. case CLKID_MPLL2:
  220. rate = meson_mpll_get_rate(clk, id);
  221. break;
  222. case CLKID_CLK81:
  223. rate = meson_clk81_get_rate(clk);
  224. break;
  225. default:
  226. if (gates[id].reg != 0) {
  227. /* a clock gate */
  228. rate = meson_clk81_get_rate(clk);
  229. break;
  230. }
  231. return -ENOENT;
  232. }
  233. debug("clock %lu has rate %lu\n", id, rate);
  234. return rate;
  235. }
  236. static ulong meson_clk_get_rate(struct clk *clk)
  237. {
  238. return meson_clk_get_rate_by_id(clk, clk->id);
  239. }
  240. static int meson_clk_probe(struct udevice *dev)
  241. {
  242. struct meson_clk *priv = dev_get_priv(dev);
  243. priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
  244. if (IS_ERR(priv->map))
  245. return PTR_ERR(priv->map);
  246. /*
  247. * Depending on the boot src, the state of the MMC clock might
  248. * be different. Reset it to make sure we won't get stuck
  249. */
  250. regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
  251. regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
  252. debug("meson-clk-axg: probed\n");
  253. return 0;
  254. }
  255. static struct clk_ops meson_clk_ops = {
  256. .disable = meson_clk_disable,
  257. .enable = meson_clk_enable,
  258. .get_rate = meson_clk_get_rate,
  259. };
  260. static const struct udevice_id meson_clk_ids[] = {
  261. { .compatible = "amlogic,axg-clkc" },
  262. { }
  263. };
  264. U_BOOT_DRIVER(meson_clk_axg) = {
  265. .name = "meson_clk_axg",
  266. .id = UCLASS_CLK,
  267. .of_match = meson_clk_ids,
  268. .priv_auto_alloc_size = sizeof(struct meson_clk),
  269. .ops = &meson_clk_ops,
  270. .probe = meson_clk_probe,
  271. };