meson-gx.dtsi 14 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2016 Andreas Färber
  4. *
  5. * Copyright (c) 2016 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. *
  8. * Copyright (c) 2016 Endless Computers, Inc.
  9. * Author: Carlo Caione <carlo@endlessm.com>
  10. */
  11. #include <dt-bindings/gpio/gpio.h>
  12. #include <dt-bindings/interrupt-controller/irq.h>
  13. #include <dt-bindings/interrupt-controller/arm-gic.h>
  14. / {
  15. interrupt-parent = <&gic>;
  16. #address-cells = <2>;
  17. #size-cells = <2>;
  18. reserved-memory {
  19. #address-cells = <2>;
  20. #size-cells = <2>;
  21. ranges;
  22. /* 16 MiB reserved for Hardware ROM Firmware */
  23. hwrom_reserved: hwrom@0 {
  24. reg = <0x0 0x0 0x0 0x1000000>;
  25. no-map;
  26. };
  27. /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
  28. secmon_reserved: secmon@10000000 {
  29. reg = <0x0 0x10000000 0x0 0x200000>;
  30. no-map;
  31. };
  32. /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  33. secmon_reserved_alt: secmon@5000000 {
  34. reg = <0x0 0x05000000 0x0 0x300000>;
  35. no-map;
  36. };
  37. linux,cma {
  38. compatible = "shared-dma-pool";
  39. reusable;
  40. size = <0x0 0x10000000>;
  41. alignment = <0x0 0x400000>;
  42. linux,cma-default;
  43. };
  44. };
  45. chosen {
  46. #address-cells = <2>;
  47. #size-cells = <2>;
  48. ranges;
  49. simplefb_cvbs: framebuffer-cvbs {
  50. compatible = "amlogic,simple-framebuffer",
  51. "simple-framebuffer";
  52. amlogic,pipeline = "vpu-cvbs";
  53. power-domains = <&pwrc_vpu>;
  54. status = "disabled";
  55. };
  56. simplefb_hdmi: framebuffer-hdmi {
  57. compatible = "amlogic,simple-framebuffer",
  58. "simple-framebuffer";
  59. amlogic,pipeline = "vpu-hdmi";
  60. power-domains = <&pwrc_vpu>;
  61. status = "disabled";
  62. };
  63. };
  64. cpus {
  65. #address-cells = <0x2>;
  66. #size-cells = <0x0>;
  67. cpu0: cpu@0 {
  68. device_type = "cpu";
  69. compatible = "arm,cortex-a53";
  70. reg = <0x0 0x0>;
  71. enable-method = "psci";
  72. next-level-cache = <&l2>;
  73. clocks = <&scpi_dvfs 0>;
  74. };
  75. cpu1: cpu@1 {
  76. device_type = "cpu";
  77. compatible = "arm,cortex-a53";
  78. reg = <0x0 0x1>;
  79. enable-method = "psci";
  80. next-level-cache = <&l2>;
  81. clocks = <&scpi_dvfs 0>;
  82. };
  83. cpu2: cpu@2 {
  84. device_type = "cpu";
  85. compatible = "arm,cortex-a53";
  86. reg = <0x0 0x2>;
  87. enable-method = "psci";
  88. next-level-cache = <&l2>;
  89. clocks = <&scpi_dvfs 0>;
  90. };
  91. cpu3: cpu@3 {
  92. device_type = "cpu";
  93. compatible = "arm,cortex-a53";
  94. reg = <0x0 0x3>;
  95. enable-method = "psci";
  96. next-level-cache = <&l2>;
  97. clocks = <&scpi_dvfs 0>;
  98. };
  99. l2: l2-cache0 {
  100. compatible = "cache";
  101. };
  102. };
  103. arm-pmu {
  104. compatible = "arm,cortex-a53-pmu";
  105. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  106. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  107. <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  108. <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  109. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  110. };
  111. psci {
  112. compatible = "arm,psci-0.2";
  113. method = "smc";
  114. };
  115. timer {
  116. compatible = "arm,armv8-timer";
  117. interrupts = <GIC_PPI 13
  118. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  119. <GIC_PPI 14
  120. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  121. <GIC_PPI 11
  122. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  123. <GIC_PPI 10
  124. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  125. };
  126. xtal: xtal-clk {
  127. compatible = "fixed-clock";
  128. clock-frequency = <24000000>;
  129. clock-output-names = "xtal";
  130. #clock-cells = <0>;
  131. };
  132. firmware {
  133. sm: secure-monitor {
  134. compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
  135. };
  136. };
  137. efuse: efuse {
  138. compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
  139. #address-cells = <1>;
  140. #size-cells = <1>;
  141. read-only;
  142. secure-monitor = <&sm>;
  143. sn: sn@14 {
  144. reg = <0x14 0x10>;
  145. };
  146. eth_mac: eth_mac@34 {
  147. reg = <0x34 0x10>;
  148. };
  149. bid: bid@46 {
  150. reg = <0x46 0x30>;
  151. };
  152. };
  153. scpi {
  154. compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
  155. mboxes = <&mailbox 1 &mailbox 2>;
  156. shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
  157. scpi_clocks: clocks {
  158. compatible = "arm,scpi-clocks";
  159. scpi_dvfs: scpi_clocks@0 {
  160. compatible = "arm,scpi-dvfs-clocks";
  161. #clock-cells = <1>;
  162. clock-indices = <0>;
  163. clock-output-names = "vcpu";
  164. };
  165. };
  166. scpi_sensors: sensors {
  167. compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
  168. #thermal-sensor-cells = <1>;
  169. };
  170. };
  171. soc {
  172. compatible = "simple-bus";
  173. #address-cells = <2>;
  174. #size-cells = <2>;
  175. ranges;
  176. cbus: bus@c1100000 {
  177. compatible = "simple-bus";
  178. reg = <0x0 0xc1100000 0x0 0x100000>;
  179. #address-cells = <2>;
  180. #size-cells = <2>;
  181. ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
  182. gpio_intc: interrupt-controller@9880 {
  183. compatible = "amlogic,meson-gpio-intc";
  184. reg = <0x0 0x9880 0x0 0x10>;
  185. interrupt-controller;
  186. #interrupt-cells = <2>;
  187. amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
  188. status = "disabled";
  189. };
  190. reset: reset-controller@4404 {
  191. compatible = "amlogic,meson-gxbb-reset";
  192. reg = <0x0 0x04404 0x0 0x9c>;
  193. #reset-cells = <1>;
  194. };
  195. uart_A: serial@84c0 {
  196. compatible = "amlogic,meson-gx-uart";
  197. reg = <0x0 0x84c0 0x0 0x18>;
  198. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  199. status = "disabled";
  200. };
  201. uart_B: serial@84dc {
  202. compatible = "amlogic,meson-gx-uart";
  203. reg = <0x0 0x84dc 0x0 0x18>;
  204. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  205. status = "disabled";
  206. };
  207. i2c_A: i2c@8500 {
  208. compatible = "amlogic,meson-gxbb-i2c";
  209. reg = <0x0 0x08500 0x0 0x20>;
  210. interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. status = "disabled";
  214. };
  215. pwm_ab: pwm@8550 {
  216. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  217. reg = <0x0 0x08550 0x0 0x10>;
  218. #pwm-cells = <3>;
  219. status = "disabled";
  220. };
  221. pwm_cd: pwm@8650 {
  222. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  223. reg = <0x0 0x08650 0x0 0x10>;
  224. #pwm-cells = <3>;
  225. status = "disabled";
  226. };
  227. saradc: adc@8680 {
  228. compatible = "amlogic,meson-saradc";
  229. reg = <0x0 0x8680 0x0 0x34>;
  230. #io-channel-cells = <1>;
  231. interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
  232. status = "disabled";
  233. };
  234. pwm_ef: pwm@86c0 {
  235. compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
  236. reg = <0x0 0x086c0 0x0 0x10>;
  237. #pwm-cells = <3>;
  238. status = "disabled";
  239. };
  240. uart_C: serial@8700 {
  241. compatible = "amlogic,meson-gx-uart";
  242. reg = <0x0 0x8700 0x0 0x18>;
  243. interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
  244. status = "disabled";
  245. };
  246. clock-measure@8758 {
  247. compatible = "amlogic,meson-gx-clk-measure";
  248. reg = <0x0 0x8758 0x0 0x10>;
  249. };
  250. i2c_B: i2c@87c0 {
  251. compatible = "amlogic,meson-gxbb-i2c";
  252. reg = <0x0 0x087c0 0x0 0x20>;
  253. interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
  254. #address-cells = <1>;
  255. #size-cells = <0>;
  256. status = "disabled";
  257. };
  258. i2c_C: i2c@87e0 {
  259. compatible = "amlogic,meson-gxbb-i2c";
  260. reg = <0x0 0x087e0 0x0 0x20>;
  261. interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
  262. #address-cells = <1>;
  263. #size-cells = <0>;
  264. status = "disabled";
  265. };
  266. spicc: spi@8d80 {
  267. compatible = "amlogic,meson-gx-spicc";
  268. reg = <0x0 0x08d80 0x0 0x80>;
  269. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. status = "disabled";
  273. };
  274. spifc: spi@8c80 {
  275. compatible = "amlogic,meson-gxbb-spifc";
  276. reg = <0x0 0x08c80 0x0 0x80>;
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. status = "disabled";
  280. };
  281. watchdog@98d0 {
  282. compatible = "amlogic,meson-gxbb-wdt";
  283. reg = <0x0 0x098d0 0x0 0x10>;
  284. clocks = <&xtal>;
  285. };
  286. };
  287. gic: interrupt-controller@c4301000 {
  288. compatible = "arm,gic-400";
  289. reg = <0x0 0xc4301000 0 0x1000>,
  290. <0x0 0xc4302000 0 0x2000>,
  291. <0x0 0xc4304000 0 0x2000>,
  292. <0x0 0xc4306000 0 0x2000>;
  293. interrupt-controller;
  294. interrupts = <GIC_PPI 9
  295. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  296. #interrupt-cells = <3>;
  297. #address-cells = <0>;
  298. };
  299. sram: sram@c8000000 {
  300. compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
  301. reg = <0x0 0xc8000000 0x0 0x14000>;
  302. #address-cells = <1>;
  303. #size-cells = <1>;
  304. ranges = <0 0x0 0xc8000000 0x14000>;
  305. cpu_scp_lpri: scp-shmem@0 {
  306. compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
  307. reg = <0x13000 0x400>;
  308. };
  309. cpu_scp_hpri: scp-shmem@200 {
  310. compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
  311. reg = <0x13400 0x400>;
  312. };
  313. };
  314. aobus: bus@c8100000 {
  315. compatible = "simple-bus";
  316. reg = <0x0 0xc8100000 0x0 0x100000>;
  317. #address-cells = <2>;
  318. #size-cells = <2>;
  319. ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
  320. sysctrl_AO: sys-ctrl@0 {
  321. compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
  322. reg = <0x0 0x0 0x0 0x100>;
  323. pwrc_vpu: power-controller-vpu {
  324. compatible = "amlogic,meson-gx-pwrc-vpu";
  325. #power-domain-cells = <0>;
  326. amlogic,hhi-sysctrl = <&sysctrl>;
  327. };
  328. clkc_AO: clock-controller {
  329. compatible = "amlogic,meson-gx-aoclkc";
  330. #clock-cells = <1>;
  331. #reset-cells = <1>;
  332. };
  333. };
  334. cec_AO: cec@100 {
  335. compatible = "amlogic,meson-gx-ao-cec";
  336. reg = <0x0 0x00100 0x0 0x14>;
  337. interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
  338. status = "disabled";
  339. };
  340. sec_AO: ao-secure@140 {
  341. compatible = "amlogic,meson-gx-ao-secure", "syscon";
  342. reg = <0x0 0x140 0x0 0x140>;
  343. amlogic,has-chip-id;
  344. };
  345. uart_AO: serial@4c0 {
  346. compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
  347. reg = <0x0 0x004c0 0x0 0x18>;
  348. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  349. status = "disabled";
  350. };
  351. uart_AO_B: serial@4e0 {
  352. compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
  353. reg = <0x0 0x004e0 0x0 0x18>;
  354. interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
  355. status = "disabled";
  356. };
  357. i2c_AO: i2c@500 {
  358. compatible = "amlogic,meson-gxbb-i2c";
  359. reg = <0x0 0x500 0x0 0x20>;
  360. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  361. #address-cells = <1>;
  362. #size-cells = <0>;
  363. status = "disabled";
  364. };
  365. pwm_AO_ab: pwm@550 {
  366. compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
  367. reg = <0x0 0x00550 0x0 0x10>;
  368. #pwm-cells = <3>;
  369. status = "disabled";
  370. };
  371. ir: ir@580 {
  372. compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
  373. reg = <0x0 0x00580 0x0 0x40>;
  374. interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
  375. status = "disabled";
  376. };
  377. };
  378. vdec: video-codec@c8820000 {
  379. compatible = "amlogic,gx-vdec";
  380. reg = <0x0 0xc8820000 0x0 0x10000>,
  381. <0x0 0xc110a580 0x0 0xe4>;
  382. reg-names = "dos", "esparser";
  383. interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
  384. <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
  385. interrupt-names = "vdec", "esparser";
  386. amlogic,ao-sysctrl = <&sysctrl_AO>;
  387. amlogic,canvas = <&canvas>;
  388. };
  389. periphs: bus@c8834000 {
  390. compatible = "simple-bus";
  391. reg = <0x0 0xc8834000 0x0 0x2000>;
  392. #address-cells = <2>;
  393. #size-cells = <2>;
  394. ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
  395. hwrng: rng {
  396. compatible = "amlogic,meson-rng";
  397. reg = <0x0 0x0 0x0 0x4>;
  398. };
  399. };
  400. dmcbus: bus@c8838000 {
  401. compatible = "simple-bus";
  402. reg = <0x0 0xc8838000 0x0 0x400>;
  403. #address-cells = <2>;
  404. #size-cells = <2>;
  405. ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
  406. canvas: video-lut@48 {
  407. compatible = "amlogic,canvas";
  408. reg = <0x0 0x48 0x0 0x14>;
  409. };
  410. };
  411. hiubus: bus@c883c000 {
  412. compatible = "simple-bus";
  413. reg = <0x0 0xc883c000 0x0 0x2000>;
  414. #address-cells = <2>;
  415. #size-cells = <2>;
  416. ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
  417. sysctrl: system-controller@0 {
  418. compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
  419. reg = <0 0 0 0x400>;
  420. };
  421. mailbox: mailbox@404 {
  422. compatible = "amlogic,meson-gxbb-mhu";
  423. reg = <0 0x404 0 0x4c>;
  424. interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
  425. <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
  426. <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
  427. #mbox-cells = <1>;
  428. };
  429. };
  430. ethmac: ethernet@c9410000 {
  431. compatible = "amlogic,meson-gxbb-dwmac",
  432. "snps,dwmac-3.70a",
  433. "snps,dwmac";
  434. reg = <0x0 0xc9410000 0x0 0x10000>,
  435. <0x0 0xc8834540 0x0 0x4>;
  436. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  437. interrupt-names = "macirq";
  438. rx-fifo-depth = <4096>;
  439. tx-fifo-depth = <2048>;
  440. status = "disabled";
  441. };
  442. apb: apb@d0000000 {
  443. compatible = "simple-bus";
  444. reg = <0x0 0xd0000000 0x0 0x200000>;
  445. #address-cells = <2>;
  446. #size-cells = <2>;
  447. ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
  448. sd_emmc_a: mmc@70000 {
  449. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  450. reg = <0x0 0x70000 0x0 0x800>;
  451. interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
  452. status = "disabled";
  453. };
  454. sd_emmc_b: mmc@72000 {
  455. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  456. reg = <0x0 0x72000 0x0 0x800>;
  457. interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
  458. status = "disabled";
  459. };
  460. sd_emmc_c: mmc@74000 {
  461. compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
  462. reg = <0x0 0x74000 0x0 0x800>;
  463. interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
  464. status = "disabled";
  465. };
  466. };
  467. vpu: vpu@d0100000 {
  468. compatible = "amlogic,meson-gx-vpu";
  469. reg = <0x0 0xd0100000 0x0 0x100000>,
  470. <0x0 0xc883c000 0x0 0x1000>;
  471. reg-names = "vpu", "hhi";
  472. interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
  473. #address-cells = <1>;
  474. #size-cells = <0>;
  475. amlogic,canvas = <&canvas>;
  476. /* CVBS VDAC output port */
  477. cvbs_vdac_port: port@0 {
  478. reg = <0>;
  479. };
  480. /* HDMI-TX output port */
  481. hdmi_tx_port: port@1 {
  482. reg = <1>;
  483. hdmi_tx_out: endpoint {
  484. remote-endpoint = <&hdmi_tx_in>;
  485. };
  486. };
  487. };
  488. hdmi_tx: hdmi-tx@c883a000 {
  489. compatible = "amlogic,meson-gx-dw-hdmi";
  490. reg = <0x0 0xc883a000 0x0 0x1c>;
  491. interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
  492. #address-cells = <1>;
  493. #size-cells = <0>;
  494. status = "disabled";
  495. /* VPU VENC Input */
  496. hdmi_tx_venc_port: port@0 {
  497. reg = <0>;
  498. hdmi_tx_in: endpoint {
  499. remote-endpoint = <&hdmi_tx_out>;
  500. };
  501. };
  502. /* TMDS Output */
  503. hdmi_tx_tmds_port: port@1 {
  504. reg = <1>;
  505. };
  506. };
  507. };
  508. };