meson-g12-common.dtsi 50 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
  4. */
  5. #include <dt-bindings/phy/phy.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/clock/g12a-clkc.h>
  8. #include <dt-bindings/clock/g12a-aoclkc.h>
  9. #include <dt-bindings/interrupt-controller/irq.h>
  10. #include <dt-bindings/interrupt-controller/arm-gic.h>
  11. #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
  12. #include <dt-bindings/thermal/thermal.h>
  13. / {
  14. interrupt-parent = <&gic>;
  15. #address-cells = <2>;
  16. #size-cells = <2>;
  17. chosen {
  18. #address-cells = <2>;
  19. #size-cells = <2>;
  20. ranges;
  21. simplefb_cvbs: framebuffer-cvbs {
  22. compatible = "amlogic,simple-framebuffer",
  23. "simple-framebuffer";
  24. amlogic,pipeline = "vpu-cvbs";
  25. clocks = <&clkc CLKID_HDMI>,
  26. <&clkc CLKID_HTX_PCLK>,
  27. <&clkc CLKID_VPU_INTR>;
  28. status = "disabled";
  29. };
  30. simplefb_hdmi: framebuffer-hdmi {
  31. compatible = "amlogic,simple-framebuffer",
  32. "simple-framebuffer";
  33. amlogic,pipeline = "vpu-hdmi";
  34. clocks = <&clkc CLKID_HDMI>,
  35. <&clkc CLKID_HTX_PCLK>,
  36. <&clkc CLKID_VPU_INTR>;
  37. status = "disabled";
  38. };
  39. };
  40. efuse: efuse {
  41. compatible = "amlogic,meson-gxbb-efuse";
  42. clocks = <&clkc CLKID_EFUSE>;
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. read-only;
  46. secure-monitor = <&sm>;
  47. };
  48. psci {
  49. compatible = "arm,psci-1.0";
  50. method = "smc";
  51. };
  52. reserved-memory {
  53. #address-cells = <2>;
  54. #size-cells = <2>;
  55. ranges;
  56. /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
  57. secmon_reserved: secmon@5000000 {
  58. reg = <0x0 0x05000000 0x0 0x300000>;
  59. no-map;
  60. };
  61. linux,cma {
  62. compatible = "shared-dma-pool";
  63. reusable;
  64. size = <0x0 0x10000000>;
  65. alignment = <0x0 0x400000>;
  66. linux,cma-default;
  67. };
  68. };
  69. sm: secure-monitor {
  70. compatible = "amlogic,meson-gxbb-sm";
  71. };
  72. soc {
  73. compatible = "simple-bus";
  74. #address-cells = <2>;
  75. #size-cells = <2>;
  76. ranges;
  77. pcie: pcie@fc000000 {
  78. compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
  79. reg = <0x0 0xfc000000 0x0 0x400000
  80. 0x0 0xff648000 0x0 0x2000
  81. 0x0 0xfc400000 0x0 0x200000>;
  82. reg-names = "elbi", "cfg", "config";
  83. interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
  84. #interrupt-cells = <1>;
  85. interrupt-map-mask = <0 0 0 0>;
  86. interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
  87. bus-range = <0x0 0xff>;
  88. #address-cells = <3>;
  89. #size-cells = <2>;
  90. device_type = "pci";
  91. ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
  92. 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
  93. clocks = <&clkc CLKID_PCIE_PHY
  94. &clkc CLKID_PCIE_COMB
  95. &clkc CLKID_PCIE_PLL>;
  96. clock-names = "general",
  97. "pclk",
  98. "port";
  99. resets = <&reset RESET_PCIE_CTRL_A>,
  100. <&reset RESET_PCIE_APB>;
  101. reset-names = "port",
  102. "apb";
  103. num-lanes = <1>;
  104. phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
  105. phy-names = "pcie";
  106. status = "disabled";
  107. };
  108. thermal-zones {
  109. cpu_thermal: cpu-thermal {
  110. polling-delay = <1000>;
  111. polling-delay-passive = <100>;
  112. thermal-sensors = <&cpu_temp>;
  113. trips {
  114. cpu_passive: cpu-passive {
  115. temperature = <85000>; /* millicelsius */
  116. hysteresis = <2000>; /* millicelsius */
  117. type = "passive";
  118. };
  119. cpu_hot: cpu-hot {
  120. temperature = <95000>; /* millicelsius */
  121. hysteresis = <2000>; /* millicelsius */
  122. type = "hot";
  123. };
  124. cpu_critical: cpu-critical {
  125. temperature = <110000>; /* millicelsius */
  126. hysteresis = <2000>; /* millicelsius */
  127. type = "critical";
  128. };
  129. };
  130. };
  131. ddr_thermal: ddr-thermal {
  132. polling-delay = <1000>;
  133. polling-delay-passive = <100>;
  134. thermal-sensors = <&ddr_temp>;
  135. trips {
  136. ddr_passive: ddr-passive {
  137. temperature = <85000>; /* millicelsius */
  138. hysteresis = <2000>; /* millicelsius */
  139. type = "passive";
  140. };
  141. ddr_critical: ddr-critical {
  142. temperature = <110000>; /* millicelsius */
  143. hysteresis = <2000>; /* millicelsius */
  144. type = "critical";
  145. };
  146. };
  147. cooling-maps {
  148. map {
  149. trip = <&ddr_passive>;
  150. cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  151. };
  152. };
  153. };
  154. };
  155. ethmac: ethernet@ff3f0000 {
  156. compatible = "amlogic,meson-axg-dwmac",
  157. "snps,dwmac-3.70a",
  158. "snps,dwmac";
  159. reg = <0x0 0xff3f0000 0x0 0x10000>,
  160. <0x0 0xff634540 0x0 0x8>;
  161. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  162. interrupt-names = "macirq";
  163. clocks = <&clkc CLKID_ETH>,
  164. <&clkc CLKID_FCLK_DIV2>,
  165. <&clkc CLKID_MPLL2>;
  166. clock-names = "stmmaceth", "clkin0", "clkin1";
  167. rx-fifo-depth = <4096>;
  168. tx-fifo-depth = <2048>;
  169. status = "disabled";
  170. mdio0: mdio {
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. compatible = "snps,dwmac-mdio";
  174. };
  175. };
  176. apb: bus@ff600000 {
  177. compatible = "simple-bus";
  178. reg = <0x0 0xff600000 0x0 0x200000>;
  179. #address-cells = <2>;
  180. #size-cells = <2>;
  181. ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
  182. hdmi_tx: hdmi-tx@0 {
  183. compatible = "amlogic,meson-g12a-dw-hdmi";
  184. reg = <0x0 0x0 0x0 0x10000>;
  185. interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
  186. resets = <&reset RESET_HDMITX_CAPB3>,
  187. <&reset RESET_HDMITX_PHY>,
  188. <&reset RESET_HDMITX>;
  189. reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
  190. clocks = <&clkc CLKID_HDMI>,
  191. <&clkc CLKID_HTX_PCLK>,
  192. <&clkc CLKID_VPU_INTR>;
  193. clock-names = "isfr", "iahb", "venci";
  194. #address-cells = <1>;
  195. #size-cells = <0>;
  196. #sound-dai-cells = <0>;
  197. status = "disabled";
  198. /* VPU VENC Input */
  199. hdmi_tx_venc_port: port@0 {
  200. reg = <0>;
  201. hdmi_tx_in: endpoint {
  202. remote-endpoint = <&hdmi_tx_out>;
  203. };
  204. };
  205. /* TMDS Output */
  206. hdmi_tx_tmds_port: port@1 {
  207. reg = <1>;
  208. };
  209. };
  210. apb_efuse: bus@30000 {
  211. compatible = "simple-bus";
  212. reg = <0x0 0x30000 0x0 0x2000>;
  213. #address-cells = <2>;
  214. #size-cells = <2>;
  215. ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
  216. hwrng: rng@218 {
  217. compatible = "amlogic,meson-rng";
  218. reg = <0x0 0x218 0x0 0x4>;
  219. };
  220. };
  221. periphs: bus@34400 {
  222. compatible = "simple-bus";
  223. reg = <0x0 0x34400 0x0 0x400>;
  224. #address-cells = <2>;
  225. #size-cells = <2>;
  226. ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
  227. periphs_pinctrl: pinctrl@40 {
  228. compatible = "amlogic,meson-g12a-periphs-pinctrl";
  229. #address-cells = <2>;
  230. #size-cells = <2>;
  231. ranges;
  232. gpio: bank@40 {
  233. reg = <0x0 0x40 0x0 0x4c>,
  234. <0x0 0xe8 0x0 0x18>,
  235. <0x0 0x120 0x0 0x18>,
  236. <0x0 0x2c0 0x0 0x40>,
  237. <0x0 0x340 0x0 0x1c>;
  238. reg-names = "gpio",
  239. "pull",
  240. "pull-enable",
  241. "mux",
  242. "ds";
  243. gpio-controller;
  244. #gpio-cells = <2>;
  245. gpio-ranges = <&periphs_pinctrl 0 0 86>;
  246. };
  247. cec_ao_a_h_pins: cec_ao_a_h {
  248. mux {
  249. groups = "cec_ao_a_h";
  250. function = "cec_ao_a_h";
  251. bias-disable;
  252. };
  253. };
  254. cec_ao_b_h_pins: cec_ao_b_h {
  255. mux {
  256. groups = "cec_ao_b_h";
  257. function = "cec_ao_b_h";
  258. bias-disable;
  259. };
  260. };
  261. emmc_pins: emmc {
  262. mux-0 {
  263. groups = "emmc_nand_d0",
  264. "emmc_nand_d1",
  265. "emmc_nand_d2",
  266. "emmc_nand_d3",
  267. "emmc_nand_d4",
  268. "emmc_nand_d5",
  269. "emmc_nand_d6",
  270. "emmc_nand_d7",
  271. "emmc_cmd";
  272. function = "emmc";
  273. bias-pull-up;
  274. drive-strength-microamp = <4000>;
  275. };
  276. mux-1 {
  277. groups = "emmc_clk";
  278. function = "emmc";
  279. bias-disable;
  280. drive-strength-microamp = <4000>;
  281. };
  282. };
  283. emmc_ds_pins: emmc-ds {
  284. mux {
  285. groups = "emmc_nand_ds";
  286. function = "emmc";
  287. bias-pull-down;
  288. drive-strength-microamp = <4000>;
  289. };
  290. };
  291. emmc_clk_gate_pins: emmc_clk_gate {
  292. mux {
  293. groups = "BOOT_8";
  294. function = "gpio_periphs";
  295. bias-pull-down;
  296. drive-strength-microamp = <4000>;
  297. };
  298. };
  299. hdmitx_ddc_pins: hdmitx_ddc {
  300. mux {
  301. groups = "hdmitx_sda",
  302. "hdmitx_sck";
  303. function = "hdmitx";
  304. bias-disable;
  305. drive-strength-microamp = <4000>;
  306. };
  307. };
  308. hdmitx_hpd_pins: hdmitx_hpd {
  309. mux {
  310. groups = "hdmitx_hpd_in";
  311. function = "hdmitx";
  312. bias-disable;
  313. };
  314. };
  315. i2c0_sda_c_pins: i2c0-sda-c {
  316. mux {
  317. groups = "i2c0_sda_c";
  318. function = "i2c0";
  319. bias-disable;
  320. drive-strength-microamp = <3000>;
  321. };
  322. };
  323. i2c0_sck_c_pins: i2c0-sck-c {
  324. mux {
  325. groups = "i2c0_sck_c";
  326. function = "i2c0";
  327. bias-disable;
  328. drive-strength-microamp = <3000>;
  329. };
  330. };
  331. i2c0_sda_z0_pins: i2c0-sda-z0 {
  332. mux {
  333. groups = "i2c0_sda_z0";
  334. function = "i2c0";
  335. bias-disable;
  336. drive-strength-microamp = <3000>;
  337. };
  338. };
  339. i2c0_sck_z1_pins: i2c0-sck-z1 {
  340. mux {
  341. groups = "i2c0_sck_z1";
  342. function = "i2c0";
  343. bias-disable;
  344. drive-strength-microamp = <3000>;
  345. };
  346. };
  347. i2c0_sda_z7_pins: i2c0-sda-z7 {
  348. mux {
  349. groups = "i2c0_sda_z7";
  350. function = "i2c0";
  351. bias-disable;
  352. drive-strength-microamp = <3000>;
  353. };
  354. };
  355. i2c0_sda_z8_pins: i2c0-sda-z8 {
  356. mux {
  357. groups = "i2c0_sda_z8";
  358. function = "i2c0";
  359. bias-disable;
  360. drive-strength-microamp = <3000>;
  361. };
  362. };
  363. i2c1_sda_x_pins: i2c1-sda-x {
  364. mux {
  365. groups = "i2c1_sda_x";
  366. function = "i2c1";
  367. bias-disable;
  368. drive-strength-microamp = <3000>;
  369. };
  370. };
  371. i2c1_sck_x_pins: i2c1-sck-x {
  372. mux {
  373. groups = "i2c1_sck_x";
  374. function = "i2c1";
  375. bias-disable;
  376. drive-strength-microamp = <3000>;
  377. };
  378. };
  379. i2c1_sda_h2_pins: i2c1-sda-h2 {
  380. mux {
  381. groups = "i2c1_sda_h2";
  382. function = "i2c1";
  383. bias-disable;
  384. drive-strength-microamp = <3000>;
  385. };
  386. };
  387. i2c1_sck_h3_pins: i2c1-sck-h3 {
  388. mux {
  389. groups = "i2c1_sck_h3";
  390. function = "i2c1";
  391. bias-disable;
  392. drive-strength-microamp = <3000>;
  393. };
  394. };
  395. i2c1_sda_h6_pins: i2c1-sda-h6 {
  396. mux {
  397. groups = "i2c1_sda_h6";
  398. function = "i2c1";
  399. bias-disable;
  400. drive-strength-microamp = <3000>;
  401. };
  402. };
  403. i2c1_sck_h7_pins: i2c1-sck-h7 {
  404. mux {
  405. groups = "i2c1_sck_h7";
  406. function = "i2c1";
  407. bias-disable;
  408. drive-strength-microamp = <3000>;
  409. };
  410. };
  411. i2c2_sda_x_pins: i2c2-sda-x {
  412. mux {
  413. groups = "i2c2_sda_x";
  414. function = "i2c2";
  415. bias-disable;
  416. drive-strength-microamp = <3000>;
  417. };
  418. };
  419. i2c2_sck_x_pins: i2c2-sck-x {
  420. mux {
  421. groups = "i2c2_sck_x";
  422. function = "i2c2";
  423. bias-disable;
  424. drive-strength-microamp = <3000>;
  425. };
  426. };
  427. i2c2_sda_z_pins: i2c2-sda-z {
  428. mux {
  429. groups = "i2c2_sda_z";
  430. function = "i2c2";
  431. bias-disable;
  432. drive-strength-microamp = <3000>;
  433. };
  434. };
  435. i2c2_sck_z_pins: i2c2-sck-z {
  436. mux {
  437. groups = "i2c2_sck_z";
  438. function = "i2c2";
  439. bias-disable;
  440. drive-strength-microamp = <3000>;
  441. };
  442. };
  443. i2c3_sda_h_pins: i2c3-sda-h {
  444. mux {
  445. groups = "i2c3_sda_h";
  446. function = "i2c3";
  447. bias-disable;
  448. drive-strength-microamp = <3000>;
  449. };
  450. };
  451. i2c3_sck_h_pins: i2c3-sck-h {
  452. mux {
  453. groups = "i2c3_sck_h";
  454. function = "i2c3";
  455. bias-disable;
  456. drive-strength-microamp = <3000>;
  457. };
  458. };
  459. i2c3_sda_a_pins: i2c3-sda-a {
  460. mux {
  461. groups = "i2c3_sda_a";
  462. function = "i2c3";
  463. bias-disable;
  464. drive-strength-microamp = <3000>;
  465. };
  466. };
  467. i2c3_sck_a_pins: i2c3-sck-a {
  468. mux {
  469. groups = "i2c3_sck_a";
  470. function = "i2c3";
  471. bias-disable;
  472. drive-strength-microamp = <3000>;
  473. };
  474. };
  475. mclk0_a_pins: mclk0-a {
  476. mux {
  477. groups = "mclk0_a";
  478. function = "mclk0";
  479. bias-disable;
  480. drive-strength-microamp = <3000>;
  481. };
  482. };
  483. mclk1_a_pins: mclk1-a {
  484. mux {
  485. groups = "mclk1_a";
  486. function = "mclk1";
  487. bias-disable;
  488. drive-strength-microamp = <3000>;
  489. };
  490. };
  491. mclk1_x_pins: mclk1-x {
  492. mux {
  493. groups = "mclk1_x";
  494. function = "mclk1";
  495. bias-disable;
  496. drive-strength-microamp = <3000>;
  497. };
  498. };
  499. mclk1_z_pins: mclk1-z {
  500. mux {
  501. groups = "mclk1_z";
  502. function = "mclk1";
  503. bias-disable;
  504. drive-strength-microamp = <3000>;
  505. };
  506. };
  507. pdm_din0_a_pins: pdm-din0-a {
  508. mux {
  509. groups = "pdm_din0_a";
  510. function = "pdm";
  511. bias-disable;
  512. };
  513. };
  514. pdm_din0_c_pins: pdm-din0-c {
  515. mux {
  516. groups = "pdm_din0_c";
  517. function = "pdm";
  518. bias-disable;
  519. };
  520. };
  521. pdm_din0_x_pins: pdm-din0-x {
  522. mux {
  523. groups = "pdm_din0_x";
  524. function = "pdm";
  525. bias-disable;
  526. };
  527. };
  528. pdm_din0_z_pins: pdm-din0-z {
  529. mux {
  530. groups = "pdm_din0_z";
  531. function = "pdm";
  532. bias-disable;
  533. };
  534. };
  535. pdm_din1_a_pins: pdm-din1-a {
  536. mux {
  537. groups = "pdm_din1_a";
  538. function = "pdm";
  539. bias-disable;
  540. };
  541. };
  542. pdm_din1_c_pins: pdm-din1-c {
  543. mux {
  544. groups = "pdm_din1_c";
  545. function = "pdm";
  546. bias-disable;
  547. };
  548. };
  549. pdm_din1_x_pins: pdm-din1-x {
  550. mux {
  551. groups = "pdm_din1_x";
  552. function = "pdm";
  553. bias-disable;
  554. };
  555. };
  556. pdm_din1_z_pins: pdm-din1-z {
  557. mux {
  558. groups = "pdm_din1_z";
  559. function = "pdm";
  560. bias-disable;
  561. };
  562. };
  563. pdm_din2_a_pins: pdm-din2-a {
  564. mux {
  565. groups = "pdm_din2_a";
  566. function = "pdm";
  567. bias-disable;
  568. };
  569. };
  570. pdm_din2_c_pins: pdm-din2-c {
  571. mux {
  572. groups = "pdm_din2_c";
  573. function = "pdm";
  574. bias-disable;
  575. };
  576. };
  577. pdm_din2_x_pins: pdm-din2-x {
  578. mux {
  579. groups = "pdm_din2_x";
  580. function = "pdm";
  581. bias-disable;
  582. };
  583. };
  584. pdm_din2_z_pins: pdm-din2-z {
  585. mux {
  586. groups = "pdm_din2_z";
  587. function = "pdm";
  588. bias-disable;
  589. };
  590. };
  591. pdm_din3_a_pins: pdm-din3-a {
  592. mux {
  593. groups = "pdm_din3_a";
  594. function = "pdm";
  595. bias-disable;
  596. };
  597. };
  598. pdm_din3_c_pins: pdm-din3-c {
  599. mux {
  600. groups = "pdm_din3_c";
  601. function = "pdm";
  602. bias-disable;
  603. };
  604. };
  605. pdm_din3_x_pins: pdm-din3-x {
  606. mux {
  607. groups = "pdm_din3_x";
  608. function = "pdm";
  609. bias-disable;
  610. };
  611. };
  612. pdm_din3_z_pins: pdm-din3-z {
  613. mux {
  614. groups = "pdm_din3_z";
  615. function = "pdm";
  616. bias-disable;
  617. };
  618. };
  619. pdm_dclk_a_pins: pdm-dclk-a {
  620. mux {
  621. groups = "pdm_dclk_a";
  622. function = "pdm";
  623. bias-disable;
  624. drive-strength-microamp = <500>;
  625. };
  626. };
  627. pdm_dclk_c_pins: pdm-dclk-c {
  628. mux {
  629. groups = "pdm_dclk_c";
  630. function = "pdm";
  631. bias-disable;
  632. drive-strength-microamp = <500>;
  633. };
  634. };
  635. pdm_dclk_x_pins: pdm-dclk-x {
  636. mux {
  637. groups = "pdm_dclk_x";
  638. function = "pdm";
  639. bias-disable;
  640. drive-strength-microamp = <500>;
  641. };
  642. };
  643. pdm_dclk_z_pins: pdm-dclk-z {
  644. mux {
  645. groups = "pdm_dclk_z";
  646. function = "pdm";
  647. bias-disable;
  648. drive-strength-microamp = <500>;
  649. };
  650. };
  651. pwm_a_pins: pwm-a {
  652. mux {
  653. groups = "pwm_a";
  654. function = "pwm_a";
  655. bias-disable;
  656. };
  657. };
  658. pwm_b_x7_pins: pwm-b-x7 {
  659. mux {
  660. groups = "pwm_b_x7";
  661. function = "pwm_b";
  662. bias-disable;
  663. };
  664. };
  665. pwm_b_x19_pins: pwm-b-x19 {
  666. mux {
  667. groups = "pwm_b_x19";
  668. function = "pwm_b";
  669. bias-disable;
  670. };
  671. };
  672. pwm_c_c_pins: pwm-c-c {
  673. mux {
  674. groups = "pwm_c_c";
  675. function = "pwm_c";
  676. bias-disable;
  677. };
  678. };
  679. pwm_c_x5_pins: pwm-c-x5 {
  680. mux {
  681. groups = "pwm_c_x5";
  682. function = "pwm_c";
  683. bias-disable;
  684. };
  685. };
  686. pwm_c_x8_pins: pwm-c-x8 {
  687. mux {
  688. groups = "pwm_c_x8";
  689. function = "pwm_c";
  690. bias-disable;
  691. };
  692. };
  693. pwm_d_x3_pins: pwm-d-x3 {
  694. mux {
  695. groups = "pwm_d_x3";
  696. function = "pwm_d";
  697. bias-disable;
  698. };
  699. };
  700. pwm_d_x6_pins: pwm-d-x6 {
  701. mux {
  702. groups = "pwm_d_x6";
  703. function = "pwm_d";
  704. bias-disable;
  705. };
  706. };
  707. pwm_e_pins: pwm-e {
  708. mux {
  709. groups = "pwm_e";
  710. function = "pwm_e";
  711. bias-disable;
  712. };
  713. };
  714. pwm_f_x_pins: pwm-f-x {
  715. mux {
  716. groups = "pwm_f_x";
  717. function = "pwm_f";
  718. bias-disable;
  719. };
  720. };
  721. pwm_f_h_pins: pwm-f-h {
  722. mux {
  723. groups = "pwm_f_h";
  724. function = "pwm_f";
  725. bias-disable;
  726. };
  727. };
  728. sdcard_c_pins: sdcard_c {
  729. mux-0 {
  730. groups = "sdcard_d0_c",
  731. "sdcard_d1_c",
  732. "sdcard_d2_c",
  733. "sdcard_d3_c",
  734. "sdcard_cmd_c";
  735. function = "sdcard";
  736. bias-pull-up;
  737. drive-strength-microamp = <4000>;
  738. };
  739. mux-1 {
  740. groups = "sdcard_clk_c";
  741. function = "sdcard";
  742. bias-disable;
  743. drive-strength-microamp = <4000>;
  744. };
  745. };
  746. sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
  747. mux {
  748. groups = "GPIOC_4";
  749. function = "gpio_periphs";
  750. bias-pull-down;
  751. drive-strength-microamp = <4000>;
  752. };
  753. };
  754. sdcard_z_pins: sdcard_z {
  755. mux-0 {
  756. groups = "sdcard_d0_z",
  757. "sdcard_d1_z",
  758. "sdcard_d2_z",
  759. "sdcard_d3_z",
  760. "sdcard_cmd_z";
  761. function = "sdcard";
  762. bias-pull-up;
  763. drive-strength-microamp = <4000>;
  764. };
  765. mux-1 {
  766. groups = "sdcard_clk_z";
  767. function = "sdcard";
  768. bias-disable;
  769. drive-strength-microamp = <4000>;
  770. };
  771. };
  772. sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
  773. mux {
  774. groups = "GPIOZ_6";
  775. function = "gpio_periphs";
  776. bias-pull-down;
  777. drive-strength-microamp = <4000>;
  778. };
  779. };
  780. sdio_pins: sdio {
  781. mux {
  782. groups = "sdio_d0",
  783. "sdio_d1",
  784. "sdio_d2",
  785. "sdio_d3",
  786. "sdio_clk",
  787. "sdio_cmd";
  788. function = "sdio";
  789. bias-disable;
  790. drive-strength-microamp = <4000>;
  791. };
  792. };
  793. sdio_clk_gate_pins: sdio_clk_gate {
  794. mux {
  795. groups = "GPIOX_4";
  796. function = "gpio_periphs";
  797. bias-pull-down;
  798. drive-strength-microamp = <4000>;
  799. };
  800. };
  801. spdif_in_a10_pins: spdif-in-a10 {
  802. mux {
  803. groups = "spdif_in_a10";
  804. function = "spdif_in";
  805. bias-disable;
  806. };
  807. };
  808. spdif_in_a12_pins: spdif-in-a12 {
  809. mux {
  810. groups = "spdif_in_a12";
  811. function = "spdif_in";
  812. bias-disable;
  813. };
  814. };
  815. spdif_in_h_pins: spdif-in-h {
  816. mux {
  817. groups = "spdif_in_h";
  818. function = "spdif_in";
  819. bias-disable;
  820. };
  821. };
  822. spdif_out_h_pins: spdif-out-h {
  823. mux {
  824. groups = "spdif_out_h";
  825. function = "spdif_out";
  826. drive-strength-microamp = <500>;
  827. bias-disable;
  828. };
  829. };
  830. spdif_out_a11_pins: spdif-out-a11 {
  831. mux {
  832. groups = "spdif_out_a11";
  833. function = "spdif_out";
  834. drive-strength-microamp = <500>;
  835. bias-disable;
  836. };
  837. };
  838. spdif_out_a13_pins: spdif-out-a13 {
  839. mux {
  840. groups = "spdif_out_a13";
  841. function = "spdif_out";
  842. drive-strength-microamp = <500>;
  843. bias-disable;
  844. };
  845. };
  846. tdm_a_din0_pins: tdm-a-din0 {
  847. mux {
  848. groups = "tdm_a_din0";
  849. function = "tdm_a";
  850. bias-disable;
  851. };
  852. };
  853. tdm_a_din1_pins: tdm-a-din1 {
  854. mux {
  855. groups = "tdm_a_din1";
  856. function = "tdm_a";
  857. bias-disable;
  858. };
  859. };
  860. tdm_a_dout0_pins: tdm-a-dout0 {
  861. mux {
  862. groups = "tdm_a_dout0";
  863. function = "tdm_a";
  864. bias-disable;
  865. drive-strength-microamp = <3000>;
  866. };
  867. };
  868. tdm_a_dout1_pins: tdm-a-dout1 {
  869. mux {
  870. groups = "tdm_a_dout1";
  871. function = "tdm_a";
  872. bias-disable;
  873. drive-strength-microamp = <3000>;
  874. };
  875. };
  876. tdm_a_fs_pins: tdm-a-fs {
  877. mux {
  878. groups = "tdm_a_fs";
  879. function = "tdm_a";
  880. bias-disable;
  881. drive-strength-microamp = <3000>;
  882. };
  883. };
  884. tdm_a_sclk_pins: tdm-a-sclk {
  885. mux {
  886. groups = "tdm_a_sclk";
  887. function = "tdm_a";
  888. bias-disable;
  889. drive-strength-microamp = <3000>;
  890. };
  891. };
  892. tdm_a_slv_fs_pins: tdm-a-slv-fs {
  893. mux {
  894. groups = "tdm_a_slv_fs";
  895. function = "tdm_a";
  896. bias-disable;
  897. };
  898. };
  899. tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
  900. mux {
  901. groups = "tdm_a_slv_sclk";
  902. function = "tdm_a";
  903. bias-disable;
  904. };
  905. };
  906. tdm_b_din0_pins: tdm-b-din0 {
  907. mux {
  908. groups = "tdm_b_din0";
  909. function = "tdm_b";
  910. bias-disable;
  911. };
  912. };
  913. tdm_b_din1_pins: tdm-b-din1 {
  914. mux {
  915. groups = "tdm_b_din1";
  916. function = "tdm_b";
  917. bias-disable;
  918. };
  919. };
  920. tdm_b_din2_pins: tdm-b-din2 {
  921. mux {
  922. groups = "tdm_b_din2";
  923. function = "tdm_b";
  924. bias-disable;
  925. };
  926. };
  927. tdm_b_din3_a_pins: tdm-b-din3-a {
  928. mux {
  929. groups = "tdm_b_din3_a";
  930. function = "tdm_b";
  931. bias-disable;
  932. };
  933. };
  934. tdm_b_din3_h_pins: tdm-b-din3-h {
  935. mux {
  936. groups = "tdm_b_din3_h";
  937. function = "tdm_b";
  938. bias-disable;
  939. };
  940. };
  941. tdm_b_dout0_pins: tdm-b-dout0 {
  942. mux {
  943. groups = "tdm_b_dout0";
  944. function = "tdm_b";
  945. bias-disable;
  946. drive-strength-microamp = <3000>;
  947. };
  948. };
  949. tdm_b_dout1_pins: tdm-b-dout1 {
  950. mux {
  951. groups = "tdm_b_dout1";
  952. function = "tdm_b";
  953. bias-disable;
  954. drive-strength-microamp = <3000>;
  955. };
  956. };
  957. tdm_b_dout2_pins: tdm-b-dout2 {
  958. mux {
  959. groups = "tdm_b_dout2";
  960. function = "tdm_b";
  961. bias-disable;
  962. drive-strength-microamp = <3000>;
  963. };
  964. };
  965. tdm_b_dout3_a_pins: tdm-b-dout3-a {
  966. mux {
  967. groups = "tdm_b_dout3_a";
  968. function = "tdm_b";
  969. bias-disable;
  970. drive-strength-microamp = <3000>;
  971. };
  972. };
  973. tdm_b_dout3_h_pins: tdm-b-dout3-h {
  974. mux {
  975. groups = "tdm_b_dout3_h";
  976. function = "tdm_b";
  977. bias-disable;
  978. drive-strength-microamp = <3000>;
  979. };
  980. };
  981. tdm_b_fs_pins: tdm-b-fs {
  982. mux {
  983. groups = "tdm_b_fs";
  984. function = "tdm_b";
  985. bias-disable;
  986. drive-strength-microamp = <3000>;
  987. };
  988. };
  989. tdm_b_sclk_pins: tdm-b-sclk {
  990. mux {
  991. groups = "tdm_b_sclk";
  992. function = "tdm_b";
  993. bias-disable;
  994. drive-strength-microamp = <3000>;
  995. };
  996. };
  997. tdm_b_slv_fs_pins: tdm-b-slv-fs {
  998. mux {
  999. groups = "tdm_b_slv_fs";
  1000. function = "tdm_b";
  1001. bias-disable;
  1002. };
  1003. };
  1004. tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
  1005. mux {
  1006. groups = "tdm_b_slv_sclk";
  1007. function = "tdm_b";
  1008. bias-disable;
  1009. };
  1010. };
  1011. tdm_c_din0_a_pins: tdm-c-din0-a {
  1012. mux {
  1013. groups = "tdm_c_din0_a";
  1014. function = "tdm_c";
  1015. bias-disable;
  1016. };
  1017. };
  1018. tdm_c_din0_z_pins: tdm-c-din0-z {
  1019. mux {
  1020. groups = "tdm_c_din0_z";
  1021. function = "tdm_c";
  1022. bias-disable;
  1023. };
  1024. };
  1025. tdm_c_din1_a_pins: tdm-c-din1-a {
  1026. mux {
  1027. groups = "tdm_c_din1_a";
  1028. function = "tdm_c";
  1029. bias-disable;
  1030. };
  1031. };
  1032. tdm_c_din1_z_pins: tdm-c-din1-z {
  1033. mux {
  1034. groups = "tdm_c_din1_z";
  1035. function = "tdm_c";
  1036. bias-disable;
  1037. };
  1038. };
  1039. tdm_c_din2_a_pins: tdm-c-din2-a {
  1040. mux {
  1041. groups = "tdm_c_din2_a";
  1042. function = "tdm_c";
  1043. bias-disable;
  1044. };
  1045. };
  1046. eth_leds_pins: eth-leds {
  1047. mux {
  1048. groups = "eth_link_led",
  1049. "eth_act_led";
  1050. function = "eth";
  1051. bias-disable;
  1052. };
  1053. };
  1054. eth_pins: eth {
  1055. mux {
  1056. groups = "eth_mdio",
  1057. "eth_mdc",
  1058. "eth_rgmii_rx_clk",
  1059. "eth_rx_dv",
  1060. "eth_rxd0",
  1061. "eth_rxd1",
  1062. "eth_txen",
  1063. "eth_txd0",
  1064. "eth_txd1";
  1065. function = "eth";
  1066. drive-strength-microamp = <4000>;
  1067. bias-disable;
  1068. };
  1069. };
  1070. eth_rgmii_pins: eth-rgmii {
  1071. mux {
  1072. groups = "eth_rxd2_rgmii",
  1073. "eth_rxd3_rgmii",
  1074. "eth_rgmii_tx_clk",
  1075. "eth_txd2_rgmii",
  1076. "eth_txd3_rgmii";
  1077. function = "eth";
  1078. drive-strength-microamp = <4000>;
  1079. bias-disable;
  1080. };
  1081. };
  1082. tdm_c_din2_z_pins: tdm-c-din2-z {
  1083. mux {
  1084. groups = "tdm_c_din2_z";
  1085. function = "tdm_c";
  1086. bias-disable;
  1087. };
  1088. };
  1089. tdm_c_din3_a_pins: tdm-c-din3-a {
  1090. mux {
  1091. groups = "tdm_c_din3_a";
  1092. function = "tdm_c";
  1093. bias-disable;
  1094. };
  1095. };
  1096. tdm_c_din3_z_pins: tdm-c-din3-z {
  1097. mux {
  1098. groups = "tdm_c_din3_z";
  1099. function = "tdm_c";
  1100. bias-disable;
  1101. };
  1102. };
  1103. tdm_c_dout0_a_pins: tdm-c-dout0-a {
  1104. mux {
  1105. groups = "tdm_c_dout0_a";
  1106. function = "tdm_c";
  1107. bias-disable;
  1108. drive-strength-microamp = <3000>;
  1109. };
  1110. };
  1111. tdm_c_dout0_z_pins: tdm-c-dout0-z {
  1112. mux {
  1113. groups = "tdm_c_dout0_z";
  1114. function = "tdm_c";
  1115. bias-disable;
  1116. drive-strength-microamp = <3000>;
  1117. };
  1118. };
  1119. tdm_c_dout1_a_pins: tdm-c-dout1-a {
  1120. mux {
  1121. groups = "tdm_c_dout1_a";
  1122. function = "tdm_c";
  1123. bias-disable;
  1124. drive-strength-microamp = <3000>;
  1125. };
  1126. };
  1127. tdm_c_dout1_z_pins: tdm-c-dout1-z {
  1128. mux {
  1129. groups = "tdm_c_dout1_z";
  1130. function = "tdm_c";
  1131. bias-disable;
  1132. drive-strength-microamp = <3000>;
  1133. };
  1134. };
  1135. tdm_c_dout2_a_pins: tdm-c-dout2-a {
  1136. mux {
  1137. groups = "tdm_c_dout2_a";
  1138. function = "tdm_c";
  1139. bias-disable;
  1140. drive-strength-microamp = <3000>;
  1141. };
  1142. };
  1143. tdm_c_dout2_z_pins: tdm-c-dout2-z {
  1144. mux {
  1145. groups = "tdm_c_dout2_z";
  1146. function = "tdm_c";
  1147. bias-disable;
  1148. drive-strength-microamp = <3000>;
  1149. };
  1150. };
  1151. tdm_c_dout3_a_pins: tdm-c-dout3-a {
  1152. mux {
  1153. groups = "tdm_c_dout3_a";
  1154. function = "tdm_c";
  1155. bias-disable;
  1156. drive-strength-microamp = <3000>;
  1157. };
  1158. };
  1159. tdm_c_dout3_z_pins: tdm-c-dout3-z {
  1160. mux {
  1161. groups = "tdm_c_dout3_z";
  1162. function = "tdm_c";
  1163. bias-disable;
  1164. drive-strength-microamp = <3000>;
  1165. };
  1166. };
  1167. tdm_c_fs_a_pins: tdm-c-fs-a {
  1168. mux {
  1169. groups = "tdm_c_fs_a";
  1170. function = "tdm_c";
  1171. bias-disable;
  1172. drive-strength-microamp = <3000>;
  1173. };
  1174. };
  1175. tdm_c_fs_z_pins: tdm-c-fs-z {
  1176. mux {
  1177. groups = "tdm_c_fs_z";
  1178. function = "tdm_c";
  1179. bias-disable;
  1180. drive-strength-microamp = <3000>;
  1181. };
  1182. };
  1183. tdm_c_sclk_a_pins: tdm-c-sclk-a {
  1184. mux {
  1185. groups = "tdm_c_sclk_a";
  1186. function = "tdm_c";
  1187. bias-disable;
  1188. drive-strength-microamp = <3000>;
  1189. };
  1190. };
  1191. tdm_c_sclk_z_pins: tdm-c-sclk-z {
  1192. mux {
  1193. groups = "tdm_c_sclk_z";
  1194. function = "tdm_c";
  1195. bias-disable;
  1196. drive-strength-microamp = <3000>;
  1197. };
  1198. };
  1199. tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
  1200. mux {
  1201. groups = "tdm_c_slv_fs_a";
  1202. function = "tdm_c";
  1203. bias-disable;
  1204. };
  1205. };
  1206. tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
  1207. mux {
  1208. groups = "tdm_c_slv_fs_z";
  1209. function = "tdm_c";
  1210. bias-disable;
  1211. };
  1212. };
  1213. tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
  1214. mux {
  1215. groups = "tdm_c_slv_sclk_a";
  1216. function = "tdm_c";
  1217. bias-disable;
  1218. };
  1219. };
  1220. tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
  1221. mux {
  1222. groups = "tdm_c_slv_sclk_z";
  1223. function = "tdm_c";
  1224. bias-disable;
  1225. };
  1226. };
  1227. uart_a_pins: uart-a {
  1228. mux {
  1229. groups = "uart_a_tx",
  1230. "uart_a_rx";
  1231. function = "uart_a";
  1232. bias-disable;
  1233. };
  1234. };
  1235. uart_a_cts_rts_pins: uart-a-cts-rts {
  1236. mux {
  1237. groups = "uart_a_cts",
  1238. "uart_a_rts";
  1239. function = "uart_a";
  1240. bias-disable;
  1241. };
  1242. };
  1243. uart_b_pins: uart-b {
  1244. mux {
  1245. groups = "uart_b_tx",
  1246. "uart_b_rx";
  1247. function = "uart_b";
  1248. bias-disable;
  1249. };
  1250. };
  1251. uart_c_pins: uart-c {
  1252. mux {
  1253. groups = "uart_c_tx",
  1254. "uart_c_rx";
  1255. function = "uart_c";
  1256. bias-disable;
  1257. };
  1258. };
  1259. uart_c_cts_rts_pins: uart-c-cts-rts {
  1260. mux {
  1261. groups = "uart_c_cts",
  1262. "uart_c_rts";
  1263. function = "uart_c";
  1264. bias-disable;
  1265. };
  1266. };
  1267. };
  1268. };
  1269. cpu_temp: temperature-sensor@34800 {
  1270. compatible = "amlogic,g12a-cpu-thermal",
  1271. "amlogic,g12a-thermal";
  1272. reg = <0x0 0x34800 0x0 0x50>;
  1273. interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
  1274. clocks = <&clkc CLKID_TS>;
  1275. #thermal-sensor-cells = <0>;
  1276. amlogic,ao-secure = <&sec_AO>;
  1277. };
  1278. ddr_temp: temperature-sensor@34c00 {
  1279. compatible = "amlogic,g12a-ddr-thermal",
  1280. "amlogic,g12a-thermal";
  1281. reg = <0x0 0x34c00 0x0 0x50>;
  1282. interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
  1283. clocks = <&clkc CLKID_TS>;
  1284. #thermal-sensor-cells = <0>;
  1285. amlogic,ao-secure = <&sec_AO>;
  1286. };
  1287. usb2_phy0: phy@36000 {
  1288. compatible = "amlogic,g12a-usb2-phy";
  1289. reg = <0x0 0x36000 0x0 0x2000>;
  1290. clocks = <&xtal>;
  1291. clock-names = "xtal";
  1292. resets = <&reset RESET_USB_PHY20>;
  1293. reset-names = "phy";
  1294. #phy-cells = <0>;
  1295. };
  1296. dmc: bus@38000 {
  1297. compatible = "simple-bus";
  1298. reg = <0x0 0x38000 0x0 0x400>;
  1299. #address-cells = <2>;
  1300. #size-cells = <2>;
  1301. ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
  1302. canvas: video-lut@48 {
  1303. compatible = "amlogic,canvas";
  1304. reg = <0x0 0x48 0x0 0x14>;
  1305. };
  1306. };
  1307. usb2_phy1: phy@3a000 {
  1308. compatible = "amlogic,g12a-usb2-phy";
  1309. reg = <0x0 0x3a000 0x0 0x2000>;
  1310. clocks = <&xtal>;
  1311. clock-names = "xtal";
  1312. resets = <&reset RESET_USB_PHY21>;
  1313. reset-names = "phy";
  1314. #phy-cells = <0>;
  1315. };
  1316. hiu: bus@3c000 {
  1317. compatible = "simple-bus";
  1318. reg = <0x0 0x3c000 0x0 0x1400>;
  1319. #address-cells = <2>;
  1320. #size-cells = <2>;
  1321. ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
  1322. hhi: system-controller@0 {
  1323. compatible = "amlogic,meson-gx-hhi-sysctrl",
  1324. "simple-mfd", "syscon";
  1325. reg = <0 0 0 0x400>;
  1326. clkc: clock-controller {
  1327. compatible = "amlogic,g12a-clkc";
  1328. #clock-cells = <1>;
  1329. clocks = <&xtal>;
  1330. clock-names = "xtal";
  1331. };
  1332. pwrc: power-controller {
  1333. compatible = "amlogic,meson-g12a-pwrc";
  1334. #power-domain-cells = <1>;
  1335. amlogic,ao-sysctrl = <&rti>;
  1336. resets = <&reset RESET_VIU>,
  1337. <&reset RESET_VENC>,
  1338. <&reset RESET_VCBUS>,
  1339. <&reset RESET_BT656>,
  1340. <&reset RESET_RDMA>,
  1341. <&reset RESET_VENCI>,
  1342. <&reset RESET_VENCP>,
  1343. <&reset RESET_VDAC>,
  1344. <&reset RESET_VDI6>,
  1345. <&reset RESET_VENCL>,
  1346. <&reset RESET_VID_LOCK>;
  1347. reset-names = "viu", "venc", "vcbus", "bt656",
  1348. "rdma", "venci", "vencp", "vdac",
  1349. "vdi6", "vencl", "vid_lock";
  1350. clocks = <&clkc CLKID_VPU>,
  1351. <&clkc CLKID_VAPB>;
  1352. clock-names = "vpu", "vapb";
  1353. /*
  1354. * VPU clocking is provided by two identical clock paths
  1355. * VPU_0 and VPU_1 muxed to a single clock by a glitch
  1356. * free mux to safely change frequency while running.
  1357. * Same for VAPB but with a final gate after the glitch free mux.
  1358. */
  1359. assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
  1360. <&clkc CLKID_VPU_0>,
  1361. <&clkc CLKID_VPU>, /* Glitch free mux */
  1362. <&clkc CLKID_VAPB_0_SEL>,
  1363. <&clkc CLKID_VAPB_0>,
  1364. <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
  1365. assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  1366. <0>, /* Do Nothing */
  1367. <&clkc CLKID_VPU_0>,
  1368. <&clkc CLKID_FCLK_DIV4>,
  1369. <0>, /* Do Nothing */
  1370. <&clkc CLKID_VAPB_0>;
  1371. assigned-clock-rates = <0>, /* Do Nothing */
  1372. <666666666>,
  1373. <0>, /* Do Nothing */
  1374. <0>, /* Do Nothing */
  1375. <250000000>,
  1376. <0>; /* Do Nothing */
  1377. };
  1378. };
  1379. };
  1380. usb3_pcie_phy: phy@46000 {
  1381. compatible = "amlogic,g12a-usb3-pcie-phy";
  1382. reg = <0x0 0x46000 0x0 0x2000>;
  1383. clocks = <&clkc CLKID_PCIE_PLL>;
  1384. clock-names = "ref_clk";
  1385. resets = <&reset RESET_PCIE_PHY>;
  1386. reset-names = "phy";
  1387. assigned-clocks = <&clkc CLKID_PCIE_PLL>;
  1388. assigned-clock-rates = <100000000>;
  1389. #phy-cells = <1>;
  1390. };
  1391. eth_phy: mdio-multiplexer@4c000 {
  1392. compatible = "amlogic,g12a-mdio-mux";
  1393. reg = <0x0 0x4c000 0x0 0xa4>;
  1394. clocks = <&clkc CLKID_ETH_PHY>,
  1395. <&xtal>,
  1396. <&clkc CLKID_MPLL_50M>;
  1397. clock-names = "pclk", "clkin0", "clkin1";
  1398. mdio-parent-bus = <&mdio0>;
  1399. #address-cells = <1>;
  1400. #size-cells = <0>;
  1401. ext_mdio: mdio@0 {
  1402. reg = <0>;
  1403. #address-cells = <1>;
  1404. #size-cells = <0>;
  1405. };
  1406. int_mdio: mdio@1 {
  1407. reg = <1>;
  1408. #address-cells = <1>;
  1409. #size-cells = <0>;
  1410. internal_ephy: ethernet_phy@8 {
  1411. compatible = "ethernet-phy-id0180.3301",
  1412. "ethernet-phy-ieee802.3-c22";
  1413. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  1414. reg = <8>;
  1415. max-speed = <100>;
  1416. };
  1417. };
  1418. };
  1419. };
  1420. aobus: bus@ff800000 {
  1421. compatible = "simple-bus";
  1422. reg = <0x0 0xff800000 0x0 0x100000>;
  1423. #address-cells = <2>;
  1424. #size-cells = <2>;
  1425. ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
  1426. rti: sys-ctrl@0 {
  1427. compatible = "amlogic,meson-gx-ao-sysctrl",
  1428. "simple-mfd", "syscon";
  1429. reg = <0x0 0x0 0x0 0x100>;
  1430. #address-cells = <2>;
  1431. #size-cells = <2>;
  1432. ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
  1433. clkc_AO: clock-controller {
  1434. compatible = "amlogic,meson-g12a-aoclkc";
  1435. #clock-cells = <1>;
  1436. #reset-cells = <1>;
  1437. clocks = <&xtal>, <&clkc CLKID_CLK81>;
  1438. clock-names = "xtal", "mpeg-clk";
  1439. };
  1440. ao_pinctrl: pinctrl@14 {
  1441. compatible = "amlogic,meson-g12a-aobus-pinctrl";
  1442. #address-cells = <2>;
  1443. #size-cells = <2>;
  1444. ranges;
  1445. gpio_ao: bank@14 {
  1446. reg = <0x0 0x14 0x0 0x8>,
  1447. <0x0 0x1c 0x0 0x8>,
  1448. <0x0 0x24 0x0 0x14>;
  1449. reg-names = "mux",
  1450. "ds",
  1451. "gpio";
  1452. gpio-controller;
  1453. #gpio-cells = <2>;
  1454. gpio-ranges = <&ao_pinctrl 0 0 15>;
  1455. };
  1456. i2c_ao_sck_pins: i2c_ao_sck_pins {
  1457. mux {
  1458. groups = "i2c_ao_sck";
  1459. function = "i2c_ao";
  1460. bias-disable;
  1461. drive-strength-microamp = <3000>;
  1462. };
  1463. };
  1464. i2c_ao_sda_pins: i2c_ao_sda {
  1465. mux {
  1466. groups = "i2c_ao_sda";
  1467. function = "i2c_ao";
  1468. bias-disable;
  1469. drive-strength-microamp = <3000>;
  1470. };
  1471. };
  1472. i2c_ao_sck_e_pins: i2c_ao_sck_e {
  1473. mux {
  1474. groups = "i2c_ao_sck_e";
  1475. function = "i2c_ao";
  1476. bias-disable;
  1477. drive-strength-microamp = <3000>;
  1478. };
  1479. };
  1480. i2c_ao_sda_e_pins: i2c_ao_sda_e {
  1481. mux {
  1482. groups = "i2c_ao_sda_e";
  1483. function = "i2c_ao";
  1484. bias-disable;
  1485. drive-strength-microamp = <3000>;
  1486. };
  1487. };
  1488. mclk0_ao_pins: mclk0-ao {
  1489. mux {
  1490. groups = "mclk0_ao";
  1491. function = "mclk0_ao";
  1492. bias-disable;
  1493. drive-strength-microamp = <3000>;
  1494. };
  1495. };
  1496. tdm_ao_b_din0_pins: tdm-ao-b-din0 {
  1497. mux {
  1498. groups = "tdm_ao_b_din0";
  1499. function = "tdm_ao_b";
  1500. bias-disable;
  1501. };
  1502. };
  1503. spdif_ao_out_pins: spdif-ao-out {
  1504. mux {
  1505. groups = "spdif_ao_out";
  1506. function = "spdif_ao_out";
  1507. drive-strength-microamp = <500>;
  1508. bias-disable;
  1509. };
  1510. };
  1511. tdm_ao_b_din1_pins: tdm-ao-b-din1 {
  1512. mux {
  1513. groups = "tdm_ao_b_din1";
  1514. function = "tdm_ao_b";
  1515. bias-disable;
  1516. };
  1517. };
  1518. tdm_ao_b_din2_pins: tdm-ao-b-din2 {
  1519. mux {
  1520. groups = "tdm_ao_b_din2";
  1521. function = "tdm_ao_b";
  1522. bias-disable;
  1523. };
  1524. };
  1525. tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
  1526. mux {
  1527. groups = "tdm_ao_b_dout0";
  1528. function = "tdm_ao_b";
  1529. bias-disable;
  1530. drive-strength-microamp = <3000>;
  1531. };
  1532. };
  1533. tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
  1534. mux {
  1535. groups = "tdm_ao_b_dout1";
  1536. function = "tdm_ao_b";
  1537. bias-disable;
  1538. drive-strength-microamp = <3000>;
  1539. };
  1540. };
  1541. tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
  1542. mux {
  1543. groups = "tdm_ao_b_dout2";
  1544. function = "tdm_ao_b";
  1545. bias-disable;
  1546. drive-strength-microamp = <3000>;
  1547. };
  1548. };
  1549. tdm_ao_b_fs_pins: tdm-ao-b-fs {
  1550. mux {
  1551. groups = "tdm_ao_b_fs";
  1552. function = "tdm_ao_b";
  1553. bias-disable;
  1554. drive-strength-microamp = <3000>;
  1555. };
  1556. };
  1557. tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
  1558. mux {
  1559. groups = "tdm_ao_b_sclk";
  1560. function = "tdm_ao_b";
  1561. bias-disable;
  1562. drive-strength-microamp = <3000>;
  1563. };
  1564. };
  1565. tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
  1566. mux {
  1567. groups = "tdm_ao_b_slv_fs";
  1568. function = "tdm_ao_b";
  1569. bias-disable;
  1570. };
  1571. };
  1572. tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
  1573. mux {
  1574. groups = "tdm_ao_b_slv_sclk";
  1575. function = "tdm_ao_b";
  1576. bias-disable;
  1577. };
  1578. };
  1579. uart_ao_a_pins: uart-a-ao {
  1580. mux {
  1581. groups = "uart_ao_a_tx",
  1582. "uart_ao_a_rx";
  1583. function = "uart_ao_a";
  1584. bias-disable;
  1585. };
  1586. };
  1587. uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
  1588. mux {
  1589. groups = "uart_ao_a_cts",
  1590. "uart_ao_a_rts";
  1591. function = "uart_ao_a";
  1592. bias-disable;
  1593. };
  1594. };
  1595. pwm_a_e_pins: pwm-a-e {
  1596. mux {
  1597. groups = "pwm_a_e";
  1598. function = "pwm_a_e";
  1599. bias-disable;
  1600. };
  1601. };
  1602. pwm_ao_a_pins: pwm-ao-a {
  1603. mux {
  1604. groups = "pwm_ao_a";
  1605. function = "pwm_ao_a";
  1606. bias-disable;
  1607. };
  1608. };
  1609. pwm_ao_b_pins: pwm-ao-b {
  1610. mux {
  1611. groups = "pwm_ao_b";
  1612. function = "pwm_ao_b";
  1613. bias-disable;
  1614. };
  1615. };
  1616. pwm_ao_c_4_pins: pwm-ao-c-4 {
  1617. mux {
  1618. groups = "pwm_ao_c_4";
  1619. function = "pwm_ao_c";
  1620. bias-disable;
  1621. };
  1622. };
  1623. pwm_ao_c_6_pins: pwm-ao-c-6 {
  1624. mux {
  1625. groups = "pwm_ao_c_6";
  1626. function = "pwm_ao_c";
  1627. bias-disable;
  1628. };
  1629. };
  1630. pwm_ao_d_5_pins: pwm-ao-d-5 {
  1631. mux {
  1632. groups = "pwm_ao_d_5";
  1633. function = "pwm_ao_d";
  1634. bias-disable;
  1635. };
  1636. };
  1637. pwm_ao_d_10_pins: pwm-ao-d-10 {
  1638. mux {
  1639. groups = "pwm_ao_d_10";
  1640. function = "pwm_ao_d";
  1641. bias-disable;
  1642. };
  1643. };
  1644. pwm_ao_d_e_pins: pwm-ao-d-e {
  1645. mux {
  1646. groups = "pwm_ao_d_e";
  1647. function = "pwm_ao_d";
  1648. };
  1649. };
  1650. remote_input_ao_pins: remote-input-ao {
  1651. mux {
  1652. groups = "remote_ao_input";
  1653. function = "remote_ao_input";
  1654. bias-disable;
  1655. };
  1656. };
  1657. };
  1658. };
  1659. vrtc: rtc@0a8 {
  1660. compatible = "amlogic,meson-vrtc";
  1661. reg = <0x0 0x000a8 0x0 0x4>;
  1662. };
  1663. cec_AO: cec@100 {
  1664. compatible = "amlogic,meson-gx-ao-cec";
  1665. reg = <0x0 0x00100 0x0 0x14>;
  1666. interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
  1667. clocks = <&clkc_AO CLKID_AO_CEC>;
  1668. clock-names = "core";
  1669. status = "disabled";
  1670. };
  1671. sec_AO: ao-secure@140 {
  1672. compatible = "amlogic,meson-gx-ao-secure", "syscon";
  1673. reg = <0x0 0x140 0x0 0x140>;
  1674. amlogic,has-chip-id;
  1675. };
  1676. cecb_AO: cec@280 {
  1677. compatible = "amlogic,meson-g12a-ao-cec";
  1678. reg = <0x0 0x00280 0x0 0x1c>;
  1679. interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
  1680. clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
  1681. clock-names = "oscin";
  1682. status = "disabled";
  1683. };
  1684. pwm_AO_cd: pwm@2000 {
  1685. compatible = "amlogic,meson-g12a-ao-pwm-cd";
  1686. reg = <0x0 0x2000 0x0 0x20>;
  1687. #pwm-cells = <3>;
  1688. status = "disabled";
  1689. };
  1690. uart_AO: serial@3000 {
  1691. compatible = "amlogic,meson-gx-uart",
  1692. "amlogic,meson-ao-uart";
  1693. reg = <0x0 0x3000 0x0 0x18>;
  1694. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  1695. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
  1696. clock-names = "xtal", "pclk", "baud";
  1697. status = "disabled";
  1698. };
  1699. uart_AO_B: serial@4000 {
  1700. compatible = "amlogic,meson-gx-uart",
  1701. "amlogic,meson-ao-uart";
  1702. reg = <0x0 0x4000 0x0 0x18>;
  1703. interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
  1704. clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  1705. clock-names = "xtal", "pclk", "baud";
  1706. status = "disabled";
  1707. };
  1708. i2c_AO: i2c@5000 {
  1709. compatible = "amlogic,meson-axg-i2c";
  1710. status = "disabled";
  1711. reg = <0x0 0x05000 0x0 0x20>;
  1712. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  1713. #address-cells = <1>;
  1714. #size-cells = <0>;
  1715. clocks = <&clkc CLKID_I2C>;
  1716. };
  1717. pwm_AO_ab: pwm@7000 {
  1718. compatible = "amlogic,meson-g12a-ao-pwm-ab";
  1719. reg = <0x0 0x7000 0x0 0x20>;
  1720. #pwm-cells = <3>;
  1721. status = "disabled";
  1722. };
  1723. ir: ir@8000 {
  1724. compatible = "amlogic,meson-gxbb-ir";
  1725. reg = <0x0 0x8000 0x0 0x20>;
  1726. interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
  1727. status = "disabled";
  1728. };
  1729. saradc: adc@9000 {
  1730. compatible = "amlogic,meson-g12a-saradc",
  1731. "amlogic,meson-saradc";
  1732. reg = <0x0 0x9000 0x0 0x48>;
  1733. #io-channel-cells = <1>;
  1734. interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
  1735. clocks = <&xtal>,
  1736. <&clkc_AO CLKID_AO_SAR_ADC>,
  1737. <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
  1738. <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
  1739. clock-names = "clkin", "core", "adc_clk", "adc_sel";
  1740. status = "disabled";
  1741. };
  1742. };
  1743. vdec: video-decoder@ff620000 {
  1744. compatible = "amlogic,g12a-vdec";
  1745. reg = <0x0 0xff620000 0x0 0x10000>,
  1746. <0x0 0xffd0e180 0x0 0xe4>;
  1747. reg-names = "dos", "esparser";
  1748. interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
  1749. <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
  1750. interrupt-names = "vdec", "esparser";
  1751. amlogic,ao-sysctrl = <&rti>;
  1752. amlogic,canvas = <&canvas>;
  1753. clocks = <&clkc CLKID_PARSER>,
  1754. <&clkc CLKID_DOS>,
  1755. <&clkc CLKID_VDEC_1>,
  1756. <&clkc CLKID_VDEC_HEVC>,
  1757. <&clkc CLKID_VDEC_HEVCF>;
  1758. clock-names = "dos_parser", "dos", "vdec_1",
  1759. "vdec_hevc", "vdec_hevcf";
  1760. resets = <&reset RESET_PARSER>;
  1761. reset-names = "esparser";
  1762. };
  1763. vpu: vpu@ff900000 {
  1764. compatible = "amlogic,meson-g12a-vpu";
  1765. reg = <0x0 0xff900000 0x0 0x100000>,
  1766. <0x0 0xff63c000 0x0 0x1000>;
  1767. reg-names = "vpu", "hhi";
  1768. interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
  1769. #address-cells = <1>;
  1770. #size-cells = <0>;
  1771. amlogic,canvas = <&canvas>;
  1772. /* CVBS VDAC output port */
  1773. cvbs_vdac_port: port@0 {
  1774. reg = <0>;
  1775. };
  1776. /* HDMI-TX output port */
  1777. hdmi_tx_port: port@1 {
  1778. reg = <1>;
  1779. hdmi_tx_out: endpoint {
  1780. remote-endpoint = <&hdmi_tx_in>;
  1781. };
  1782. };
  1783. };
  1784. gic: interrupt-controller@ffc01000 {
  1785. compatible = "arm,gic-400";
  1786. reg = <0x0 0xffc01000 0 0x1000>,
  1787. <0x0 0xffc02000 0 0x2000>,
  1788. <0x0 0xffc04000 0 0x2000>,
  1789. <0x0 0xffc06000 0 0x2000>;
  1790. interrupt-controller;
  1791. interrupts = <GIC_PPI 9
  1792. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  1793. #interrupt-cells = <3>;
  1794. #address-cells = <0>;
  1795. };
  1796. cbus: bus@ffd00000 {
  1797. compatible = "simple-bus";
  1798. reg = <0x0 0xffd00000 0x0 0x100000>;
  1799. #address-cells = <2>;
  1800. #size-cells = <2>;
  1801. ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
  1802. reset: reset-controller@1004 {
  1803. compatible = "amlogic,meson-axg-reset";
  1804. reg = <0x0 0x1004 0x0 0x9c>;
  1805. #reset-cells = <1>;
  1806. };
  1807. gpio_intc: interrupt-controller@f080 {
  1808. compatible = "amlogic,meson-g12a-gpio-intc",
  1809. "amlogic,meson-gpio-intc";
  1810. reg = <0x0 0xf080 0x0 0x10>;
  1811. interrupt-controller;
  1812. #interrupt-cells = <2>;
  1813. amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
  1814. };
  1815. pwm_ef: pwm@19000 {
  1816. compatible = "amlogic,meson-g12a-ee-pwm";
  1817. reg = <0x0 0x19000 0x0 0x20>;
  1818. #pwm-cells = <3>;
  1819. status = "disabled";
  1820. };
  1821. pwm_cd: pwm@1a000 {
  1822. compatible = "amlogic,meson-g12a-ee-pwm";
  1823. reg = <0x0 0x1a000 0x0 0x20>;
  1824. #pwm-cells = <3>;
  1825. status = "disabled";
  1826. };
  1827. pwm_ab: pwm@1b000 {
  1828. compatible = "amlogic,meson-g12a-ee-pwm";
  1829. reg = <0x0 0x1b000 0x0 0x20>;
  1830. #pwm-cells = <3>;
  1831. status = "disabled";
  1832. };
  1833. i2c3: i2c@1c000 {
  1834. compatible = "amlogic,meson-axg-i2c";
  1835. status = "disabled";
  1836. reg = <0x0 0x1c000 0x0 0x20>;
  1837. interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
  1838. #address-cells = <1>;
  1839. #size-cells = <0>;
  1840. clocks = <&clkc CLKID_I2C>;
  1841. };
  1842. i2c2: i2c@1d000 {
  1843. compatible = "amlogic,meson-axg-i2c";
  1844. status = "disabled";
  1845. reg = <0x0 0x1d000 0x0 0x20>;
  1846. interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
  1847. #address-cells = <1>;
  1848. #size-cells = <0>;
  1849. clocks = <&clkc CLKID_I2C>;
  1850. };
  1851. i2c1: i2c@1e000 {
  1852. compatible = "amlogic,meson-axg-i2c";
  1853. status = "disabled";
  1854. reg = <0x0 0x1e000 0x0 0x20>;
  1855. interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
  1856. #address-cells = <1>;
  1857. #size-cells = <0>;
  1858. clocks = <&clkc CLKID_I2C>;
  1859. };
  1860. i2c0: i2c@1f000 {
  1861. compatible = "amlogic,meson-axg-i2c";
  1862. status = "disabled";
  1863. reg = <0x0 0x1f000 0x0 0x20>;
  1864. interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
  1865. #address-cells = <1>;
  1866. #size-cells = <0>;
  1867. clocks = <&clkc CLKID_I2C>;
  1868. };
  1869. clk_msr: clock-measure@18000 {
  1870. compatible = "amlogic,meson-g12a-clk-measure";
  1871. reg = <0x0 0x18000 0x0 0x10>;
  1872. };
  1873. uart_C: serial@22000 {
  1874. compatible = "amlogic,meson-gx-uart";
  1875. reg = <0x0 0x22000 0x0 0x18>;
  1876. interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
  1877. clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
  1878. clock-names = "xtal", "pclk", "baud";
  1879. status = "disabled";
  1880. };
  1881. uart_B: serial@23000 {
  1882. compatible = "amlogic,meson-gx-uart";
  1883. reg = <0x0 0x23000 0x0 0x18>;
  1884. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  1885. clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  1886. clock-names = "xtal", "pclk", "baud";
  1887. status = "disabled";
  1888. };
  1889. uart_A: serial@24000 {
  1890. compatible = "amlogic,meson-gx-uart";
  1891. reg = <0x0 0x24000 0x0 0x18>;
  1892. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  1893. clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  1894. clock-names = "xtal", "pclk", "baud";
  1895. status = "disabled";
  1896. };
  1897. };
  1898. sd_emmc_a: sd@ffe03000 {
  1899. compatible = "amlogic,meson-axg-mmc";
  1900. reg = <0x0 0xffe03000 0x0 0x800>;
  1901. interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
  1902. status = "disabled";
  1903. clocks = <&clkc CLKID_SD_EMMC_A>,
  1904. <&clkc CLKID_SD_EMMC_A_CLK0>,
  1905. <&clkc CLKID_FCLK_DIV2>;
  1906. clock-names = "core", "clkin0", "clkin1";
  1907. resets = <&reset RESET_SD_EMMC_A>;
  1908. };
  1909. sd_emmc_b: sd@ffe05000 {
  1910. compatible = "amlogic,meson-axg-mmc";
  1911. reg = <0x0 0xffe05000 0x0 0x800>;
  1912. interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
  1913. status = "disabled";
  1914. clocks = <&clkc CLKID_SD_EMMC_B>,
  1915. <&clkc CLKID_SD_EMMC_B_CLK0>,
  1916. <&clkc CLKID_FCLK_DIV2>;
  1917. clock-names = "core", "clkin0", "clkin1";
  1918. resets = <&reset RESET_SD_EMMC_B>;
  1919. };
  1920. sd_emmc_c: mmc@ffe07000 {
  1921. compatible = "amlogic,meson-axg-mmc";
  1922. reg = <0x0 0xffe07000 0x0 0x800>;
  1923. interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
  1924. status = "disabled";
  1925. clocks = <&clkc CLKID_SD_EMMC_C>,
  1926. <&clkc CLKID_SD_EMMC_C_CLK0>,
  1927. <&clkc CLKID_FCLK_DIV2>;
  1928. clock-names = "core", "clkin0", "clkin1";
  1929. resets = <&reset RESET_SD_EMMC_C>;
  1930. };
  1931. usb: usb@ffe09000 {
  1932. status = "disabled";
  1933. compatible = "amlogic,meson-g12a-usb-ctrl";
  1934. reg = <0x0 0xffe09000 0x0 0xa0>;
  1935. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  1936. #address-cells = <2>;
  1937. #size-cells = <2>;
  1938. ranges;
  1939. clocks = <&clkc CLKID_USB>;
  1940. resets = <&reset RESET_USB>;
  1941. dr_mode = "otg";
  1942. phys = <&usb2_phy0>, <&usb2_phy1>,
  1943. <&usb3_pcie_phy PHY_TYPE_USB3>;
  1944. phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
  1945. dwc2: usb@ff400000 {
  1946. compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
  1947. reg = <0x0 0xff400000 0x0 0x40000>;
  1948. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  1949. clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
  1950. clock-names = "ddr";
  1951. phys = <&usb2_phy1>;
  1952. phy-names = "usb2-phy";
  1953. dr_mode = "peripheral";
  1954. g-rx-fifo-size = <192>;
  1955. g-np-tx-fifo-size = <128>;
  1956. g-tx-fifo-size = <128 128 16 16 16>;
  1957. };
  1958. dwc3: usb@ff500000 {
  1959. compatible = "snps,dwc3";
  1960. reg = <0x0 0xff500000 0x0 0x100000>;
  1961. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  1962. dr_mode = "host";
  1963. snps,dis_u2_susphy_quirk;
  1964. snps,quirk-frame-length-adjustment;
  1965. };
  1966. };
  1967. mali: gpu@ffe40000 {
  1968. compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
  1969. reg = <0x0 0xffe40000 0x0 0x40000>;
  1970. interrupt-parent = <&gic>;
  1971. interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
  1972. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  1973. <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
  1974. interrupt-names = "job", "mmu", "gpu";
  1975. clocks = <&clkc CLKID_MALI>;
  1976. resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
  1977. /*
  1978. * Mali clocking is provided by two identical clock paths
  1979. * MALI_0 and MALI_1 muxed to a single clock by a glitch
  1980. * free mux to safely change frequency while running.
  1981. */
  1982. assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
  1983. <&clkc CLKID_MALI_0>,
  1984. <&clkc CLKID_MALI>; /* Glitch free mux */
  1985. assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
  1986. <0>, /* Do Nothing */
  1987. <&clkc CLKID_MALI_0>;
  1988. assigned-clock-rates = <0>, /* Do Nothing */
  1989. <800000000>,
  1990. <0>; /* Do Nothing */
  1991. #cooling-cells = <2>;
  1992. };
  1993. };
  1994. timer {
  1995. compatible = "arm,armv8-timer";
  1996. interrupts = <GIC_PPI 13
  1997. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  1998. <GIC_PPI 14
  1999. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  2000. <GIC_PPI 11
  2001. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  2002. <GIC_PPI 10
  2003. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  2004. arm,no-tick-in-suspend;
  2005. };
  2006. xtal: xtal-clk {
  2007. compatible = "fixed-clock";
  2008. clock-frequency = <24000000>;
  2009. clock-output-names = "xtal";
  2010. #clock-cells = <0>;
  2011. };
  2012. };