spi-nor-core.c 102 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
  4. * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
  5. *
  6. * Copyright (C) 2005, Intec Automation Inc.
  7. * Copyright (C) 2014, Freescale Semiconductor, Inc.
  8. *
  9. * Synced from Linux v4.19
  10. */
  11. #include <common.h>
  12. #include <flash.h>
  13. #include <log.h>
  14. #include <watchdog.h>
  15. #include <dm.h>
  16. #include <dm/device_compat.h>
  17. #include <dm/devres.h>
  18. #include <linux/bitops.h>
  19. #include <linux/err.h>
  20. #include <linux/errno.h>
  21. #include <linux/log2.h>
  22. #include <linux/math64.h>
  23. #include <linux/sizes.h>
  24. #include <linux/bitfield.h>
  25. #include <linux/delay.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/spi-nor.h>
  28. #include <mtd/cfi_flash.h>
  29. #include <spi-mem.h>
  30. #include <spi.h>
  31. #include "sf_internal.h"
  32. /* Define max times to check status register before we give up. */
  33. /*
  34. * For everything but full-chip erase; probably could be much smaller, but kept
  35. * around for safety for now
  36. */
  37. #define HZ CONFIG_SYS_HZ
  38. #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
  39. #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
  40. struct sfdp_parameter_header {
  41. u8 id_lsb;
  42. u8 minor;
  43. u8 major;
  44. u8 length; /* in double words */
  45. u8 parameter_table_pointer[3]; /* byte address */
  46. u8 id_msb;
  47. };
  48. #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
  49. #define SFDP_PARAM_HEADER_PTP(p) \
  50. (((p)->parameter_table_pointer[2] << 16) | \
  51. ((p)->parameter_table_pointer[1] << 8) | \
  52. ((p)->parameter_table_pointer[0] << 0))
  53. #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
  54. #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
  55. #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
  56. #define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */
  57. #define SFDP_SIGNATURE 0x50444653U
  58. #define SFDP_JESD216_MAJOR 1
  59. #define SFDP_JESD216_MINOR 0
  60. #define SFDP_JESD216A_MINOR 5
  61. #define SFDP_JESD216B_MINOR 6
  62. struct sfdp_header {
  63. u32 signature; /* Ox50444653U <=> "SFDP" */
  64. u8 minor;
  65. u8 major;
  66. u8 nph; /* 0-base number of parameter headers */
  67. u8 unused;
  68. /* Basic Flash Parameter Table. */
  69. struct sfdp_parameter_header bfpt_header;
  70. };
  71. /* Basic Flash Parameter Table */
  72. /*
  73. * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs.
  74. * They are indexed from 1 but C arrays are indexed from 0.
  75. */
  76. #define BFPT_DWORD(i) ((i) - 1)
  77. #define BFPT_DWORD_MAX 20
  78. /* The first version of JESB216 defined only 9 DWORDs. */
  79. #define BFPT_DWORD_MAX_JESD216 9
  80. #define BFPT_DWORD_MAX_JESD216B 16
  81. /* 1st DWORD. */
  82. #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
  83. #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
  84. #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
  85. #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
  86. #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
  87. #define BFPT_DWORD1_DTR BIT(19)
  88. #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
  89. #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
  90. #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
  91. /* 5th DWORD. */
  92. #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
  93. #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
  94. /* 11th DWORD. */
  95. #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
  96. #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
  97. /* 15th DWORD. */
  98. /*
  99. * (from JESD216 rev B)
  100. * Quad Enable Requirements (QER):
  101. * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
  102. * reads based on instruction. DQ3/HOLD# functions are hold during
  103. * instruction phase.
  104. * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
  105. * two data bytes where bit 1 of the second byte is one.
  106. * [...]
  107. * Writing only one byte to the status register has the side-effect of
  108. * clearing status register 2, including the QE bit. The 100b code is
  109. * used if writing one byte to the status register does not modify
  110. * status register 2.
  111. * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
  112. * one data byte where bit 6 is one.
  113. * [...]
  114. * - 011b: QE is bit 7 of status register 2. It is set via Write status
  115. * register 2 instruction 3Eh with one data byte where bit 7 is one.
  116. * [...]
  117. * The status register 2 is read using instruction 3Fh.
  118. * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
  119. * two data bytes where bit 1 of the second byte is one.
  120. * [...]
  121. * In contrast to the 001b code, writing one byte to the status
  122. * register does not modify status register 2.
  123. * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
  124. * Read Status instruction 05h. Status register2 is read using
  125. * instruction 35h. QE is set via Writ Status instruction 01h with
  126. * two data bytes where bit 1 of the second byte is one.
  127. * [...]
  128. */
  129. #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
  130. #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
  131. #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
  132. #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
  133. #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
  134. #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
  135. #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
  136. #define BFPT_DWORD16_SOFT_RST BIT(12)
  137. #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29)
  138. #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */
  139. #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */
  140. #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */
  141. #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
  142. /* xSPI Profile 1.0 table (from JESD216D.01). */
  143. #define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8)
  144. #define PROFILE1_DWORD1_RDSR_DUMMY BIT(28)
  145. #define PROFILE1_DWORD1_RDSR_ADDR_BYTES BIT(29)
  146. #define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7)
  147. #define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27)
  148. #define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17)
  149. #define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)
  150. #define PROFILE1_DUMMY_DEFAULT 20
  151. struct sfdp_bfpt {
  152. u32 dwords[BFPT_DWORD_MAX];
  153. };
  154. /**
  155. * struct spi_nor_fixups - SPI NOR fixup hooks
  156. * @default_init: called after default flash parameters init. Used to tweak
  157. * flash parameters when information provided by the flash_info
  158. * table is incomplete or wrong.
  159. * @post_bfpt: called after the BFPT table has been parsed
  160. * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
  161. * that do not support RDSFDP). Typically used to tweak various
  162. * parameters that could not be extracted by other means (i.e.
  163. * when information provided by the SFDP/flash_info tables are
  164. * incomplete or wrong).
  165. *
  166. * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
  167. * table is broken or not available.
  168. */
  169. struct spi_nor_fixups {
  170. void (*default_init)(struct spi_nor *nor);
  171. int (*post_bfpt)(struct spi_nor *nor,
  172. const struct sfdp_parameter_header *bfpt_header,
  173. const struct sfdp_bfpt *bfpt,
  174. struct spi_nor_flash_parameter *params);
  175. void (*post_sfdp)(struct spi_nor *nor,
  176. struct spi_nor_flash_parameter *params);
  177. };
  178. #define SPI_NOR_SRST_SLEEP_LEN 200
  179. /**
  180. * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
  181. * extension type.
  182. * @nor: pointer to a 'struct spi_nor'
  183. * @op: pointer to the 'struct spi_mem_op' whose properties
  184. * need to be initialized.
  185. *
  186. * Right now, only "repeat" and "invert" are supported.
  187. *
  188. * Return: The opcode extension.
  189. */
  190. static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
  191. const struct spi_mem_op *op)
  192. {
  193. switch (nor->cmd_ext_type) {
  194. case SPI_NOR_EXT_INVERT:
  195. return ~op->cmd.opcode;
  196. case SPI_NOR_EXT_REPEAT:
  197. return op->cmd.opcode;
  198. default:
  199. dev_dbg(nor->dev, "Unknown command extension type\n");
  200. return 0;
  201. }
  202. }
  203. /**
  204. * spi_nor_setup_op() - Set up common properties of a spi-mem op.
  205. * @nor: pointer to a 'struct spi_nor'
  206. * @op: pointer to the 'struct spi_mem_op' whose properties
  207. * need to be initialized.
  208. * @proto: the protocol from which the properties need to be set.
  209. */
  210. static void spi_nor_setup_op(const struct spi_nor *nor,
  211. struct spi_mem_op *op,
  212. const enum spi_nor_protocol proto)
  213. {
  214. u8 ext;
  215. op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
  216. if (op->addr.nbytes)
  217. op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
  218. if (op->dummy.nbytes)
  219. op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
  220. if (op->data.nbytes)
  221. op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
  222. if (spi_nor_protocol_is_dtr(proto)) {
  223. /*
  224. * spi-mem supports mixed DTR modes, but right now we can only
  225. * have all phases either DTR or STR. IOW, spi-mem can have
  226. * something like 4S-4D-4D, but spi-nor can't. So, set all 4
  227. * phases to either DTR or STR.
  228. */
  229. op->cmd.dtr = op->addr.dtr = op->dummy.dtr =
  230. op->data.dtr = true;
  231. /* 2 bytes per clock cycle in DTR mode. */
  232. op->dummy.nbytes *= 2;
  233. ext = spi_nor_get_cmd_ext(nor, op);
  234. op->cmd.opcode = (op->cmd.opcode << 8) | ext;
  235. op->cmd.nbytes = 2;
  236. }
  237. }
  238. static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
  239. *op, void *buf)
  240. {
  241. if (op->data.dir == SPI_MEM_DATA_IN)
  242. op->data.buf.in = buf;
  243. else
  244. op->data.buf.out = buf;
  245. return spi_mem_exec_op(nor->spi, op);
  246. }
  247. static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
  248. {
  249. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 0),
  250. SPI_MEM_OP_NO_ADDR,
  251. SPI_MEM_OP_NO_DUMMY,
  252. SPI_MEM_OP_DATA_IN(len, NULL, 0));
  253. int ret;
  254. spi_nor_setup_op(nor, &op, nor->reg_proto);
  255. ret = spi_nor_read_write_reg(nor, &op, val);
  256. if (ret < 0)
  257. dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
  258. return ret;
  259. }
  260. static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  261. {
  262. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),
  263. SPI_MEM_OP_NO_ADDR,
  264. SPI_MEM_OP_NO_DUMMY,
  265. SPI_MEM_OP_DATA_OUT(len, NULL, 0));
  266. spi_nor_setup_op(nor, &op, nor->reg_proto);
  267. if (len == 0)
  268. op.data.dir = SPI_MEM_NO_DATA;
  269. return spi_nor_read_write_reg(nor, &op, buf);
  270. }
  271. #ifdef CONFIG_SPI_FLASH_SPANSION
  272. static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy,
  273. u8 *val)
  274. {
  275. struct spi_mem_op op =
  276. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1),
  277. SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
  278. SPI_MEM_OP_DUMMY(dummy / 8, 1),
  279. SPI_MEM_OP_DATA_IN(1, NULL, 1));
  280. return spi_nor_read_write_reg(nor, &op, val);
  281. }
  282. static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val)
  283. {
  284. struct spi_mem_op op =
  285. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1),
  286. SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
  287. SPI_MEM_OP_NO_DUMMY,
  288. SPI_MEM_OP_DATA_OUT(1, NULL, 1));
  289. return spi_nor_read_write_reg(nor, &op, &val);
  290. }
  291. #endif
  292. static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
  293. u_char *buf)
  294. {
  295. struct spi_mem_op op =
  296. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
  297. SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
  298. SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
  299. SPI_MEM_OP_DATA_IN(len, buf, 0));
  300. size_t remaining = len;
  301. int ret;
  302. spi_nor_setup_op(nor, &op, nor->read_proto);
  303. /* convert the dummy cycles to the number of bytes */
  304. op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
  305. if (spi_nor_protocol_is_dtr(nor->read_proto))
  306. op.dummy.nbytes *= 2;
  307. while (remaining) {
  308. op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
  309. ret = spi_mem_adjust_op_size(nor->spi, &op);
  310. if (ret)
  311. return ret;
  312. ret = spi_mem_exec_op(nor->spi, &op);
  313. if (ret)
  314. return ret;
  315. op.addr.val += op.data.nbytes;
  316. remaining -= op.data.nbytes;
  317. op.data.buf.in += op.data.nbytes;
  318. }
  319. return len;
  320. }
  321. static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
  322. const u_char *buf)
  323. {
  324. struct spi_mem_op op =
  325. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
  326. SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
  327. SPI_MEM_OP_NO_DUMMY,
  328. SPI_MEM_OP_DATA_OUT(len, buf, 0));
  329. int ret;
  330. if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
  331. op.addr.nbytes = 0;
  332. spi_nor_setup_op(nor, &op, nor->write_proto);
  333. ret = spi_mem_adjust_op_size(nor->spi, &op);
  334. if (ret)
  335. return ret;
  336. op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
  337. ret = spi_mem_exec_op(nor->spi, &op);
  338. if (ret)
  339. return ret;
  340. return op.data.nbytes;
  341. }
  342. /*
  343. * Read the status register, returning its value in the location
  344. * Return the status register value.
  345. * Returns negative if error occurred.
  346. */
  347. static int read_sr(struct spi_nor *nor)
  348. {
  349. struct spi_mem_op op;
  350. int ret;
  351. u8 val[2];
  352. u8 addr_nbytes, dummy;
  353. if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
  354. addr_nbytes = nor->rdsr_addr_nbytes;
  355. dummy = nor->rdsr_dummy;
  356. } else {
  357. addr_nbytes = 0;
  358. dummy = 0;
  359. }
  360. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0),
  361. SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
  362. SPI_MEM_OP_DUMMY(dummy, 0),
  363. SPI_MEM_OP_DATA_IN(1, NULL, 0));
  364. spi_nor_setup_op(nor, &op, nor->reg_proto);
  365. /*
  366. * We don't want to read only one byte in DTR mode. So, read 2 and then
  367. * discard the second byte.
  368. */
  369. if (spi_nor_protocol_is_dtr(nor->reg_proto))
  370. op.data.nbytes = 2;
  371. ret = spi_nor_read_write_reg(nor, &op, val);
  372. if (ret < 0) {
  373. pr_debug("error %d reading SR\n", (int)ret);
  374. return ret;
  375. }
  376. return *val;
  377. }
  378. /*
  379. * Read the flag status register, returning its value in the location
  380. * Return the status register value.
  381. * Returns negative if error occurred.
  382. */
  383. static int read_fsr(struct spi_nor *nor)
  384. {
  385. struct spi_mem_op op;
  386. int ret;
  387. u8 val[2];
  388. u8 addr_nbytes, dummy;
  389. if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
  390. addr_nbytes = nor->rdsr_addr_nbytes;
  391. dummy = nor->rdsr_dummy;
  392. } else {
  393. addr_nbytes = 0;
  394. dummy = 0;
  395. }
  396. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
  397. SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
  398. SPI_MEM_OP_DUMMY(dummy, 0),
  399. SPI_MEM_OP_DATA_IN(1, NULL, 0));
  400. spi_nor_setup_op(nor, &op, nor->reg_proto);
  401. /*
  402. * We don't want to read only one byte in DTR mode. So, read 2 and then
  403. * discard the second byte.
  404. */
  405. if (spi_nor_protocol_is_dtr(nor->reg_proto))
  406. op.data.nbytes = 2;
  407. ret = spi_nor_read_write_reg(nor, &op, val);
  408. if (ret < 0) {
  409. pr_debug("error %d reading FSR\n", ret);
  410. return ret;
  411. }
  412. return *val;
  413. }
  414. /*
  415. * Read configuration register, returning its value in the
  416. * location. Return the configuration register value.
  417. * Returns negative if error occurred.
  418. */
  419. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  420. static int read_cr(struct spi_nor *nor)
  421. {
  422. int ret;
  423. u8 val;
  424. ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
  425. if (ret < 0) {
  426. dev_dbg(nor->dev, "error %d reading CR\n", ret);
  427. return ret;
  428. }
  429. return val;
  430. }
  431. #endif
  432. /*
  433. * Write status register 1 byte
  434. * Returns negative if error occurred.
  435. */
  436. static int write_sr(struct spi_nor *nor, u8 val)
  437. {
  438. nor->cmd_buf[0] = val;
  439. return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
  440. }
  441. /*
  442. * Set write enable latch with Write Enable command.
  443. * Returns negative if error occurred.
  444. */
  445. static int write_enable(struct spi_nor *nor)
  446. {
  447. return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
  448. }
  449. /*
  450. * Send write disable instruction to the chip.
  451. */
  452. static int write_disable(struct spi_nor *nor)
  453. {
  454. return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
  455. }
  456. static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
  457. {
  458. return mtd->priv;
  459. }
  460. #ifndef CONFIG_SPI_FLASH_BAR
  461. static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
  462. {
  463. size_t i;
  464. for (i = 0; i < size; i++)
  465. if (table[i][0] == opcode)
  466. return table[i][1];
  467. /* No conversion found, keep input op code. */
  468. return opcode;
  469. }
  470. static u8 spi_nor_convert_3to4_read(u8 opcode)
  471. {
  472. static const u8 spi_nor_3to4_read[][2] = {
  473. { SPINOR_OP_READ, SPINOR_OP_READ_4B },
  474. { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
  475. { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
  476. { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
  477. { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
  478. { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
  479. { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
  480. { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
  481. { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
  482. { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
  483. { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
  484. };
  485. return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
  486. ARRAY_SIZE(spi_nor_3to4_read));
  487. }
  488. static u8 spi_nor_convert_3to4_program(u8 opcode)
  489. {
  490. static const u8 spi_nor_3to4_program[][2] = {
  491. { SPINOR_OP_PP, SPINOR_OP_PP_4B },
  492. { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
  493. { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
  494. { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
  495. { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
  496. };
  497. return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
  498. ARRAY_SIZE(spi_nor_3to4_program));
  499. }
  500. static u8 spi_nor_convert_3to4_erase(u8 opcode)
  501. {
  502. static const u8 spi_nor_3to4_erase[][2] = {
  503. { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
  504. { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
  505. { SPINOR_OP_SE, SPINOR_OP_SE_4B },
  506. };
  507. return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
  508. ARRAY_SIZE(spi_nor_3to4_erase));
  509. }
  510. static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
  511. const struct flash_info *info)
  512. {
  513. /* Do some manufacturer fixups first */
  514. switch (JEDEC_MFR(info)) {
  515. case SNOR_MFR_SPANSION:
  516. /* No small sector erase for 4-byte command set */
  517. nor->erase_opcode = SPINOR_OP_SE;
  518. nor->mtd.erasesize = info->sector_size;
  519. break;
  520. default:
  521. break;
  522. }
  523. nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
  524. nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
  525. nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
  526. }
  527. #endif /* !CONFIG_SPI_FLASH_BAR */
  528. /* Enable/disable 4-byte addressing mode. */
  529. static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  530. int enable)
  531. {
  532. int status;
  533. bool need_wren = false;
  534. u8 cmd;
  535. switch (JEDEC_MFR(info)) {
  536. case SNOR_MFR_ST:
  537. case SNOR_MFR_MICRON:
  538. case SNOR_MFR_GIGADEVICE:
  539. /* Some Micron need WREN command; all will accept it */
  540. need_wren = true;
  541. case SNOR_MFR_ISSI:
  542. case SNOR_MFR_MACRONIX:
  543. case SNOR_MFR_WINBOND:
  544. if (need_wren)
  545. write_enable(nor);
  546. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
  547. status = nor->write_reg(nor, cmd, NULL, 0);
  548. if (need_wren)
  549. write_disable(nor);
  550. if (!status && !enable &&
  551. JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
  552. /*
  553. * On Winbond W25Q256FV, leaving 4byte mode causes
  554. * the Extended Address Register to be set to 1, so all
  555. * 3-byte-address reads come from the second 16M.
  556. * We must clear the register to enable normal behavior.
  557. */
  558. write_enable(nor);
  559. nor->cmd_buf[0] = 0;
  560. nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
  561. write_disable(nor);
  562. }
  563. return status;
  564. case SNOR_MFR_CYPRESS:
  565. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS;
  566. return nor->write_reg(nor, cmd, NULL, 0);
  567. default:
  568. /* Spansion style */
  569. nor->cmd_buf[0] = enable << 7;
  570. return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
  571. }
  572. }
  573. #ifdef CONFIG_SPI_FLASH_SPANSION
  574. /*
  575. * Read status register 1 by using Read Any Register command to support multi
  576. * die package parts.
  577. */
  578. static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy)
  579. {
  580. u32 reg_addr = addr_base + SPINOR_REG_ADDR_STR1V;
  581. u8 sr;
  582. int ret;
  583. ret = spansion_read_any_reg(nor, reg_addr, dummy, &sr);
  584. if (ret < 0)
  585. return ret;
  586. if (sr & (SR_E_ERR | SR_P_ERR)) {
  587. if (sr & SR_E_ERR)
  588. dev_dbg(nor->dev, "Erase Error occurred\n");
  589. else
  590. dev_dbg(nor->dev, "Programming Error occurred\n");
  591. nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
  592. return -EIO;
  593. }
  594. return !(sr & SR_WIP);
  595. }
  596. #endif
  597. static int spi_nor_sr_ready(struct spi_nor *nor)
  598. {
  599. int sr = read_sr(nor);
  600. if (sr < 0)
  601. return sr;
  602. if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
  603. if (sr & SR_E_ERR)
  604. dev_dbg(nor->dev, "Erase Error occurred\n");
  605. else
  606. dev_dbg(nor->dev, "Programming Error occurred\n");
  607. nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
  608. return -EIO;
  609. }
  610. return !(sr & SR_WIP);
  611. }
  612. static int spi_nor_fsr_ready(struct spi_nor *nor)
  613. {
  614. int fsr = read_fsr(nor);
  615. if (fsr < 0)
  616. return fsr;
  617. if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
  618. if (fsr & FSR_E_ERR)
  619. dev_err(nor->dev, "Erase operation failed.\n");
  620. else
  621. dev_err(nor->dev, "Program operation failed.\n");
  622. if (fsr & FSR_PT_ERR)
  623. dev_err(nor->dev,
  624. "Attempted to modify a protected sector.\n");
  625. nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
  626. return -EIO;
  627. }
  628. return fsr & FSR_READY;
  629. }
  630. static int spi_nor_default_ready(struct spi_nor *nor)
  631. {
  632. int sr, fsr;
  633. sr = spi_nor_sr_ready(nor);
  634. if (sr < 0)
  635. return sr;
  636. fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
  637. if (fsr < 0)
  638. return fsr;
  639. return sr && fsr;
  640. }
  641. static int spi_nor_ready(struct spi_nor *nor)
  642. {
  643. if (nor->ready)
  644. return nor->ready(nor);
  645. return spi_nor_default_ready(nor);
  646. }
  647. /*
  648. * Service routine to read status register until ready, or timeout occurs.
  649. * Returns non-zero if error.
  650. */
  651. static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
  652. unsigned long timeout)
  653. {
  654. unsigned long timebase;
  655. int ret;
  656. timebase = get_timer(0);
  657. while (get_timer(timebase) < timeout) {
  658. ret = spi_nor_ready(nor);
  659. if (ret < 0)
  660. return ret;
  661. if (ret)
  662. return 0;
  663. }
  664. dev_err(nor->dev, "flash operation timed out\n");
  665. return -ETIMEDOUT;
  666. }
  667. static int spi_nor_wait_till_ready(struct spi_nor *nor)
  668. {
  669. return spi_nor_wait_till_ready_with_timeout(nor,
  670. DEFAULT_READY_WAIT_JIFFIES);
  671. }
  672. #ifdef CONFIG_SPI_FLASH_BAR
  673. /*
  674. * This "clean_bar" is necessary in a situation when one was accessing
  675. * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
  676. *
  677. * After it the BA24 bit shall be cleared to allow access to correct
  678. * memory region after SW reset (by calling "reset" command).
  679. *
  680. * Otherwise, the BA24 bit may be left set and then after reset, the
  681. * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
  682. */
  683. static int clean_bar(struct spi_nor *nor)
  684. {
  685. u8 cmd, bank_sel = 0;
  686. if (nor->bank_curr == 0)
  687. return 0;
  688. cmd = nor->bank_write_cmd;
  689. nor->bank_curr = 0;
  690. write_enable(nor);
  691. return nor->write_reg(nor, cmd, &bank_sel, 1);
  692. }
  693. static int write_bar(struct spi_nor *nor, u32 offset)
  694. {
  695. u8 cmd, bank_sel;
  696. int ret;
  697. bank_sel = offset / SZ_16M;
  698. if (bank_sel == nor->bank_curr)
  699. goto bar_end;
  700. cmd = nor->bank_write_cmd;
  701. write_enable(nor);
  702. ret = nor->write_reg(nor, cmd, &bank_sel, 1);
  703. if (ret < 0) {
  704. debug("SF: fail to write bank register\n");
  705. return ret;
  706. }
  707. bar_end:
  708. nor->bank_curr = bank_sel;
  709. return nor->bank_curr;
  710. }
  711. static int read_bar(struct spi_nor *nor, const struct flash_info *info)
  712. {
  713. u8 curr_bank = 0;
  714. int ret;
  715. switch (JEDEC_MFR(info)) {
  716. case SNOR_MFR_SPANSION:
  717. nor->bank_read_cmd = SPINOR_OP_BRRD;
  718. nor->bank_write_cmd = SPINOR_OP_BRWR;
  719. break;
  720. default:
  721. nor->bank_read_cmd = SPINOR_OP_RDEAR;
  722. nor->bank_write_cmd = SPINOR_OP_WREAR;
  723. }
  724. ret = nor->read_reg(nor, nor->bank_read_cmd,
  725. &curr_bank, 1);
  726. if (ret) {
  727. debug("SF: fail to read bank addr register\n");
  728. return ret;
  729. }
  730. nor->bank_curr = curr_bank;
  731. return 0;
  732. }
  733. #endif
  734. /*
  735. * Initiate the erasure of a single sector. Returns the number of bytes erased
  736. * on success, a negative error code on error.
  737. */
  738. static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
  739. {
  740. struct spi_mem_op op =
  741. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
  742. SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
  743. SPI_MEM_OP_NO_DUMMY,
  744. SPI_MEM_OP_NO_DATA);
  745. int ret;
  746. spi_nor_setup_op(nor, &op, nor->write_proto);
  747. if (nor->erase)
  748. return nor->erase(nor, addr);
  749. /*
  750. * Default implementation, if driver doesn't have a specialized HW
  751. * control
  752. */
  753. ret = spi_mem_exec_op(nor->spi, &op);
  754. if (ret)
  755. return ret;
  756. return nor->mtd.erasesize;
  757. }
  758. /*
  759. * Erase an address range on the nor chip. The address range may extend
  760. * one or more erase sectors. Return an error is there is a problem erasing.
  761. */
  762. static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
  763. {
  764. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  765. u32 addr, len, rem;
  766. int ret;
  767. dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
  768. (long long)instr->len);
  769. if (!instr->len)
  770. return 0;
  771. div_u64_rem(instr->len, mtd->erasesize, &rem);
  772. if (rem)
  773. return -EINVAL;
  774. addr = instr->addr;
  775. len = instr->len;
  776. while (len) {
  777. WATCHDOG_RESET();
  778. #ifdef CONFIG_SPI_FLASH_BAR
  779. ret = write_bar(nor, addr);
  780. if (ret < 0)
  781. return ret;
  782. #endif
  783. write_enable(nor);
  784. ret = spi_nor_erase_sector(nor, addr);
  785. if (ret < 0)
  786. goto erase_err;
  787. addr += ret;
  788. len -= ret;
  789. ret = spi_nor_wait_till_ready(nor);
  790. if (ret)
  791. goto erase_err;
  792. }
  793. erase_err:
  794. #ifdef CONFIG_SPI_FLASH_BAR
  795. ret = clean_bar(nor);
  796. #endif
  797. write_disable(nor);
  798. return ret;
  799. }
  800. #ifdef CONFIG_SPI_FLASH_SPANSION
  801. /**
  802. * spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress
  803. * chips
  804. * @nor: pointer to a 'struct spi_nor'
  805. * @addr: address of the sector to erase
  806. * @opcode_4k: opcode for 4K sector erase
  807. * @ovlsz_top: size of overlaid portion at the top address
  808. * @ovlsz_btm: size of overlaid portion at the bottom address
  809. *
  810. * Erase an address range on the nor chip that can contain 4KB sectors overlaid
  811. * on top and/or bottom. The appropriate erase opcode and size are chosen by
  812. * address to erase and size of overlaid portion.
  813. *
  814. * Return: number of bytes erased on success, -errno otherwise.
  815. */
  816. static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr,
  817. u8 opcode_4k, u32 ovlsz_top,
  818. u32 ovlsz_btm)
  819. {
  820. struct spi_mem_op op =
  821. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
  822. SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
  823. SPI_MEM_OP_NO_DUMMY,
  824. SPI_MEM_OP_NO_DATA);
  825. struct mtd_info *mtd = &nor->mtd;
  826. u32 erasesize;
  827. int ret;
  828. /* 4KB sectors */
  829. if (op.addr.val < ovlsz_btm ||
  830. op.addr.val >= mtd->size - ovlsz_top) {
  831. op.cmd.opcode = opcode_4k;
  832. erasesize = SZ_4K;
  833. /* Non-overlaid portion in the normal sector at the bottom */
  834. } else if (op.addr.val == ovlsz_btm) {
  835. op.cmd.opcode = nor->erase_opcode;
  836. erasesize = mtd->erasesize - ovlsz_btm;
  837. /* Non-overlaid portion in the normal sector at the top */
  838. } else if (op.addr.val == mtd->size - mtd->erasesize) {
  839. op.cmd.opcode = nor->erase_opcode;
  840. erasesize = mtd->erasesize - ovlsz_top;
  841. /* Normal sectors */
  842. } else {
  843. op.cmd.opcode = nor->erase_opcode;
  844. erasesize = mtd->erasesize;
  845. }
  846. spi_nor_setup_op(nor, &op, nor->write_proto);
  847. ret = spi_mem_exec_op(nor->spi, &op);
  848. if (ret)
  849. return ret;
  850. return erasesize;
  851. }
  852. #endif
  853. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  854. /* Write status register and ensure bits in mask match written values */
  855. static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
  856. {
  857. int ret;
  858. write_enable(nor);
  859. ret = write_sr(nor, status_new);
  860. if (ret)
  861. return ret;
  862. ret = spi_nor_wait_till_ready(nor);
  863. if (ret)
  864. return ret;
  865. ret = read_sr(nor);
  866. if (ret < 0)
  867. return ret;
  868. return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
  869. }
  870. static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
  871. uint64_t *len)
  872. {
  873. struct mtd_info *mtd = &nor->mtd;
  874. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  875. int shift = ffs(mask) - 1;
  876. int pow;
  877. if (!(sr & mask)) {
  878. /* No protection */
  879. *ofs = 0;
  880. *len = 0;
  881. } else {
  882. pow = ((sr & mask) ^ mask) >> shift;
  883. *len = mtd->size >> pow;
  884. if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
  885. *ofs = 0;
  886. else
  887. *ofs = mtd->size - *len;
  888. }
  889. }
  890. /*
  891. * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
  892. * @locked is false); 0 otherwise
  893. */
  894. static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
  895. u8 sr, bool locked)
  896. {
  897. loff_t lock_offs;
  898. uint64_t lock_len;
  899. if (!len)
  900. return 1;
  901. stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
  902. if (locked)
  903. /* Requested range is a sub-range of locked range */
  904. return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
  905. else
  906. /* Requested range does not overlap with locked range */
  907. return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
  908. }
  909. static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  910. u8 sr)
  911. {
  912. return stm_check_lock_status_sr(nor, ofs, len, sr, true);
  913. }
  914. static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  915. u8 sr)
  916. {
  917. return stm_check_lock_status_sr(nor, ofs, len, sr, false);
  918. }
  919. /*
  920. * Lock a region of the flash. Compatible with ST Micro and similar flash.
  921. * Supports the block protection bits BP{0,1,2} in the status register
  922. * (SR). Does not support these features found in newer SR bitfields:
  923. * - SEC: sector/block protect - only handle SEC=0 (block protect)
  924. * - CMP: complement protect - only support CMP=0 (range is not complemented)
  925. *
  926. * Support for the following is provided conditionally for some flash:
  927. * - TB: top/bottom protect
  928. *
  929. * Sample table portion for 8MB flash (Winbond w25q64fw):
  930. *
  931. * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
  932. * --------------------------------------------------------------------------
  933. * X | X | 0 | 0 | 0 | NONE | NONE
  934. * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
  935. * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
  936. * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
  937. * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
  938. * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
  939. * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
  940. * X | X | 1 | 1 | 1 | 8 MB | ALL
  941. * ------|-------|-------|-------|-------|---------------|-------------------
  942. * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
  943. * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
  944. * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
  945. * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
  946. * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
  947. * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
  948. *
  949. * Returns negative on errors, 0 on success.
  950. */
  951. static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  952. {
  953. struct mtd_info *mtd = &nor->mtd;
  954. int status_old, status_new;
  955. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  956. u8 shift = ffs(mask) - 1, pow, val;
  957. loff_t lock_len;
  958. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  959. bool use_top;
  960. status_old = read_sr(nor);
  961. if (status_old < 0)
  962. return status_old;
  963. /* If nothing in our range is unlocked, we don't need to do anything */
  964. if (stm_is_locked_sr(nor, ofs, len, status_old))
  965. return 0;
  966. /* If anything below us is unlocked, we can't use 'bottom' protection */
  967. if (!stm_is_locked_sr(nor, 0, ofs, status_old))
  968. can_be_bottom = false;
  969. /* If anything above us is unlocked, we can't use 'top' protection */
  970. if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
  971. status_old))
  972. can_be_top = false;
  973. if (!can_be_bottom && !can_be_top)
  974. return -EINVAL;
  975. /* Prefer top, if both are valid */
  976. use_top = can_be_top;
  977. /* lock_len: length of region that should end up locked */
  978. if (use_top)
  979. lock_len = mtd->size - ofs;
  980. else
  981. lock_len = ofs + len;
  982. /*
  983. * Need smallest pow such that:
  984. *
  985. * 1 / (2^pow) <= (len / size)
  986. *
  987. * so (assuming power-of-2 size) we do:
  988. *
  989. * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
  990. */
  991. pow = ilog2(mtd->size) - ilog2(lock_len);
  992. val = mask - (pow << shift);
  993. if (val & ~mask)
  994. return -EINVAL;
  995. /* Don't "lock" with no region! */
  996. if (!(val & mask))
  997. return -EINVAL;
  998. status_new = (status_old & ~mask & ~SR_TB) | val;
  999. /* Disallow further writes if WP pin is asserted */
  1000. status_new |= SR_SRWD;
  1001. if (!use_top)
  1002. status_new |= SR_TB;
  1003. /* Don't bother if they're the same */
  1004. if (status_new == status_old)
  1005. return 0;
  1006. /* Only modify protection if it will not unlock other areas */
  1007. if ((status_new & mask) < (status_old & mask))
  1008. return -EINVAL;
  1009. return write_sr_and_check(nor, status_new, mask);
  1010. }
  1011. /*
  1012. * Unlock a region of the flash. See stm_lock() for more info
  1013. *
  1014. * Returns negative on errors, 0 on success.
  1015. */
  1016. static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1017. {
  1018. struct mtd_info *mtd = &nor->mtd;
  1019. int status_old, status_new;
  1020. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  1021. u8 shift = ffs(mask) - 1, pow, val;
  1022. loff_t lock_len;
  1023. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  1024. bool use_top;
  1025. status_old = read_sr(nor);
  1026. if (status_old < 0)
  1027. return status_old;
  1028. /* If nothing in our range is locked, we don't need to do anything */
  1029. if (stm_is_unlocked_sr(nor, ofs, len, status_old))
  1030. return 0;
  1031. /* If anything below us is locked, we can't use 'top' protection */
  1032. if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
  1033. can_be_top = false;
  1034. /* If anything above us is locked, we can't use 'bottom' protection */
  1035. if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
  1036. status_old))
  1037. can_be_bottom = false;
  1038. if (!can_be_bottom && !can_be_top)
  1039. return -EINVAL;
  1040. /* Prefer top, if both are valid */
  1041. use_top = can_be_top;
  1042. /* lock_len: length of region that should remain locked */
  1043. if (use_top)
  1044. lock_len = mtd->size - (ofs + len);
  1045. else
  1046. lock_len = ofs;
  1047. /*
  1048. * Need largest pow such that:
  1049. *
  1050. * 1 / (2^pow) >= (len / size)
  1051. *
  1052. * so (assuming power-of-2 size) we do:
  1053. *
  1054. * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
  1055. */
  1056. pow = ilog2(mtd->size) - order_base_2(lock_len);
  1057. if (lock_len == 0) {
  1058. val = 0; /* fully unlocked */
  1059. } else {
  1060. val = mask - (pow << shift);
  1061. /* Some power-of-two sizes are not supported */
  1062. if (val & ~mask)
  1063. return -EINVAL;
  1064. }
  1065. status_new = (status_old & ~mask & ~SR_TB) | val;
  1066. /* Don't protect status register if we're fully unlocked */
  1067. if (lock_len == 0)
  1068. status_new &= ~SR_SRWD;
  1069. if (!use_top)
  1070. status_new |= SR_TB;
  1071. /* Don't bother if they're the same */
  1072. if (status_new == status_old)
  1073. return 0;
  1074. /* Only modify protection if it will not lock other areas */
  1075. if ((status_new & mask) > (status_old & mask))
  1076. return -EINVAL;
  1077. return write_sr_and_check(nor, status_new, mask);
  1078. }
  1079. /*
  1080. * Check if a region of the flash is (completely) locked. See stm_lock() for
  1081. * more info.
  1082. *
  1083. * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  1084. * negative on errors.
  1085. */
  1086. static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1087. {
  1088. int status;
  1089. status = read_sr(nor);
  1090. if (status < 0)
  1091. return status;
  1092. return stm_is_locked_sr(nor, ofs, len, status);
  1093. }
  1094. #endif /* CONFIG_SPI_FLASH_STMICRO */
  1095. static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  1096. {
  1097. int tmp;
  1098. u8 id[SPI_NOR_MAX_ID_LEN];
  1099. const struct flash_info *info;
  1100. tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
  1101. if (tmp < 0) {
  1102. dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
  1103. return ERR_PTR(tmp);
  1104. }
  1105. info = spi_nor_ids;
  1106. for (; info->name; info++) {
  1107. if (info->id_len) {
  1108. if (!memcmp(info->id, id, info->id_len))
  1109. return info;
  1110. }
  1111. }
  1112. dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  1113. id[0], id[1], id[2]);
  1114. return ERR_PTR(-ENODEV);
  1115. }
  1116. static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
  1117. size_t *retlen, u_char *buf)
  1118. {
  1119. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1120. int ret;
  1121. dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
  1122. while (len) {
  1123. loff_t addr = from;
  1124. size_t read_len = len;
  1125. #ifdef CONFIG_SPI_FLASH_BAR
  1126. u32 remain_len;
  1127. ret = write_bar(nor, addr);
  1128. if (ret < 0)
  1129. return log_ret(ret);
  1130. remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
  1131. if (len < remain_len)
  1132. read_len = len;
  1133. else
  1134. read_len = remain_len;
  1135. #endif
  1136. ret = nor->read(nor, addr, read_len, buf);
  1137. if (ret == 0) {
  1138. /* We shouldn't see 0-length reads */
  1139. ret = -EIO;
  1140. goto read_err;
  1141. }
  1142. if (ret < 0)
  1143. goto read_err;
  1144. *retlen += ret;
  1145. buf += ret;
  1146. from += ret;
  1147. len -= ret;
  1148. }
  1149. ret = 0;
  1150. read_err:
  1151. #ifdef CONFIG_SPI_FLASH_BAR
  1152. ret = clean_bar(nor);
  1153. #endif
  1154. return ret;
  1155. }
  1156. #ifdef CONFIG_SPI_FLASH_SST
  1157. /*
  1158. * sst26 flash series has its own block protection implementation:
  1159. * 4x - 8 KByte blocks - read & write protection bits - upper addresses
  1160. * 1x - 32 KByte blocks - write protection bits
  1161. * rest - 64 KByte blocks - write protection bits
  1162. * 1x - 32 KByte blocks - write protection bits
  1163. * 4x - 8 KByte blocks - read & write protection bits - lower addresses
  1164. *
  1165. * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
  1166. * will be treated as single block.
  1167. */
  1168. #define SST26_BPR_8K_NUM 4
  1169. #define SST26_MAX_BPR_REG_LEN (18 + 1)
  1170. #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
  1171. enum lock_ctl {
  1172. SST26_CTL_LOCK,
  1173. SST26_CTL_UNLOCK,
  1174. SST26_CTL_CHECK
  1175. };
  1176. static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
  1177. {
  1178. switch (ctl) {
  1179. case SST26_CTL_LOCK:
  1180. cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
  1181. break;
  1182. case SST26_CTL_UNLOCK:
  1183. cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
  1184. break;
  1185. case SST26_CTL_CHECK:
  1186. return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
  1187. }
  1188. return false;
  1189. }
  1190. /*
  1191. * Lock, unlock or check lock status of the flash region of the flash (depending
  1192. * on the lock_ctl value)
  1193. */
  1194. static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
  1195. {
  1196. struct mtd_info *mtd = &nor->mtd;
  1197. u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
  1198. bool lower_64k = false, upper_64k = false;
  1199. u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
  1200. int ret;
  1201. /* Check length and offset for 64k alignment */
  1202. if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
  1203. dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
  1204. return -EINVAL;
  1205. }
  1206. if (ofs + len > mtd->size) {
  1207. dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
  1208. ofs, len, mtd->size);
  1209. return -EINVAL;
  1210. }
  1211. /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
  1212. if (mtd->size != SZ_2M &&
  1213. mtd->size != SZ_4M &&
  1214. mtd->size != SZ_8M)
  1215. return -EINVAL;
  1216. bpr_size = 2 + (mtd->size / SZ_64K / 8);
  1217. ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
  1218. if (ret < 0) {
  1219. dev_err(nor->dev, "fail to read block-protection register\n");
  1220. return ret;
  1221. }
  1222. rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
  1223. lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
  1224. upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
  1225. lower_64k = (ofs < SST26_BOUND_REG_SIZE);
  1226. /* Lower bits in block-protection register are about 64k region */
  1227. bpr_ptr = lptr_64k / SZ_64K - 1;
  1228. /* Process 64K blocks region */
  1229. while (lptr_64k < rptr_64k) {
  1230. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1231. return EACCES;
  1232. bpr_ptr++;
  1233. lptr_64k += SZ_64K;
  1234. }
  1235. /* 32K and 8K region bits in BPR are after 64k region bits */
  1236. bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
  1237. /* Process lower 32K block region */
  1238. if (lower_64k)
  1239. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1240. return EACCES;
  1241. bpr_ptr++;
  1242. /* Process upper 32K block region */
  1243. if (upper_64k)
  1244. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1245. return EACCES;
  1246. bpr_ptr++;
  1247. /* Process lower 8K block regions */
  1248. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  1249. if (lower_64k)
  1250. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1251. return EACCES;
  1252. /* In 8K area BPR has both read and write protection bits */
  1253. bpr_ptr += 2;
  1254. }
  1255. /* Process upper 8K block regions */
  1256. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  1257. if (upper_64k)
  1258. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1259. return EACCES;
  1260. /* In 8K area BPR has both read and write protection bits */
  1261. bpr_ptr += 2;
  1262. }
  1263. /* If we check region status we don't need to write BPR back */
  1264. if (ctl == SST26_CTL_CHECK)
  1265. return 0;
  1266. ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
  1267. if (ret < 0) {
  1268. dev_err(nor->dev, "fail to write block-protection register\n");
  1269. return ret;
  1270. }
  1271. return 0;
  1272. }
  1273. static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1274. {
  1275. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
  1276. }
  1277. static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1278. {
  1279. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
  1280. }
  1281. /*
  1282. * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
  1283. * and negative on errors.
  1284. */
  1285. static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1286. {
  1287. /*
  1288. * is_locked function is used for check before reading or erasing flash
  1289. * region, so offset and length might be not 64k allighned, so adjust
  1290. * them to be 64k allighned as sst26_lock_ctl works only with 64k
  1291. * allighned regions.
  1292. */
  1293. ofs -= ofs & (SZ_64K - 1);
  1294. len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
  1295. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
  1296. }
  1297. static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
  1298. size_t *retlen, const u_char *buf)
  1299. {
  1300. size_t actual;
  1301. int ret = 0;
  1302. for (actual = 0; actual < len; actual++) {
  1303. nor->program_opcode = SPINOR_OP_BP;
  1304. write_enable(nor);
  1305. /* write one byte. */
  1306. ret = nor->write(nor, to, 1, buf + actual);
  1307. if (ret < 0)
  1308. goto sst_write_err;
  1309. ret = spi_nor_wait_till_ready(nor);
  1310. if (ret)
  1311. goto sst_write_err;
  1312. to++;
  1313. }
  1314. sst_write_err:
  1315. write_disable(nor);
  1316. return ret;
  1317. }
  1318. static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
  1319. size_t *retlen, const u_char *buf)
  1320. {
  1321. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1322. struct spi_slave *spi = nor->spi;
  1323. size_t actual;
  1324. int ret;
  1325. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  1326. if (spi->mode & SPI_TX_BYTE)
  1327. return sst_write_byteprogram(nor, to, len, retlen, buf);
  1328. write_enable(nor);
  1329. nor->sst_write_second = false;
  1330. actual = to % 2;
  1331. /* Start write from odd address. */
  1332. if (actual) {
  1333. nor->program_opcode = SPINOR_OP_BP;
  1334. /* write one byte. */
  1335. ret = nor->write(nor, to, 1, buf);
  1336. if (ret < 0)
  1337. goto sst_write_err;
  1338. ret = spi_nor_wait_till_ready(nor);
  1339. if (ret)
  1340. goto sst_write_err;
  1341. }
  1342. to += actual;
  1343. /* Write out most of the data here. */
  1344. for (; actual < len - 1; actual += 2) {
  1345. nor->program_opcode = SPINOR_OP_AAI_WP;
  1346. /* write two bytes. */
  1347. ret = nor->write(nor, to, 2, buf + actual);
  1348. if (ret < 0)
  1349. goto sst_write_err;
  1350. ret = spi_nor_wait_till_ready(nor);
  1351. if (ret)
  1352. goto sst_write_err;
  1353. to += 2;
  1354. nor->sst_write_second = true;
  1355. }
  1356. nor->sst_write_second = false;
  1357. write_disable(nor);
  1358. ret = spi_nor_wait_till_ready(nor);
  1359. if (ret)
  1360. goto sst_write_err;
  1361. /* Write out trailing byte if it exists. */
  1362. if (actual != len) {
  1363. write_enable(nor);
  1364. nor->program_opcode = SPINOR_OP_BP;
  1365. ret = nor->write(nor, to, 1, buf + actual);
  1366. if (ret < 0)
  1367. goto sst_write_err;
  1368. ret = spi_nor_wait_till_ready(nor);
  1369. if (ret)
  1370. goto sst_write_err;
  1371. write_disable(nor);
  1372. actual += 1;
  1373. }
  1374. sst_write_err:
  1375. *retlen += actual;
  1376. return ret;
  1377. }
  1378. #endif
  1379. /*
  1380. * Write an address range to the nor chip. Data must be written in
  1381. * FLASH_PAGESIZE chunks. The address range may be any size provided
  1382. * it is within the physical boundaries.
  1383. */
  1384. static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
  1385. size_t *retlen, const u_char *buf)
  1386. {
  1387. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1388. size_t page_offset, page_remain, i;
  1389. ssize_t ret;
  1390. #ifdef CONFIG_SPI_FLASH_SST
  1391. /* sst nor chips use AAI word program */
  1392. if (nor->info->flags & SST_WRITE)
  1393. return sst_write(mtd, to, len, retlen, buf);
  1394. #endif
  1395. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  1396. if (!len)
  1397. return 0;
  1398. for (i = 0; i < len; ) {
  1399. ssize_t written;
  1400. loff_t addr = to + i;
  1401. WATCHDOG_RESET();
  1402. /*
  1403. * If page_size is a power of two, the offset can be quickly
  1404. * calculated with an AND operation. On the other cases we
  1405. * need to do a modulus operation (more expensive).
  1406. */
  1407. if (is_power_of_2(nor->page_size)) {
  1408. page_offset = addr & (nor->page_size - 1);
  1409. } else {
  1410. u64 aux = addr;
  1411. page_offset = do_div(aux, nor->page_size);
  1412. }
  1413. /* the size of data remaining on the first page */
  1414. page_remain = min_t(size_t,
  1415. nor->page_size - page_offset, len - i);
  1416. #ifdef CONFIG_SPI_FLASH_BAR
  1417. ret = write_bar(nor, addr);
  1418. if (ret < 0)
  1419. return ret;
  1420. #endif
  1421. write_enable(nor);
  1422. ret = nor->write(nor, addr, page_remain, buf + i);
  1423. if (ret < 0)
  1424. goto write_err;
  1425. written = ret;
  1426. ret = spi_nor_wait_till_ready(nor);
  1427. if (ret)
  1428. goto write_err;
  1429. *retlen += written;
  1430. i += written;
  1431. }
  1432. write_err:
  1433. #ifdef CONFIG_SPI_FLASH_BAR
  1434. ret = clean_bar(nor);
  1435. #endif
  1436. return ret;
  1437. }
  1438. #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
  1439. /**
  1440. * macronix_quad_enable() - set QE bit in Status Register.
  1441. * @nor: pointer to a 'struct spi_nor'
  1442. *
  1443. * Set the Quad Enable (QE) bit in the Status Register.
  1444. *
  1445. * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
  1446. *
  1447. * Return: 0 on success, -errno otherwise.
  1448. */
  1449. static int macronix_quad_enable(struct spi_nor *nor)
  1450. {
  1451. int ret, val;
  1452. val = read_sr(nor);
  1453. if (val < 0)
  1454. return val;
  1455. if (val & SR_QUAD_EN_MX)
  1456. return 0;
  1457. write_enable(nor);
  1458. write_sr(nor, val | SR_QUAD_EN_MX);
  1459. ret = spi_nor_wait_till_ready(nor);
  1460. if (ret)
  1461. return ret;
  1462. ret = read_sr(nor);
  1463. if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
  1464. dev_err(nor->dev, "Macronix Quad bit not set\n");
  1465. return -EINVAL;
  1466. }
  1467. return 0;
  1468. }
  1469. #endif
  1470. #ifdef CONFIG_SPI_FLASH_SPANSION
  1471. /**
  1472. * spansion_quad_enable_volatile() - enable Quad I/O mode in volatile register.
  1473. * @nor: pointer to a 'struct spi_nor'
  1474. * @addr_base: base address of register (can be >0 in multi-die parts)
  1475. * @dummy: number of dummy cycles for register read
  1476. *
  1477. * It is recommended to update volatile registers in the field application due
  1478. * to a risk of the non-volatile registers corruption by power interrupt. This
  1479. * function sets Quad Enable bit in CFR1 volatile.
  1480. *
  1481. * Return: 0 on success, -errno otherwise.
  1482. */
  1483. static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base,
  1484. u8 dummy)
  1485. {
  1486. u32 addr = addr_base + SPINOR_REG_ADDR_CFR1V;
  1487. u8 cr;
  1488. int ret;
  1489. /* Check current Quad Enable bit value. */
  1490. ret = spansion_read_any_reg(nor, addr, dummy, &cr);
  1491. if (ret < 0) {
  1492. dev_dbg(nor->dev,
  1493. "error while reading configuration register\n");
  1494. return -EINVAL;
  1495. }
  1496. if (cr & CR_QUAD_EN_SPAN)
  1497. return 0;
  1498. cr |= CR_QUAD_EN_SPAN;
  1499. write_enable(nor);
  1500. ret = spansion_write_any_reg(nor, addr, cr);
  1501. if (ret < 0) {
  1502. dev_dbg(nor->dev,
  1503. "error while writing configuration register\n");
  1504. return -EINVAL;
  1505. }
  1506. /* Read back and check it. */
  1507. ret = spansion_read_any_reg(nor, addr, dummy, &cr);
  1508. if (ret || !(cr & CR_QUAD_EN_SPAN)) {
  1509. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  1510. return -EINVAL;
  1511. }
  1512. return 0;
  1513. }
  1514. #endif
  1515. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1516. /*
  1517. * Write status Register and configuration register with 2 bytes
  1518. * The first byte will be written to the status register, while the
  1519. * second byte will be written to the configuration register.
  1520. * Return negative if error occurred.
  1521. */
  1522. static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
  1523. {
  1524. int ret;
  1525. write_enable(nor);
  1526. ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
  1527. if (ret < 0) {
  1528. dev_dbg(nor->dev,
  1529. "error while writing configuration register\n");
  1530. return -EINVAL;
  1531. }
  1532. ret = spi_nor_wait_till_ready(nor);
  1533. if (ret) {
  1534. dev_dbg(nor->dev,
  1535. "timeout while writing configuration register\n");
  1536. return ret;
  1537. }
  1538. return 0;
  1539. }
  1540. /**
  1541. * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
  1542. * @nor: pointer to a 'struct spi_nor'
  1543. *
  1544. * Set the Quad Enable (QE) bit in the Configuration Register.
  1545. * This function should be used with QSPI memories supporting the Read
  1546. * Configuration Register (35h) instruction.
  1547. *
  1548. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1549. * memories.
  1550. *
  1551. * Return: 0 on success, -errno otherwise.
  1552. */
  1553. static int spansion_read_cr_quad_enable(struct spi_nor *nor)
  1554. {
  1555. u8 sr_cr[2];
  1556. int ret;
  1557. /* Check current Quad Enable bit value. */
  1558. ret = read_cr(nor);
  1559. if (ret < 0) {
  1560. dev_dbg(nor->dev,
  1561. "error while reading configuration register\n");
  1562. return -EINVAL;
  1563. }
  1564. if (ret & CR_QUAD_EN_SPAN)
  1565. return 0;
  1566. sr_cr[1] = ret | CR_QUAD_EN_SPAN;
  1567. /* Keep the current value of the Status Register. */
  1568. ret = read_sr(nor);
  1569. if (ret < 0) {
  1570. dev_dbg(nor->dev, "error while reading status register\n");
  1571. return -EINVAL;
  1572. }
  1573. sr_cr[0] = ret;
  1574. ret = write_sr_cr(nor, sr_cr);
  1575. if (ret)
  1576. return ret;
  1577. /* Read back and check it. */
  1578. ret = read_cr(nor);
  1579. if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
  1580. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  1581. return -EINVAL;
  1582. }
  1583. return 0;
  1584. }
  1585. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1586. /**
  1587. * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
  1588. * @nor: pointer to a 'struct spi_nor'
  1589. *
  1590. * Set the Quad Enable (QE) bit in the Configuration Register.
  1591. * This function should be used with QSPI memories not supporting the Read
  1592. * Configuration Register (35h) instruction.
  1593. *
  1594. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1595. * memories.
  1596. *
  1597. * Return: 0 on success, -errno otherwise.
  1598. */
  1599. static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
  1600. {
  1601. u8 sr_cr[2];
  1602. int ret;
  1603. /* Keep the current value of the Status Register. */
  1604. ret = read_sr(nor);
  1605. if (ret < 0) {
  1606. dev_dbg(nor->dev, "error while reading status register\n");
  1607. return -EINVAL;
  1608. }
  1609. sr_cr[0] = ret;
  1610. sr_cr[1] = CR_QUAD_EN_SPAN;
  1611. return write_sr_cr(nor, sr_cr);
  1612. }
  1613. #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
  1614. #endif /* CONFIG_SPI_FLASH_SPANSION */
  1615. static void
  1616. spi_nor_set_read_settings(struct spi_nor_read_command *read,
  1617. u8 num_mode_clocks,
  1618. u8 num_wait_states,
  1619. u8 opcode,
  1620. enum spi_nor_protocol proto)
  1621. {
  1622. read->num_mode_clocks = num_mode_clocks;
  1623. read->num_wait_states = num_wait_states;
  1624. read->opcode = opcode;
  1625. read->proto = proto;
  1626. }
  1627. static void
  1628. spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
  1629. u8 opcode,
  1630. enum spi_nor_protocol proto)
  1631. {
  1632. pp->opcode = opcode;
  1633. pp->proto = proto;
  1634. }
  1635. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1636. /*
  1637. * Serial Flash Discoverable Parameters (SFDP) parsing.
  1638. */
  1639. /**
  1640. * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
  1641. * @nor: pointer to a 'struct spi_nor'
  1642. * @addr: offset in the SFDP area to start reading data from
  1643. * @len: number of bytes to read
  1644. * @buf: buffer where the SFDP data are copied into (dma-safe memory)
  1645. *
  1646. * Whatever the actual numbers of bytes for address and dummy cycles are
  1647. * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
  1648. * followed by a 3-byte address and 8 dummy clock cycles.
  1649. *
  1650. * Return: 0 on success, -errno otherwise.
  1651. */
  1652. static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
  1653. size_t len, void *buf)
  1654. {
  1655. u8 addr_width, read_opcode, read_dummy;
  1656. int ret;
  1657. read_opcode = nor->read_opcode;
  1658. addr_width = nor->addr_width;
  1659. read_dummy = nor->read_dummy;
  1660. nor->read_opcode = SPINOR_OP_RDSFDP;
  1661. nor->addr_width = 3;
  1662. nor->read_dummy = 8;
  1663. while (len) {
  1664. ret = nor->read(nor, addr, len, (u8 *)buf);
  1665. if (!ret || ret > len) {
  1666. ret = -EIO;
  1667. goto read_err;
  1668. }
  1669. if (ret < 0)
  1670. goto read_err;
  1671. buf += ret;
  1672. addr += ret;
  1673. len -= ret;
  1674. }
  1675. ret = 0;
  1676. read_err:
  1677. nor->read_opcode = read_opcode;
  1678. nor->addr_width = addr_width;
  1679. nor->read_dummy = read_dummy;
  1680. return ret;
  1681. }
  1682. /* Fast Read settings. */
  1683. static void
  1684. spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
  1685. u16 half,
  1686. enum spi_nor_protocol proto)
  1687. {
  1688. read->num_mode_clocks = (half >> 5) & 0x07;
  1689. read->num_wait_states = (half >> 0) & 0x1f;
  1690. read->opcode = (half >> 8) & 0xff;
  1691. read->proto = proto;
  1692. }
  1693. struct sfdp_bfpt_read {
  1694. /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
  1695. u32 hwcaps;
  1696. /*
  1697. * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
  1698. * whether the Fast Read x-y-z command is supported.
  1699. */
  1700. u32 supported_dword;
  1701. u32 supported_bit;
  1702. /*
  1703. * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
  1704. * encodes the op code, the number of mode clocks and the number of wait
  1705. * states to be used by Fast Read x-y-z command.
  1706. */
  1707. u32 settings_dword;
  1708. u32 settings_shift;
  1709. /* The SPI protocol for this Fast Read x-y-z command. */
  1710. enum spi_nor_protocol proto;
  1711. };
  1712. static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
  1713. /* Fast Read 1-1-2 */
  1714. {
  1715. SNOR_HWCAPS_READ_1_1_2,
  1716. BFPT_DWORD(1), BIT(16), /* Supported bit */
  1717. BFPT_DWORD(4), 0, /* Settings */
  1718. SNOR_PROTO_1_1_2,
  1719. },
  1720. /* Fast Read 1-2-2 */
  1721. {
  1722. SNOR_HWCAPS_READ_1_2_2,
  1723. BFPT_DWORD(1), BIT(20), /* Supported bit */
  1724. BFPT_DWORD(4), 16, /* Settings */
  1725. SNOR_PROTO_1_2_2,
  1726. },
  1727. /* Fast Read 2-2-2 */
  1728. {
  1729. SNOR_HWCAPS_READ_2_2_2,
  1730. BFPT_DWORD(5), BIT(0), /* Supported bit */
  1731. BFPT_DWORD(6), 16, /* Settings */
  1732. SNOR_PROTO_2_2_2,
  1733. },
  1734. /* Fast Read 1-1-4 */
  1735. {
  1736. SNOR_HWCAPS_READ_1_1_4,
  1737. BFPT_DWORD(1), BIT(22), /* Supported bit */
  1738. BFPT_DWORD(3), 16, /* Settings */
  1739. SNOR_PROTO_1_1_4,
  1740. },
  1741. /* Fast Read 1-4-4 */
  1742. {
  1743. SNOR_HWCAPS_READ_1_4_4,
  1744. BFPT_DWORD(1), BIT(21), /* Supported bit */
  1745. BFPT_DWORD(3), 0, /* Settings */
  1746. SNOR_PROTO_1_4_4,
  1747. },
  1748. /* Fast Read 4-4-4 */
  1749. {
  1750. SNOR_HWCAPS_READ_4_4_4,
  1751. BFPT_DWORD(5), BIT(4), /* Supported bit */
  1752. BFPT_DWORD(7), 16, /* Settings */
  1753. SNOR_PROTO_4_4_4,
  1754. },
  1755. };
  1756. struct sfdp_bfpt_erase {
  1757. /*
  1758. * The half-word at offset <shift> in DWORD <dwoard> encodes the
  1759. * op code and erase sector size to be used by Sector Erase commands.
  1760. */
  1761. u32 dword;
  1762. u32 shift;
  1763. };
  1764. static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
  1765. /* Erase Type 1 in DWORD8 bits[15:0] */
  1766. {BFPT_DWORD(8), 0},
  1767. /* Erase Type 2 in DWORD8 bits[31:16] */
  1768. {BFPT_DWORD(8), 16},
  1769. /* Erase Type 3 in DWORD9 bits[15:0] */
  1770. {BFPT_DWORD(9), 0},
  1771. /* Erase Type 4 in DWORD9 bits[31:16] */
  1772. {BFPT_DWORD(9), 16},
  1773. };
  1774. static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
  1775. static int
  1776. spi_nor_post_bfpt_fixups(struct spi_nor *nor,
  1777. const struct sfdp_parameter_header *bfpt_header,
  1778. const struct sfdp_bfpt *bfpt,
  1779. struct spi_nor_flash_parameter *params)
  1780. {
  1781. if (nor->fixups && nor->fixups->post_bfpt)
  1782. return nor->fixups->post_bfpt(nor, bfpt_header, bfpt, params);
  1783. return 0;
  1784. }
  1785. /**
  1786. * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
  1787. * @nor: pointer to a 'struct spi_nor'
  1788. * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
  1789. * the Basic Flash Parameter Table length and version
  1790. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  1791. * filled
  1792. *
  1793. * The Basic Flash Parameter Table is the main and only mandatory table as
  1794. * defined by the SFDP (JESD216) specification.
  1795. * It provides us with the total size (memory density) of the data array and
  1796. * the number of address bytes for Fast Read, Page Program and Sector Erase
  1797. * commands.
  1798. * For Fast READ commands, it also gives the number of mode clock cycles and
  1799. * wait states (regrouped in the number of dummy clock cycles) for each
  1800. * supported instruction op code.
  1801. * For Page Program, the page size is now available since JESD216 rev A, however
  1802. * the supported instruction op codes are still not provided.
  1803. * For Sector Erase commands, this table stores the supported instruction op
  1804. * codes and the associated sector sizes.
  1805. * Finally, the Quad Enable Requirements (QER) are also available since JESD216
  1806. * rev A. The QER bits encode the manufacturer dependent procedure to be
  1807. * executed to set the Quad Enable (QE) bit in some internal register of the
  1808. * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
  1809. * sending any Quad SPI command to the memory. Actually, setting the QE bit
  1810. * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
  1811. * and IO3 hence enabling 4 (Quad) I/O lines.
  1812. *
  1813. * Return: 0 on success, -errno otherwise.
  1814. */
  1815. static int spi_nor_parse_bfpt(struct spi_nor *nor,
  1816. const struct sfdp_parameter_header *bfpt_header,
  1817. struct spi_nor_flash_parameter *params)
  1818. {
  1819. struct mtd_info *mtd = &nor->mtd;
  1820. struct sfdp_bfpt bfpt;
  1821. size_t len;
  1822. int i, cmd, err;
  1823. u32 addr;
  1824. u16 half;
  1825. /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
  1826. if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
  1827. return -EINVAL;
  1828. /* Read the Basic Flash Parameter Table. */
  1829. len = min_t(size_t, sizeof(bfpt),
  1830. bfpt_header->length * sizeof(u32));
  1831. addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
  1832. memset(&bfpt, 0, sizeof(bfpt));
  1833. err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
  1834. if (err < 0)
  1835. return err;
  1836. /* Fix endianness of the BFPT DWORDs. */
  1837. for (i = 0; i < BFPT_DWORD_MAX; i++)
  1838. bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
  1839. /* Number of address bytes. */
  1840. switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
  1841. case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
  1842. nor->addr_width = 3;
  1843. break;
  1844. case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
  1845. nor->addr_width = 4;
  1846. break;
  1847. default:
  1848. break;
  1849. }
  1850. /* Flash Memory Density (in bits). */
  1851. params->size = bfpt.dwords[BFPT_DWORD(2)];
  1852. if (params->size & BIT(31)) {
  1853. params->size &= ~BIT(31);
  1854. /*
  1855. * Prevent overflows on params->size. Anyway, a NOR of 2^64
  1856. * bits is unlikely to exist so this error probably means
  1857. * the BFPT we are reading is corrupted/wrong.
  1858. */
  1859. if (params->size > 63)
  1860. return -EINVAL;
  1861. params->size = 1ULL << params->size;
  1862. } else {
  1863. params->size++;
  1864. }
  1865. params->size >>= 3; /* Convert to bytes. */
  1866. /* Fast Read settings. */
  1867. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
  1868. const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
  1869. struct spi_nor_read_command *read;
  1870. if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
  1871. params->hwcaps.mask &= ~rd->hwcaps;
  1872. continue;
  1873. }
  1874. params->hwcaps.mask |= rd->hwcaps;
  1875. cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
  1876. read = &params->reads[cmd];
  1877. half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
  1878. spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
  1879. }
  1880. /* Sector Erase settings. */
  1881. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
  1882. const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
  1883. u32 erasesize;
  1884. u8 opcode;
  1885. half = bfpt.dwords[er->dword] >> er->shift;
  1886. erasesize = half & 0xff;
  1887. /* erasesize == 0 means this Erase Type is not supported. */
  1888. if (!erasesize)
  1889. continue;
  1890. erasesize = 1U << erasesize;
  1891. opcode = (half >> 8) & 0xff;
  1892. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  1893. if (erasesize == SZ_4K) {
  1894. nor->erase_opcode = opcode;
  1895. mtd->erasesize = erasesize;
  1896. break;
  1897. }
  1898. #endif
  1899. if (!mtd->erasesize || mtd->erasesize < erasesize) {
  1900. nor->erase_opcode = opcode;
  1901. mtd->erasesize = erasesize;
  1902. }
  1903. }
  1904. /* Stop here if not JESD216 rev A or later. */
  1905. if (bfpt_header->length == BFPT_DWORD_MAX_JESD216)
  1906. return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
  1907. params);
  1908. /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
  1909. params->page_size = bfpt.dwords[BFPT_DWORD(11)];
  1910. params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
  1911. params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
  1912. params->page_size = 1U << params->page_size;
  1913. /* Quad Enable Requirements. */
  1914. switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
  1915. case BFPT_DWORD15_QER_NONE:
  1916. params->quad_enable = NULL;
  1917. break;
  1918. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1919. case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
  1920. case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
  1921. params->quad_enable = spansion_no_read_cr_quad_enable;
  1922. break;
  1923. #endif
  1924. #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
  1925. case BFPT_DWORD15_QER_SR1_BIT6:
  1926. params->quad_enable = macronix_quad_enable;
  1927. break;
  1928. #endif
  1929. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1930. case BFPT_DWORD15_QER_SR2_BIT1:
  1931. params->quad_enable = spansion_read_cr_quad_enable;
  1932. break;
  1933. #endif
  1934. default:
  1935. dev_dbg(nor->dev, "BFPT QER reserved value used\n");
  1936. break;
  1937. }
  1938. /* Soft Reset support. */
  1939. if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SOFT_RST)
  1940. nor->flags |= SNOR_F_SOFT_RESET;
  1941. /* Stop here if JESD216 rev B. */
  1942. if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B)
  1943. return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
  1944. params);
  1945. /* 8D-8D-8D command extension. */
  1946. switch (bfpt.dwords[BFPT_DWORD(18)] & BFPT_DWORD18_CMD_EXT_MASK) {
  1947. case BFPT_DWORD18_CMD_EXT_REP:
  1948. nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
  1949. break;
  1950. case BFPT_DWORD18_CMD_EXT_INV:
  1951. nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
  1952. break;
  1953. case BFPT_DWORD18_CMD_EXT_RES:
  1954. return -EINVAL;
  1955. case BFPT_DWORD18_CMD_EXT_16B:
  1956. dev_err(nor->dev, "16-bit opcodes not supported\n");
  1957. return -ENOTSUPP;
  1958. }
  1959. return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
  1960. }
  1961. /**
  1962. * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
  1963. * SFDP table.
  1964. * @nor: pointer to a 'struct spi_nor'.
  1965. * @param_header: pointer to the SFDP parameter header.
  1966. *
  1967. * Return: 0 on success, -errno otherwise.
  1968. */
  1969. static int
  1970. spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
  1971. const struct sfdp_parameter_header *param_header)
  1972. {
  1973. size_t size;
  1974. u32 addr;
  1975. int ret;
  1976. size = param_header->length * sizeof(u32);
  1977. addr = SFDP_PARAM_HEADER_PTP(param_header);
  1978. nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
  1979. if (!nor->manufacturer_sfdp)
  1980. return -ENOMEM;
  1981. ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
  1982. return ret;
  1983. }
  1984. /**
  1985. * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
  1986. * @nor: pointer to a 'struct spi_nor'
  1987. * @profile1_header: pointer to the 'struct sfdp_parameter_header' describing
  1988. * the 4-Byte Address Instruction Table length and version.
  1989. * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
  1990. *
  1991. * Return: 0 on success, -errno otherwise.
  1992. */
  1993. static int spi_nor_parse_profile1(struct spi_nor *nor,
  1994. const struct sfdp_parameter_header *profile1_header,
  1995. struct spi_nor_flash_parameter *params)
  1996. {
  1997. u32 *table, opcode, addr;
  1998. size_t len;
  1999. int ret, i;
  2000. u8 dummy;
  2001. len = profile1_header->length * sizeof(*table);
  2002. table = kmalloc(len, GFP_KERNEL);
  2003. if (!table)
  2004. return -ENOMEM;
  2005. addr = SFDP_PARAM_HEADER_PTP(profile1_header);
  2006. ret = spi_nor_read_sfdp(nor, addr, len, table);
  2007. if (ret)
  2008. goto out;
  2009. /* Fix endianness of the table DWORDs. */
  2010. for (i = 0; i < profile1_header->length; i++)
  2011. table[i] = le32_to_cpu(table[i]);
  2012. /* Get 8D-8D-8D fast read opcode and dummy cycles. */
  2013. opcode = FIELD_GET(PROFILE1_DWORD1_RD_FAST_CMD, table[0]);
  2014. /*
  2015. * We don't know what speed the controller is running at. Find the
  2016. * dummy cycles for the fastest frequency the flash can run at to be
  2017. * sure we are never short of dummy cycles. A value of 0 means the
  2018. * frequency is not supported.
  2019. *
  2020. * Default to PROFILE1_DUMMY_DEFAULT if we don't find anything, and let
  2021. * flashes set the correct value if needed in their fixup hooks.
  2022. */
  2023. dummy = FIELD_GET(PROFILE1_DWORD4_DUMMY_200MHZ, table[3]);
  2024. if (!dummy)
  2025. dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_166MHZ, table[4]);
  2026. if (!dummy)
  2027. dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_133MHZ, table[4]);
  2028. if (!dummy)
  2029. dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_100MHZ, table[4]);
  2030. if (!dummy)
  2031. dummy = PROFILE1_DUMMY_DEFAULT;
  2032. /* Round up to an even value to avoid tripping controllers up. */
  2033. dummy = ROUND_UP_TO(dummy, 2);
  2034. /* Update the fast read settings. */
  2035. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
  2036. 0, dummy, opcode,
  2037. SNOR_PROTO_8_8_8_DTR);
  2038. /*
  2039. * Set the Read Status Register dummy cycles and dummy address bytes.
  2040. */
  2041. if (table[0] & PROFILE1_DWORD1_RDSR_DUMMY)
  2042. params->rdsr_dummy = 8;
  2043. else
  2044. params->rdsr_dummy = 4;
  2045. if (table[0] & PROFILE1_DWORD1_RDSR_ADDR_BYTES)
  2046. params->rdsr_addr_nbytes = 4;
  2047. else
  2048. params->rdsr_addr_nbytes = 0;
  2049. out:
  2050. kfree(table);
  2051. return ret;
  2052. }
  2053. /**
  2054. * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
  2055. * @nor: pointer to a 'struct spi_nor'
  2056. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  2057. * filled
  2058. *
  2059. * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
  2060. * specification. This is a standard which tends to supported by almost all
  2061. * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
  2062. * runtime the main parameters needed to perform basic SPI flash operations such
  2063. * as Fast Read, Page Program or Sector Erase commands.
  2064. *
  2065. * Return: 0 on success, -errno otherwise.
  2066. */
  2067. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  2068. struct spi_nor_flash_parameter *params)
  2069. {
  2070. const struct sfdp_parameter_header *param_header, *bfpt_header;
  2071. struct sfdp_parameter_header *param_headers = NULL;
  2072. struct sfdp_header header;
  2073. size_t psize;
  2074. int i, err;
  2075. /* Get the SFDP header. */
  2076. err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
  2077. if (err < 0)
  2078. return err;
  2079. /* Check the SFDP header version. */
  2080. if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
  2081. header.major != SFDP_JESD216_MAJOR)
  2082. return -EINVAL;
  2083. /*
  2084. * Verify that the first and only mandatory parameter header is a
  2085. * Basic Flash Parameter Table header as specified in JESD216.
  2086. */
  2087. bfpt_header = &header.bfpt_header;
  2088. if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
  2089. bfpt_header->major != SFDP_JESD216_MAJOR)
  2090. return -EINVAL;
  2091. /*
  2092. * Allocate memory then read all parameter headers with a single
  2093. * Read SFDP command. These parameter headers will actually be parsed
  2094. * twice: a first time to get the latest revision of the basic flash
  2095. * parameter table, then a second time to handle the supported optional
  2096. * tables.
  2097. * Hence we read the parameter headers once for all to reduce the
  2098. * processing time. Also we use kmalloc() instead of devm_kmalloc()
  2099. * because we don't need to keep these parameter headers: the allocated
  2100. * memory is always released with kfree() before exiting this function.
  2101. */
  2102. if (header.nph) {
  2103. psize = header.nph * sizeof(*param_headers);
  2104. param_headers = kmalloc(psize, GFP_KERNEL);
  2105. if (!param_headers)
  2106. return -ENOMEM;
  2107. err = spi_nor_read_sfdp(nor, sizeof(header),
  2108. psize, param_headers);
  2109. if (err < 0) {
  2110. dev_err(nor->dev,
  2111. "failed to read SFDP parameter headers\n");
  2112. goto exit;
  2113. }
  2114. }
  2115. /*
  2116. * Check other parameter headers to get the latest revision of
  2117. * the basic flash parameter table.
  2118. */
  2119. for (i = 0; i < header.nph; i++) {
  2120. param_header = &param_headers[i];
  2121. if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
  2122. param_header->major == SFDP_JESD216_MAJOR &&
  2123. (param_header->minor > bfpt_header->minor ||
  2124. (param_header->minor == bfpt_header->minor &&
  2125. param_header->length > bfpt_header->length)))
  2126. bfpt_header = param_header;
  2127. }
  2128. err = spi_nor_parse_bfpt(nor, bfpt_header, params);
  2129. if (err)
  2130. goto exit;
  2131. /* Parse other parameter headers. */
  2132. for (i = 0; i < header.nph; i++) {
  2133. param_header = &param_headers[i];
  2134. switch (SFDP_PARAM_HEADER_ID(param_header)) {
  2135. case SFDP_SECTOR_MAP_ID:
  2136. dev_info(nor->dev,
  2137. "non-uniform erase sector maps are not supported yet.\n");
  2138. break;
  2139. case SFDP_SST_ID:
  2140. err = spi_nor_parse_microchip_sfdp(nor, param_header);
  2141. break;
  2142. case SFDP_PROFILE1_ID:
  2143. err = spi_nor_parse_profile1(nor, param_header, params);
  2144. break;
  2145. default:
  2146. break;
  2147. }
  2148. if (err) {
  2149. dev_warn(nor->dev,
  2150. "Failed to parse optional parameter table: %04x\n",
  2151. SFDP_PARAM_HEADER_ID(param_header));
  2152. /*
  2153. * Let's not drop all information we extracted so far
  2154. * if optional table parsers fail. In case of failing,
  2155. * each optional parser is responsible to roll back to
  2156. * the previously known spi_nor data.
  2157. */
  2158. err = 0;
  2159. }
  2160. }
  2161. exit:
  2162. kfree(param_headers);
  2163. return err;
  2164. }
  2165. #else
  2166. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  2167. struct spi_nor_flash_parameter *params)
  2168. {
  2169. return -EINVAL;
  2170. }
  2171. #endif /* SPI_FLASH_SFDP_SUPPORT */
  2172. /**
  2173. * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
  2174. * after SFDP has been parsed (is also called for SPI NORs that do not
  2175. * support RDSFDP).
  2176. * @nor: pointer to a 'struct spi_nor'
  2177. *
  2178. * Typically used to tweak various parameters that could not be extracted by
  2179. * other means (i.e. when information provided by the SFDP/flash_info tables
  2180. * are incomplete or wrong).
  2181. */
  2182. static void spi_nor_post_sfdp_fixups(struct spi_nor *nor,
  2183. struct spi_nor_flash_parameter *params)
  2184. {
  2185. if (nor->fixups && nor->fixups->post_sfdp)
  2186. nor->fixups->post_sfdp(nor, params);
  2187. }
  2188. static void spi_nor_default_init_fixups(struct spi_nor *nor)
  2189. {
  2190. if (nor->fixups && nor->fixups->default_init)
  2191. nor->fixups->default_init(nor);
  2192. }
  2193. static int spi_nor_init_params(struct spi_nor *nor,
  2194. const struct flash_info *info,
  2195. struct spi_nor_flash_parameter *params)
  2196. {
  2197. /* Set legacy flash parameters as default. */
  2198. memset(params, 0, sizeof(*params));
  2199. /* Set SPI NOR sizes. */
  2200. params->size = info->sector_size * info->n_sectors;
  2201. params->page_size = info->page_size;
  2202. if (!(info->flags & SPI_NOR_NO_FR)) {
  2203. /* Default to Fast Read for DT and non-DT platform devices. */
  2204. params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
  2205. /* Mask out Fast Read if not requested at DT instantiation. */
  2206. #if CONFIG_IS_ENABLED(DM_SPI)
  2207. if (!ofnode_read_bool(dev_ofnode(nor->spi->dev),
  2208. "m25p,fast-read"))
  2209. params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  2210. #endif
  2211. }
  2212. /* (Fast) Read settings. */
  2213. params->hwcaps.mask |= SNOR_HWCAPS_READ;
  2214. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
  2215. 0, 0, SPINOR_OP_READ,
  2216. SNOR_PROTO_1_1_1);
  2217. if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
  2218. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
  2219. 0, 8, SPINOR_OP_READ_FAST,
  2220. SNOR_PROTO_1_1_1);
  2221. if (info->flags & SPI_NOR_DUAL_READ) {
  2222. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
  2223. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
  2224. 0, 8, SPINOR_OP_READ_1_1_2,
  2225. SNOR_PROTO_1_1_2);
  2226. }
  2227. if (info->flags & SPI_NOR_QUAD_READ) {
  2228. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  2229. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
  2230. 0, 8, SPINOR_OP_READ_1_1_4,
  2231. SNOR_PROTO_1_1_4);
  2232. }
  2233. if (info->flags & SPI_NOR_OCTAL_READ) {
  2234. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
  2235. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
  2236. 0, 8, SPINOR_OP_READ_1_1_8,
  2237. SNOR_PROTO_1_1_8);
  2238. }
  2239. if (info->flags & SPI_NOR_OCTAL_DTR_READ) {
  2240. params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
  2241. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
  2242. 0, 20, SPINOR_OP_READ_FAST,
  2243. SNOR_PROTO_8_8_8_DTR);
  2244. }
  2245. /* Page Program settings. */
  2246. params->hwcaps.mask |= SNOR_HWCAPS_PP;
  2247. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
  2248. SPINOR_OP_PP, SNOR_PROTO_1_1_1);
  2249. /*
  2250. * Since xSPI Page Program opcode is backward compatible with
  2251. * Legacy SPI, use Legacy SPI opcode there as well.
  2252. */
  2253. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
  2254. SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
  2255. if (info->flags & SPI_NOR_QUAD_READ) {
  2256. params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
  2257. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
  2258. SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
  2259. }
  2260. /* Select the procedure to set the Quad Enable bit. */
  2261. if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
  2262. SNOR_HWCAPS_PP_QUAD)) {
  2263. switch (JEDEC_MFR(info)) {
  2264. #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
  2265. case SNOR_MFR_MACRONIX:
  2266. case SNOR_MFR_ISSI:
  2267. params->quad_enable = macronix_quad_enable;
  2268. break;
  2269. #endif
  2270. case SNOR_MFR_ST:
  2271. case SNOR_MFR_MICRON:
  2272. break;
  2273. default:
  2274. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  2275. /* Kept only for backward compatibility purpose. */
  2276. params->quad_enable = spansion_read_cr_quad_enable;
  2277. #endif
  2278. break;
  2279. }
  2280. }
  2281. spi_nor_default_init_fixups(nor);
  2282. /* Override the parameters with data read from SFDP tables. */
  2283. nor->addr_width = 0;
  2284. nor->mtd.erasesize = 0;
  2285. if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  2286. SPI_NOR_OCTAL_DTR_READ)) &&
  2287. !(info->flags & SPI_NOR_SKIP_SFDP)) {
  2288. struct spi_nor_flash_parameter sfdp_params;
  2289. memcpy(&sfdp_params, params, sizeof(sfdp_params));
  2290. if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
  2291. nor->addr_width = 0;
  2292. nor->mtd.erasesize = 0;
  2293. } else {
  2294. memcpy(params, &sfdp_params, sizeof(*params));
  2295. }
  2296. }
  2297. spi_nor_post_sfdp_fixups(nor, params);
  2298. return 0;
  2299. }
  2300. static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
  2301. {
  2302. size_t i;
  2303. for (i = 0; i < size; i++)
  2304. if (table[i][0] == (int)hwcaps)
  2305. return table[i][1];
  2306. return -EINVAL;
  2307. }
  2308. static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
  2309. {
  2310. static const int hwcaps_read2cmd[][2] = {
  2311. { SNOR_HWCAPS_READ, SNOR_CMD_READ },
  2312. { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
  2313. { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
  2314. { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
  2315. { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
  2316. { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
  2317. { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
  2318. { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
  2319. { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
  2320. { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
  2321. { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
  2322. { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
  2323. { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
  2324. { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
  2325. { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
  2326. { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },
  2327. };
  2328. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
  2329. ARRAY_SIZE(hwcaps_read2cmd));
  2330. }
  2331. static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
  2332. {
  2333. static const int hwcaps_pp2cmd[][2] = {
  2334. { SNOR_HWCAPS_PP, SNOR_CMD_PP },
  2335. { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
  2336. { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
  2337. { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
  2338. { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
  2339. { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
  2340. { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
  2341. { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },
  2342. };
  2343. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
  2344. ARRAY_SIZE(hwcaps_pp2cmd));
  2345. }
  2346. #ifdef CONFIG_SPI_FLASH_SMART_HWCAPS
  2347. /**
  2348. * spi_nor_check_op - check if the operation is supported by controller
  2349. * @nor: pointer to a 'struct spi_nor'
  2350. * @op: pointer to op template to be checked
  2351. *
  2352. * Returns 0 if operation is supported, -ENOTSUPP otherwise.
  2353. */
  2354. static int spi_nor_check_op(struct spi_nor *nor,
  2355. struct spi_mem_op *op)
  2356. {
  2357. /*
  2358. * First test with 4 address bytes. The opcode itself might be a 3B
  2359. * addressing opcode but we don't care, because SPI controller
  2360. * implementation should not check the opcode, but just the sequence.
  2361. */
  2362. op->addr.nbytes = 4;
  2363. if (!spi_mem_supports_op(nor->spi, op)) {
  2364. if (nor->mtd.size > SZ_16M)
  2365. return -ENOTSUPP;
  2366. /* If flash size <= 16MB, 3 address bytes are sufficient */
  2367. op->addr.nbytes = 3;
  2368. if (!spi_mem_supports_op(nor->spi, op))
  2369. return -ENOTSUPP;
  2370. }
  2371. return 0;
  2372. }
  2373. /**
  2374. * spi_nor_check_readop - check if the read op is supported by controller
  2375. * @nor: pointer to a 'struct spi_nor'
  2376. * @read: pointer to op template to be checked
  2377. *
  2378. * Returns 0 if operation is supported, -ENOTSUPP otherwise.
  2379. */
  2380. static int spi_nor_check_readop(struct spi_nor *nor,
  2381. const struct spi_nor_read_command *read)
  2382. {
  2383. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0),
  2384. SPI_MEM_OP_ADDR(3, 0, 0),
  2385. SPI_MEM_OP_DUMMY(1, 0),
  2386. SPI_MEM_OP_DATA_IN(2, NULL, 0));
  2387. spi_nor_setup_op(nor, &op, read->proto);
  2388. op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
  2389. op.dummy.buswidth / 8;
  2390. if (spi_nor_protocol_is_dtr(nor->read_proto))
  2391. op.dummy.nbytes *= 2;
  2392. return spi_nor_check_op(nor, &op);
  2393. }
  2394. /**
  2395. * spi_nor_check_pp - check if the page program op is supported by controller
  2396. * @nor: pointer to a 'struct spi_nor'
  2397. * @pp: pointer to op template to be checked
  2398. *
  2399. * Returns 0 if operation is supported, -ENOTSUPP otherwise.
  2400. */
  2401. static int spi_nor_check_pp(struct spi_nor *nor,
  2402. const struct spi_nor_pp_command *pp)
  2403. {
  2404. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0),
  2405. SPI_MEM_OP_ADDR(3, 0, 0),
  2406. SPI_MEM_OP_NO_DUMMY,
  2407. SPI_MEM_OP_DATA_OUT(2, NULL, 0));
  2408. spi_nor_setup_op(nor, &op, pp->proto);
  2409. return spi_nor_check_op(nor, &op);
  2410. }
  2411. /**
  2412. * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
  2413. * controller capabilities
  2414. * @nor: pointer to a 'struct spi_nor'
  2415. * @params: pointer to the 'struct spi_nor_flash_parameter'
  2416. * representing SPI NOR flash capabilities
  2417. * @hwcaps: pointer to resulting capabilities after adjusting
  2418. * according to controller and flash's capability
  2419. *
  2420. * Discard caps based on what the SPI controller actually supports (using
  2421. * spi_mem_supports_op()).
  2422. */
  2423. static void
  2424. spi_nor_adjust_hwcaps(struct spi_nor *nor,
  2425. const struct spi_nor_flash_parameter *params,
  2426. u32 *hwcaps)
  2427. {
  2428. unsigned int cap;
  2429. /*
  2430. * Start by assuming the controller supports every capability.
  2431. * We will mask them after checking what's really supported
  2432. * using spi_mem_supports_op().
  2433. */
  2434. *hwcaps = SNOR_HWCAPS_ALL & params->hwcaps.mask;
  2435. /* X-X-X modes are not supported yet, mask them all. */
  2436. *hwcaps &= ~SNOR_HWCAPS_X_X_X;
  2437. /*
  2438. * If the reset line is broken, we do not want to enter a stateful
  2439. * mode.
  2440. */
  2441. if (nor->flags & SNOR_F_BROKEN_RESET)
  2442. *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
  2443. for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
  2444. int rdidx, ppidx;
  2445. if (!(*hwcaps & BIT(cap)))
  2446. continue;
  2447. rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
  2448. if (rdidx >= 0 &&
  2449. spi_nor_check_readop(nor, &params->reads[rdidx]))
  2450. *hwcaps &= ~BIT(cap);
  2451. ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
  2452. if (ppidx < 0)
  2453. continue;
  2454. if (spi_nor_check_pp(nor, &params->page_programs[ppidx]))
  2455. *hwcaps &= ~BIT(cap);
  2456. }
  2457. }
  2458. #else
  2459. /**
  2460. * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
  2461. * controller capabilities
  2462. * @nor: pointer to a 'struct spi_nor'
  2463. * @params: pointer to the 'struct spi_nor_flash_parameter'
  2464. * representing SPI NOR flash capabilities
  2465. * @hwcaps: pointer to resulting capabilities after adjusting
  2466. * according to controller and flash's capability
  2467. *
  2468. * Select caps based on what the SPI controller and SPI flash both support.
  2469. */
  2470. static void
  2471. spi_nor_adjust_hwcaps(struct spi_nor *nor,
  2472. const struct spi_nor_flash_parameter *params,
  2473. u32 *hwcaps)
  2474. {
  2475. struct spi_slave *spi = nor->spi;
  2476. u32 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
  2477. SNOR_HWCAPS_READ_4_4_4 |
  2478. SNOR_HWCAPS_READ_8_8_8 |
  2479. SNOR_HWCAPS_PP_4_4_4 |
  2480. SNOR_HWCAPS_PP_8_8_8);
  2481. u32 spi_hwcaps = (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |
  2482. SNOR_HWCAPS_PP);
  2483. /* Get the hardware capabilities the SPI controller supports. */
  2484. if (spi->mode & SPI_RX_OCTAL) {
  2485. spi_hwcaps |= SNOR_HWCAPS_READ_1_1_8;
  2486. if (spi->mode & SPI_TX_OCTAL)
  2487. spi_hwcaps |= (SNOR_HWCAPS_READ_1_8_8 |
  2488. SNOR_HWCAPS_PP_1_1_8 |
  2489. SNOR_HWCAPS_PP_1_8_8);
  2490. } else if (spi->mode & SPI_RX_QUAD) {
  2491. spi_hwcaps |= SNOR_HWCAPS_READ_1_1_4;
  2492. if (spi->mode & SPI_TX_QUAD)
  2493. spi_hwcaps |= (SNOR_HWCAPS_READ_1_4_4 |
  2494. SNOR_HWCAPS_PP_1_1_4 |
  2495. SNOR_HWCAPS_PP_1_4_4);
  2496. } else if (spi->mode & SPI_RX_DUAL) {
  2497. spi_hwcaps |= SNOR_HWCAPS_READ_1_1_2;
  2498. if (spi->mode & SPI_TX_DUAL)
  2499. spi_hwcaps |= SNOR_HWCAPS_READ_1_2_2;
  2500. }
  2501. /*
  2502. * Keep only the hardware capabilities supported by both the SPI
  2503. * controller and the SPI flash memory.
  2504. */
  2505. *hwcaps = spi_hwcaps & params->hwcaps.mask;
  2506. if (*hwcaps & ignored_mask) {
  2507. dev_dbg(nor->dev,
  2508. "SPI n-n-n protocols are not supported yet.\n");
  2509. *hwcaps &= ~ignored_mask;
  2510. }
  2511. }
  2512. #endif /* CONFIG_SPI_FLASH_SMART_HWCAPS */
  2513. static int spi_nor_select_read(struct spi_nor *nor,
  2514. const struct spi_nor_flash_parameter *params,
  2515. u32 shared_hwcaps)
  2516. {
  2517. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
  2518. const struct spi_nor_read_command *read;
  2519. if (best_match < 0)
  2520. return -EINVAL;
  2521. cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
  2522. if (cmd < 0)
  2523. return -EINVAL;
  2524. read = &params->reads[cmd];
  2525. nor->read_opcode = read->opcode;
  2526. nor->read_proto = read->proto;
  2527. /*
  2528. * In the spi-nor framework, we don't need to make the difference
  2529. * between mode clock cycles and wait state clock cycles.
  2530. * Indeed, the value of the mode clock cycles is used by a QSPI
  2531. * flash memory to know whether it should enter or leave its 0-4-4
  2532. * (Continuous Read / XIP) mode.
  2533. * eXecution In Place is out of the scope of the mtd sub-system.
  2534. * Hence we choose to merge both mode and wait state clock cycles
  2535. * into the so called dummy clock cycles.
  2536. */
  2537. nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
  2538. return 0;
  2539. }
  2540. static int spi_nor_select_pp(struct spi_nor *nor,
  2541. const struct spi_nor_flash_parameter *params,
  2542. u32 shared_hwcaps)
  2543. {
  2544. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
  2545. const struct spi_nor_pp_command *pp;
  2546. if (best_match < 0)
  2547. return -EINVAL;
  2548. cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
  2549. if (cmd < 0)
  2550. return -EINVAL;
  2551. pp = &params->page_programs[cmd];
  2552. nor->program_opcode = pp->opcode;
  2553. nor->write_proto = pp->proto;
  2554. return 0;
  2555. }
  2556. static int spi_nor_select_erase(struct spi_nor *nor,
  2557. const struct flash_info *info)
  2558. {
  2559. struct mtd_info *mtd = &nor->mtd;
  2560. /* Do nothing if already configured from SFDP. */
  2561. if (mtd->erasesize)
  2562. return 0;
  2563. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  2564. /* prefer "small sector" erase if possible */
  2565. if (info->flags & SECT_4K) {
  2566. nor->erase_opcode = SPINOR_OP_BE_4K;
  2567. mtd->erasesize = 4096;
  2568. } else if (info->flags & SECT_4K_PMC) {
  2569. nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
  2570. mtd->erasesize = 4096;
  2571. } else
  2572. #endif
  2573. {
  2574. nor->erase_opcode = SPINOR_OP_SE;
  2575. mtd->erasesize = info->sector_size;
  2576. }
  2577. return 0;
  2578. }
  2579. static int spi_nor_default_setup(struct spi_nor *nor,
  2580. const struct flash_info *info,
  2581. const struct spi_nor_flash_parameter *params)
  2582. {
  2583. u32 shared_mask;
  2584. bool enable_quad_io;
  2585. int err;
  2586. spi_nor_adjust_hwcaps(nor, params, &shared_mask);
  2587. /* Select the (Fast) Read command. */
  2588. err = spi_nor_select_read(nor, params, shared_mask);
  2589. if (err) {
  2590. dev_dbg(nor->dev,
  2591. "can't select read settings supported by both the SPI controller and memory.\n");
  2592. return err;
  2593. }
  2594. /* Select the Page Program command. */
  2595. err = spi_nor_select_pp(nor, params, shared_mask);
  2596. if (err) {
  2597. dev_dbg(nor->dev,
  2598. "can't select write settings supported by both the SPI controller and memory.\n");
  2599. return err;
  2600. }
  2601. /* Select the Sector Erase command. */
  2602. err = spi_nor_select_erase(nor, info);
  2603. if (err) {
  2604. dev_dbg(nor->dev,
  2605. "can't select erase settings supported by both the SPI controller and memory.\n");
  2606. return err;
  2607. }
  2608. /* Enable Quad I/O if needed. */
  2609. enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
  2610. spi_nor_get_protocol_width(nor->write_proto) == 4);
  2611. if (enable_quad_io && params->quad_enable)
  2612. nor->quad_enable = params->quad_enable;
  2613. else
  2614. nor->quad_enable = NULL;
  2615. return 0;
  2616. }
  2617. static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
  2618. const struct spi_nor_flash_parameter *params)
  2619. {
  2620. if (!nor->setup)
  2621. return 0;
  2622. return nor->setup(nor, info, params);
  2623. }
  2624. #ifdef CONFIG_SPI_FLASH_SPANSION
  2625. static int s25hx_t_mdp_ready(struct spi_nor *nor)
  2626. {
  2627. u32 addr;
  2628. int ret;
  2629. for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
  2630. ret = spansion_sr_ready(nor, addr, 0);
  2631. if (!ret)
  2632. return ret;
  2633. }
  2634. return 1;
  2635. }
  2636. static int s25hx_t_quad_enable(struct spi_nor *nor)
  2637. {
  2638. u32 addr;
  2639. int ret;
  2640. for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
  2641. ret = spansion_quad_enable_volatile(nor, addr, 0);
  2642. if (ret)
  2643. return ret;
  2644. }
  2645. return 0;
  2646. }
  2647. static int s25hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
  2648. {
  2649. /* Support 32 x 4KB sectors at bottom */
  2650. return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0,
  2651. SZ_128K);
  2652. }
  2653. static int s25hx_t_setup(struct spi_nor *nor, const struct flash_info *info,
  2654. const struct spi_nor_flash_parameter *params)
  2655. {
  2656. int ret;
  2657. u8 cfr3v;
  2658. #ifdef CONFIG_SPI_FLASH_BAR
  2659. return -ENOTSUPP; /* Bank Address Register is not supported */
  2660. #endif
  2661. /*
  2662. * Read CFR3V to check if uniform sector is selected. If not, assign an
  2663. * erase hook that supports non-uniform erase.
  2664. */
  2665. ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cfr3v);
  2666. if (ret)
  2667. return ret;
  2668. if (!(cfr3v & CFR3V_UNHYSA))
  2669. nor->erase = s25hx_t_erase_non_uniform;
  2670. /*
  2671. * For the multi-die package parts, the ready() hook is needed to check
  2672. * all dies' status via read any register.
  2673. */
  2674. if (nor->mtd.size > SZ_128M)
  2675. nor->ready = s25hx_t_mdp_ready;
  2676. return spi_nor_default_setup(nor, info, params);
  2677. }
  2678. static void s25hx_t_default_init(struct spi_nor *nor)
  2679. {
  2680. nor->setup = s25hx_t_setup;
  2681. }
  2682. static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
  2683. const struct sfdp_parameter_header *header,
  2684. const struct sfdp_bfpt *bfpt,
  2685. struct spi_nor_flash_parameter *params)
  2686. {
  2687. int ret;
  2688. u32 addr;
  2689. u8 cfr3v;
  2690. /* erase size in case it is set to 4K from BFPT */
  2691. nor->erase_opcode = SPINOR_OP_SE_4B;
  2692. nor->mtd.erasesize = nor->info->sector_size;
  2693. ret = set_4byte(nor, nor->info, 1);
  2694. if (ret)
  2695. return ret;
  2696. nor->addr_width = 4;
  2697. /*
  2698. * The page_size is set to 512B from BFPT, but it actually depends on
  2699. * the configuration register. Look up the CFR3V and determine the
  2700. * page_size. For multi-die package parts, use 512B only when the all
  2701. * dies are configured to 512B buffer.
  2702. */
  2703. for (addr = 0; addr < params->size; addr += SZ_128M) {
  2704. ret = spansion_read_any_reg(nor, addr + SPINOR_REG_ADDR_CFR3V,
  2705. 0, &cfr3v);
  2706. if (ret)
  2707. return ret;
  2708. if (!(cfr3v & CFR3V_PGMBUF)) {
  2709. params->page_size = 256;
  2710. return 0;
  2711. }
  2712. }
  2713. params->page_size = 512;
  2714. return 0;
  2715. }
  2716. static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor,
  2717. struct spi_nor_flash_parameter *params)
  2718. {
  2719. /* READ_FAST_4B (0Ch) requires mode cycles*/
  2720. params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
  2721. /* PP_1_1_4 is not supported */
  2722. params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
  2723. /* Use volatile register to enable quad */
  2724. params->quad_enable = s25hx_t_quad_enable;
  2725. }
  2726. static struct spi_nor_fixups s25hx_t_fixups = {
  2727. .default_init = s25hx_t_default_init,
  2728. .post_bfpt = s25hx_t_post_bfpt_fixup,
  2729. .post_sfdp = s25hx_t_post_sfdp_fixup,
  2730. };
  2731. #endif
  2732. #ifdef CONFIG_SPI_FLASH_S28HS512T
  2733. /**
  2734. * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
  2735. * @nor: pointer to a 'struct spi_nor'
  2736. *
  2737. * This also sets the memory access latency cycles to 24 to allow the flash to
  2738. * run at up to 200MHz.
  2739. *
  2740. * Return: 0 on success, -errno otherwise.
  2741. */
  2742. static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
  2743. {
  2744. struct spi_mem_op op;
  2745. u8 buf;
  2746. u8 addr_width = 3;
  2747. int ret;
  2748. /* Use 24 dummy cycles for memory array reads. */
  2749. ret = write_enable(nor);
  2750. if (ret)
  2751. return ret;
  2752. buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
  2753. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
  2754. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1),
  2755. SPI_MEM_OP_NO_DUMMY,
  2756. SPI_MEM_OP_DATA_OUT(1, &buf, 1));
  2757. ret = spi_mem_exec_op(nor->spi, &op);
  2758. if (ret) {
  2759. dev_warn(nor->dev,
  2760. "failed to set default memory latency value: %d\n",
  2761. ret);
  2762. return ret;
  2763. }
  2764. ret = spi_nor_wait_till_ready(nor);
  2765. if (ret)
  2766. return ret;
  2767. nor->read_dummy = 24;
  2768. /* Set the octal and DTR enable bits. */
  2769. ret = write_enable(nor);
  2770. if (ret)
  2771. return ret;
  2772. buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
  2773. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
  2774. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1),
  2775. SPI_MEM_OP_NO_DUMMY,
  2776. SPI_MEM_OP_DATA_OUT(1, &buf, 1));
  2777. ret = spi_mem_exec_op(nor->spi, &op);
  2778. if (ret) {
  2779. dev_warn(nor->dev, "Failed to enable octal DTR mode\n");
  2780. return ret;
  2781. }
  2782. return 0;
  2783. }
  2784. static int s28hs512t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
  2785. {
  2786. /* Factory default configuration: 32 x 4 KiB sectors at bottom. */
  2787. return spansion_erase_non_uniform(nor, addr, SPINOR_OP_S28_SE_4K,
  2788. 0, SZ_128K);
  2789. }
  2790. static int s28hs512t_setup(struct spi_nor *nor, const struct flash_info *info,
  2791. const struct spi_nor_flash_parameter *params)
  2792. {
  2793. struct spi_mem_op op;
  2794. u8 buf;
  2795. u8 addr_width = 3;
  2796. int ret;
  2797. ret = spi_nor_wait_till_ready(nor);
  2798. if (ret)
  2799. return ret;
  2800. /*
  2801. * Check CFR3V to check if non-uniform sector mode is selected. If it
  2802. * is, set the erase hook to the non-uniform erase procedure.
  2803. */
  2804. op = (struct spi_mem_op)
  2805. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
  2806. SPI_MEM_OP_ADDR(addr_width,
  2807. SPINOR_REG_CYPRESS_CFR3V, 1),
  2808. SPI_MEM_OP_NO_DUMMY,
  2809. SPI_MEM_OP_DATA_IN(1, &buf, 1));
  2810. ret = spi_mem_exec_op(nor->spi, &op);
  2811. if (ret)
  2812. return ret;
  2813. if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT))
  2814. nor->erase = s28hs512t_erase_non_uniform;
  2815. return spi_nor_default_setup(nor, info, params);
  2816. }
  2817. static void s28hs512t_default_init(struct spi_nor *nor)
  2818. {
  2819. nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
  2820. nor->setup = s28hs512t_setup;
  2821. }
  2822. static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor,
  2823. struct spi_nor_flash_parameter *params)
  2824. {
  2825. /*
  2826. * On older versions of the flash the xSPI Profile 1.0 table has the
  2827. * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
  2828. */
  2829. if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
  2830. params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
  2831. SPINOR_OP_CYPRESS_RD_FAST;
  2832. params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
  2833. /* This flash is also missing the 4-byte Page Program opcode bit. */
  2834. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
  2835. SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
  2836. /*
  2837. * Since xSPI Page Program opcode is backward compatible with
  2838. * Legacy SPI, use Legacy SPI opcode there as well.
  2839. */
  2840. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
  2841. SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
  2842. /*
  2843. * The xSPI Profile 1.0 table advertises the number of additional
  2844. * address bytes needed for Read Status Register command as 0 but the
  2845. * actual value for that is 4.
  2846. */
  2847. params->rdsr_addr_nbytes = 4;
  2848. }
  2849. static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
  2850. const struct sfdp_parameter_header *bfpt_header,
  2851. const struct sfdp_bfpt *bfpt,
  2852. struct spi_nor_flash_parameter *params)
  2853. {
  2854. struct spi_mem_op op;
  2855. u8 buf;
  2856. u8 addr_width = 3;
  2857. int ret;
  2858. /*
  2859. * The BFPT table advertises a 512B page size but the page size is
  2860. * actually configurable (with the default being 256B). Read from
  2861. * CFR3V[4] and set the correct size.
  2862. */
  2863. op = (struct spi_mem_op)
  2864. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
  2865. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR3V, 1),
  2866. SPI_MEM_OP_NO_DUMMY,
  2867. SPI_MEM_OP_DATA_IN(1, &buf, 1));
  2868. ret = spi_mem_exec_op(nor->spi, &op);
  2869. if (ret)
  2870. return ret;
  2871. if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
  2872. params->page_size = 512;
  2873. else
  2874. params->page_size = 256;
  2875. /*
  2876. * The BFPT advertises that it supports 4k erases, and the datasheet
  2877. * says the same. But 4k erases did not work when testing. So, use 256k
  2878. * erases for now.
  2879. */
  2880. nor->erase_opcode = SPINOR_OP_SE_4B;
  2881. nor->mtd.erasesize = 0x40000;
  2882. return 0;
  2883. }
  2884. static struct spi_nor_fixups s28hs512t_fixups = {
  2885. .default_init = s28hs512t_default_init,
  2886. .post_sfdp = s28hs512t_post_sfdp_fixup,
  2887. .post_bfpt = s28hs512t_post_bfpt_fixup,
  2888. };
  2889. #endif /* CONFIG_SPI_FLASH_S28HS512T */
  2890. #ifdef CONFIG_SPI_FLASH_MT35XU
  2891. static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
  2892. {
  2893. struct spi_mem_op op;
  2894. u8 buf;
  2895. u8 addr_width = 3;
  2896. int ret;
  2897. /* Set dummy cycles for Fast Read to the default of 20. */
  2898. ret = write_enable(nor);
  2899. if (ret)
  2900. return ret;
  2901. buf = 20;
  2902. op = (struct spi_mem_op)
  2903. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
  2904. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR1V, 1),
  2905. SPI_MEM_OP_NO_DUMMY,
  2906. SPI_MEM_OP_DATA_OUT(1, &buf, 1));
  2907. ret = spi_mem_exec_op(nor->spi, &op);
  2908. if (ret)
  2909. return ret;
  2910. ret = spi_nor_wait_till_ready(nor);
  2911. if (ret)
  2912. return ret;
  2913. nor->read_dummy = 20;
  2914. ret = write_enable(nor);
  2915. if (ret)
  2916. return ret;
  2917. buf = SPINOR_MT_OCT_DTR;
  2918. op = (struct spi_mem_op)
  2919. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
  2920. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR0V, 1),
  2921. SPI_MEM_OP_NO_DUMMY,
  2922. SPI_MEM_OP_DATA_OUT(1, &buf, 1));
  2923. ret = spi_mem_exec_op(nor->spi, &op);
  2924. if (ret) {
  2925. dev_err(nor->dev, "Failed to enable octal DTR mode\n");
  2926. return ret;
  2927. }
  2928. return 0;
  2929. }
  2930. static void mt35xu512aba_default_init(struct spi_nor *nor)
  2931. {
  2932. nor->octal_dtr_enable = spi_nor_micron_octal_dtr_enable;
  2933. }
  2934. static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor,
  2935. struct spi_nor_flash_parameter *params)
  2936. {
  2937. /* Set the Fast Read settings. */
  2938. params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
  2939. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
  2940. 0, 20, SPINOR_OP_MT_DTR_RD,
  2941. SNOR_PROTO_8_8_8_DTR);
  2942. params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
  2943. nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
  2944. params->rdsr_dummy = 8;
  2945. params->rdsr_addr_nbytes = 0;
  2946. /*
  2947. * The BFPT quad enable field is set to a reserved value so the quad
  2948. * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
  2949. * disable it.
  2950. */
  2951. params->quad_enable = NULL;
  2952. }
  2953. static struct spi_nor_fixups mt35xu512aba_fixups = {
  2954. .default_init = mt35xu512aba_default_init,
  2955. .post_sfdp = mt35xu512aba_post_sfdp_fixup,
  2956. };
  2957. #endif /* CONFIG_SPI_FLASH_MT35XU */
  2958. /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
  2959. * @nor: pointer to a 'struct spi_nor'
  2960. *
  2961. * Return: 0 on success, -errno otherwise.
  2962. */
  2963. static int spi_nor_octal_dtr_enable(struct spi_nor *nor)
  2964. {
  2965. int ret;
  2966. if (!nor->octal_dtr_enable)
  2967. return 0;
  2968. if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
  2969. nor->write_proto == SNOR_PROTO_8_8_8_DTR))
  2970. return 0;
  2971. ret = nor->octal_dtr_enable(nor);
  2972. if (ret)
  2973. return ret;
  2974. nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
  2975. return 0;
  2976. }
  2977. static int spi_nor_init(struct spi_nor *nor)
  2978. {
  2979. int err;
  2980. err = spi_nor_octal_dtr_enable(nor);
  2981. if (err) {
  2982. dev_dbg(nor->dev, "Octal DTR mode not supported\n");
  2983. return err;
  2984. }
  2985. /*
  2986. * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
  2987. * with the software protection bits set
  2988. */
  2989. if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) &&
  2990. (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
  2991. JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
  2992. JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
  2993. nor->info->flags & SPI_NOR_HAS_LOCK)) {
  2994. write_enable(nor);
  2995. write_sr(nor, 0);
  2996. spi_nor_wait_till_ready(nor);
  2997. }
  2998. if (nor->quad_enable) {
  2999. err = nor->quad_enable(nor);
  3000. if (err) {
  3001. dev_dbg(nor->dev, "quad mode not supported\n");
  3002. return err;
  3003. }
  3004. }
  3005. if (nor->addr_width == 4 &&
  3006. !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) &&
  3007. (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
  3008. !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
  3009. /*
  3010. * If the RESET# pin isn't hooked up properly, or the system
  3011. * otherwise doesn't perform a reset command in the boot
  3012. * sequence, it's impossible to 100% protect against unexpected
  3013. * reboots (e.g., crashes). Warn the user (or hopefully, system
  3014. * designer) that this is bad.
  3015. */
  3016. if (nor->flags & SNOR_F_BROKEN_RESET)
  3017. debug("enabling reset hack; may not recover from unexpected reboots\n");
  3018. set_4byte(nor, nor->info, 1);
  3019. }
  3020. return 0;
  3021. }
  3022. #ifdef CONFIG_SPI_FLASH_SOFT_RESET
  3023. /**
  3024. * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence
  3025. * @nor: the spi_nor structure
  3026. *
  3027. * This function can be used to switch from Octal DTR mode to legacy mode on a
  3028. * flash that supports it. The soft reset is executed in Octal DTR mode.
  3029. *
  3030. * Return: 0 for success, -errno for failure.
  3031. */
  3032. static int spi_nor_soft_reset(struct spi_nor *nor)
  3033. {
  3034. struct spi_mem_op op;
  3035. int ret;
  3036. enum spi_nor_cmd_ext ext;
  3037. ext = nor->cmd_ext_type;
  3038. nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
  3039. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
  3040. SPI_MEM_OP_NO_DUMMY,
  3041. SPI_MEM_OP_NO_ADDR,
  3042. SPI_MEM_OP_NO_DATA);
  3043. spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
  3044. ret = spi_mem_exec_op(nor->spi, &op);
  3045. if (ret) {
  3046. dev_warn(nor->dev, "Software reset enable failed: %d\n", ret);
  3047. goto out;
  3048. }
  3049. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0),
  3050. SPI_MEM_OP_NO_DUMMY,
  3051. SPI_MEM_OP_NO_ADDR,
  3052. SPI_MEM_OP_NO_DATA);
  3053. spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
  3054. ret = spi_mem_exec_op(nor->spi, &op);
  3055. if (ret) {
  3056. dev_warn(nor->dev, "Software reset failed: %d\n", ret);
  3057. goto out;
  3058. }
  3059. /*
  3060. * Software Reset is not instant, and the delay varies from flash to
  3061. * flash. Looking at a few flashes, most range somewhere below 100
  3062. * microseconds. So, wait for 200ms just to be sure.
  3063. */
  3064. udelay(SPI_NOR_SRST_SLEEP_LEN);
  3065. out:
  3066. nor->cmd_ext_type = ext;
  3067. return ret;
  3068. }
  3069. #endif /* CONFIG_SPI_FLASH_SOFT_RESET */
  3070. int spi_nor_remove(struct spi_nor *nor)
  3071. {
  3072. #ifdef CONFIG_SPI_FLASH_SOFT_RESET
  3073. if (nor->info->flags & SPI_NOR_OCTAL_DTR_READ &&
  3074. nor->flags & SNOR_F_SOFT_RESET)
  3075. return spi_nor_soft_reset(nor);
  3076. #endif
  3077. return 0;
  3078. }
  3079. void spi_nor_set_fixups(struct spi_nor *nor)
  3080. {
  3081. #ifdef CONFIG_SPI_FLASH_SPANSION
  3082. if (JEDEC_MFR(nor->info) == SNOR_MFR_CYPRESS) {
  3083. switch (nor->info->id[1]) {
  3084. case 0x2a: /* S25HL (QSPI, 3.3V) */
  3085. case 0x2b: /* S25HS (QSPI, 1.8V) */
  3086. nor->fixups = &s25hx_t_fixups;
  3087. break;
  3088. default:
  3089. break;
  3090. }
  3091. }
  3092. #endif
  3093. #ifdef CONFIG_SPI_FLASH_S28HS512T
  3094. if (!strcmp(nor->info->name, "s28hs512t"))
  3095. nor->fixups = &s28hs512t_fixups;
  3096. #endif
  3097. #ifdef CONFIG_SPI_FLASH_MT35XU
  3098. if (!strcmp(nor->info->name, "mt35xu512aba"))
  3099. nor->fixups = &mt35xu512aba_fixups;
  3100. #endif
  3101. }
  3102. int spi_nor_scan(struct spi_nor *nor)
  3103. {
  3104. struct spi_nor_flash_parameter params;
  3105. const struct flash_info *info = NULL;
  3106. struct mtd_info *mtd = &nor->mtd;
  3107. struct spi_slave *spi = nor->spi;
  3108. int ret;
  3109. int cfi_mtd_nb = 0;
  3110. #ifdef CONFIG_SYS_MAX_FLASH_BANKS
  3111. cfi_mtd_nb = CONFIG_SYS_MAX_FLASH_BANKS;
  3112. #endif
  3113. /* Reset SPI protocol for all commands. */
  3114. nor->reg_proto = SNOR_PROTO_1_1_1;
  3115. nor->read_proto = SNOR_PROTO_1_1_1;
  3116. nor->write_proto = SNOR_PROTO_1_1_1;
  3117. nor->read = spi_nor_read_data;
  3118. nor->write = spi_nor_write_data;
  3119. nor->read_reg = spi_nor_read_reg;
  3120. nor->write_reg = spi_nor_write_reg;
  3121. nor->setup = spi_nor_default_setup;
  3122. #ifdef CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT
  3123. /*
  3124. * When the flash is handed to us in a stateful mode like 8D-8D-8D, it
  3125. * is difficult to detect the mode the flash is in. One option is to
  3126. * read SFDP in all modes and see which one gives the correct "SFDP"
  3127. * signature, but not all flashes support SFDP in 8D-8D-8D mode.
  3128. *
  3129. * Further, even if you detect the mode of the flash via SFDP, you
  3130. * still have the problem of actually reading the ID. The Read ID
  3131. * command is not standardized across flash vendors. Flashes can have
  3132. * different dummy cycles needed for reading the ID. Some flashes even
  3133. * expect a 4-byte dummy address with the Read ID command. All this
  3134. * information cannot be obtained from the SFDP table.
  3135. *
  3136. * So, perform a Software Reset sequence before reading the ID and
  3137. * initializing the flash. A Soft Reset will bring back the flash in
  3138. * its default protocol mode assuming no non-volatile configuration was
  3139. * set. This will let us detect the flash even if ROM hands it to us in
  3140. * Octal DTR mode.
  3141. *
  3142. * To accommodate cases where there is more than one flash on a board,
  3143. * and only one of them needs a soft reset, failure to reset is not
  3144. * made fatal, and we still try to read ID if possible.
  3145. */
  3146. spi_nor_soft_reset(nor);
  3147. #endif /* CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT */
  3148. info = spi_nor_read_id(nor);
  3149. if (IS_ERR_OR_NULL(info))
  3150. return -ENOENT;
  3151. nor->info = info;
  3152. spi_nor_set_fixups(nor);
  3153. /* Parse the Serial Flash Discoverable Parameters table. */
  3154. ret = spi_nor_init_params(nor, info, &params);
  3155. if (ret)
  3156. return ret;
  3157. if (!mtd->name) {
  3158. sprintf(nor->mtd_name, "%s%d",
  3159. MTD_DEV_TYPE(MTD_DEV_TYPE_NOR),
  3160. cfi_mtd_nb + dev_seq(nor->dev));
  3161. mtd->name = nor->mtd_name;
  3162. }
  3163. mtd->dev = nor->dev;
  3164. mtd->priv = nor;
  3165. mtd->type = MTD_NORFLASH;
  3166. mtd->writesize = 1;
  3167. mtd->flags = MTD_CAP_NORFLASH;
  3168. mtd->size = params.size;
  3169. mtd->_erase = spi_nor_erase;
  3170. mtd->_read = spi_nor_read;
  3171. mtd->_write = spi_nor_write;
  3172. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  3173. /* NOR protection support for STmicro/Micron chips and similar */
  3174. if (JEDEC_MFR(info) == SNOR_MFR_ST ||
  3175. JEDEC_MFR(info) == SNOR_MFR_MICRON ||
  3176. JEDEC_MFR(info) == SNOR_MFR_SST ||
  3177. info->flags & SPI_NOR_HAS_LOCK) {
  3178. nor->flash_lock = stm_lock;
  3179. nor->flash_unlock = stm_unlock;
  3180. nor->flash_is_locked = stm_is_locked;
  3181. }
  3182. #endif
  3183. #ifdef CONFIG_SPI_FLASH_SST
  3184. /*
  3185. * sst26 series block protection implementation differs from other
  3186. * series.
  3187. */
  3188. if (info->flags & SPI_NOR_HAS_SST26LOCK) {
  3189. nor->flash_lock = sst26_lock;
  3190. nor->flash_unlock = sst26_unlock;
  3191. nor->flash_is_locked = sst26_is_locked;
  3192. }
  3193. #endif
  3194. if (info->flags & USE_FSR)
  3195. nor->flags |= SNOR_F_USE_FSR;
  3196. if (info->flags & SPI_NOR_HAS_TB)
  3197. nor->flags |= SNOR_F_HAS_SR_TB;
  3198. if (info->flags & NO_CHIP_ERASE)
  3199. nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
  3200. if (info->flags & USE_CLSR)
  3201. nor->flags |= SNOR_F_USE_CLSR;
  3202. if (info->flags & SPI_NOR_NO_ERASE)
  3203. mtd->flags |= MTD_NO_ERASE;
  3204. nor->page_size = params.page_size;
  3205. mtd->writebufsize = nor->page_size;
  3206. /* Some devices cannot do fast-read, no matter what DT tells us */
  3207. if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
  3208. params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  3209. /*
  3210. * Configure the SPI memory:
  3211. * - select op codes for (Fast) Read, Page Program and Sector Erase.
  3212. * - set the number of dummy cycles (mode cycles + wait states).
  3213. * - set the SPI protocols for register and memory accesses.
  3214. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
  3215. */
  3216. ret = spi_nor_setup(nor, info, &params);
  3217. if (ret)
  3218. return ret;
  3219. if (spi_nor_protocol_is_dtr(nor->read_proto)) {
  3220. /* Always use 4-byte addresses in DTR mode. */
  3221. nor->addr_width = 4;
  3222. } else if (nor->addr_width) {
  3223. /* already configured from SFDP */
  3224. } else if (info->addr_width) {
  3225. nor->addr_width = info->addr_width;
  3226. } else {
  3227. nor->addr_width = 3;
  3228. }
  3229. if (nor->addr_width == 3 && mtd->size > SZ_16M) {
  3230. #ifndef CONFIG_SPI_FLASH_BAR
  3231. /* enable 4-byte addressing if the device exceeds 16MiB */
  3232. nor->addr_width = 4;
  3233. if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
  3234. info->flags & SPI_NOR_4B_OPCODES)
  3235. spi_nor_set_4byte_opcodes(nor, info);
  3236. #else
  3237. /* Configure the BAR - discover bank cmds and read current bank */
  3238. nor->addr_width = 3;
  3239. ret = read_bar(nor, info);
  3240. if (ret < 0)
  3241. return ret;
  3242. #endif
  3243. }
  3244. if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
  3245. dev_dbg(nor->dev, "address width is too large: %u\n",
  3246. nor->addr_width);
  3247. return -EINVAL;
  3248. }
  3249. /* Send all the required SPI flash commands to initialize device */
  3250. ret = spi_nor_init(nor);
  3251. if (ret)
  3252. return ret;
  3253. nor->rdsr_dummy = params.rdsr_dummy;
  3254. nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes;
  3255. nor->name = info->name;
  3256. nor->size = mtd->size;
  3257. nor->erase_size = mtd->erasesize;
  3258. nor->sector_size = mtd->erasesize;
  3259. #ifndef CONFIG_SPL_BUILD
  3260. printf("SF: Detected %s with page size ", nor->name);
  3261. print_size(nor->page_size, ", erase size ");
  3262. print_size(nor->erase_size, ", total ");
  3263. print_size(nor->size, "");
  3264. puts("\n");
  3265. #endif
  3266. return 0;
  3267. }
  3268. /* U-Boot specific functions, need to extend MTD to support these */
  3269. int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
  3270. {
  3271. int sr = read_sr(nor);
  3272. if (sr < 0)
  3273. return sr;
  3274. return (sr >> 2) & 7;
  3275. }