omap3_logic.h 10 KB

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  1. /*
  2. * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
  3. * Peter Barada <peter.barada@logicpd.com>
  4. *
  5. * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
  6. * reference boards.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /* High Level Configuration Options */
  13. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  14. /*
  15. * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  16. * 64 bytes before this address should be set aside for u-boot.img's
  17. * header. That is 0x800FFFC0--0x80100000 should not be used for any
  18. * other needs. We use this rather than the inherited defines from
  19. * ti_armv7_common.h for backwards compatibility.
  20. */
  21. #define CONFIG_SYS_TEXT_BASE 0x80100000
  22. #define CONFIG_SPL_BSS_START_ADDR 0x80000000
  23. #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
  24. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  25. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  26. #include <configs/ti_omap3_common.h>
  27. /* Override default SPL info to minimize empty space and allow BCH8 in SPL */
  28. #undef CONFIG_SPL_TEXT_BASE
  29. #undef CONFIG_SPL_MAX_SIZE
  30. #define CONFIG_SPL_TEXT_BASE 0x40200000
  31. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
  32. /* Display CPU and Board information */
  33. #define CONFIG_DISPLAY_CPUINFO
  34. #define CONFIG_DISPLAY_BOARDINFO
  35. #define CONFIG_BOARD_LATE_INIT
  36. #define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
  37. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  38. #define CONFIG_SETUP_MEMORY_TAGS
  39. #define CONFIG_INITRD_TAG
  40. #define CONFIG_REVISION_TAG
  41. #define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
  42. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
  43. /* Hardware drivers */
  44. /* GPIO banks */
  45. #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
  46. #define CONFIG_USB_OMAP3
  47. /* select serial console configuration */
  48. #undef CONFIG_CONS_INDEX
  49. #define CONFIG_CONS_INDEX 1
  50. #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
  51. #define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
  52. /* commands to include */
  53. #define CONFIG_CMD_NAND
  54. #define CONFIG_CMD_MTDPARTS
  55. #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
  56. /* I2C */
  57. #define CONFIG_SYS_I2C_OMAP34XX
  58. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
  59. #define EXPANSION_EEPROM_I2C_BUS 2 /* I2C Bus for AT24C64 */
  60. #define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID
  61. /* USB */
  62. #define CONFIG_USB_MUSB_OMAP2PLUS
  63. #define CONFIG_USB_MUSB_PIO_ONLY
  64. #define CONFIG_USB_ETHER
  65. #define CONFIG_USB_ETHER_RNDIS
  66. #define CONFIG_USB_FUNCTION_FASTBOOT
  67. #define CONFIG_CMD_FASTBOOT
  68. #define CONFIG_ANDROID_BOOT_IMAGE
  69. #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
  70. #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
  71. #define CONFIG_SYS_CACHELINE_SIZE 64
  72. /* TWL4030 */
  73. #define CONFIG_TWL4030_PWM
  74. #define CONFIG_TWL4030_USB
  75. /* Board NAND Info. */
  76. #ifdef CONFIG_NAND
  77. #define CONFIG_NAND_OMAP_GPMC
  78. #define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
  79. #define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
  80. #define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
  81. #define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
  82. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  83. /* to access nand */
  84. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
  85. /* NAND devices */
  86. #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
  87. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  88. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  89. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  90. #define CONFIG_SYS_NAND_OOBSIZE 64
  91. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  92. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  93. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
  94. 13, 14, 16, 17, 18, 19, 20, 21, 22, \
  95. 23, 24, 25, 26, 27, 28, 30, 31, 32, \
  96. 33, 34, 35, 36, 37, 38, 39, 40, 41, \
  97. 42, 44, 45, 46, 47, 48, 49, 50, 51, \
  98. 52, 53, 54, 55, 56}
  99. #define CONFIG_SYS_NAND_ECCSIZE 512
  100. #define CONFIG_SYS_NAND_ECCBYTES 13
  101. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
  102. #define CONFIG_BCH
  103. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  104. #define CONFIG_SYS_NAND_MAX_ECCPOS 56
  105. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  106. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  107. #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
  108. #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
  109. #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO),"\
  110. "1920k(u-boot),128k(u-boot-env),"\
  111. "4m(kernel),-(fs)"
  112. #endif
  113. /* Environment information */
  114. /*
  115. * PREBOOT assumes the 4.3" display is attached. User can interrupt
  116. * and modify display variable to suit their needs.
  117. */
  118. #define CONFIG_PREBOOT \
  119. "echo ======================NOTICE============================;"\
  120. "echo \"The u-boot environment is not set.\";" \
  121. "echo \"If using a display a valid display variable for your panel\";" \
  122. "echo \"needs to be set.\";" \
  123. "echo \"Valid display options are:\";" \
  124. "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
  125. "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
  126. "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
  127. "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
  128. "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
  129. "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
  130. "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
  131. "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
  132. "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
  133. "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
  134. "setenv display 15;" \
  135. "setenv preboot;" \
  136. "nand unlock;" \
  137. "saveenv;"
  138. #define CONFIG_EXTRA_ENV_SETTINGS \
  139. "loadaddr=0x81000000\0" \
  140. "uimage=uImage\0" \
  141. "zimage=zImage\0" \
  142. "mtdids=" MTDIDS_DEFAULT "\0" \
  143. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  144. "mmcdev=0\0" \
  145. "mmcroot=/dev/mmcblk0p2 rw\0" \
  146. "mmcrootfstype=ext4 rootwait\0" \
  147. "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
  148. "nandrootfstype=ubifs rootwait\0" \
  149. "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
  150. "if run loadbootscript; then " \
  151. "run bootscript; " \
  152. "else " \
  153. "run defaultboot;" \
  154. "fi; " \
  155. "else run defaultboot; fi\0" \
  156. "defaultboot=run mmcramboot\0" \
  157. "consoledevice=ttyO0\0" \
  158. "display=15\0" \
  159. "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
  160. "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
  161. "rotation=0\0" \
  162. "vrfb_arg=if itest ${rotation} -ne 0; then " \
  163. "setenv bootargs ${bootargs} omapfb.vrfb=y " \
  164. "omapfb.rotate=${rotation}; " \
  165. "fi\0" \
  166. "optargs=ignore_loglevel early_printk no_console_suspend\0" \
  167. "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
  168. "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
  169. "${optargs};" \
  170. "run addmtdparts; " \
  171. "run vrfb_arg\0" \
  172. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  173. "bootscript=echo 'Running bootscript from mmc ...'; " \
  174. "source ${loadaddr}\0" \
  175. "loaduimage=mmc rescan; " \
  176. "fatload mmc ${mmcdev} ${loadaddr} ${uimage}\0" \
  177. "loadzimage=mmc rescan; " \
  178. "fatload mmc ${mmcdev} ${loadaddr} ${zimage}\0" \
  179. "ramdisksize=64000\0" \
  180. "ramdiskaddr=0x82000000\0" \
  181. "ramdiskimage=rootfs.ext2.gz.uboot\0" \
  182. "loadramdisk=mmc rescan; " \
  183. "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}\0" \
  184. "ramargs=run setconsole; setenv bootargs console=${console} " \
  185. "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
  186. "mmcargs=run setconsole; setenv bootargs console=${console} " \
  187. "${optargs} " \
  188. "root=${mmcroot} " \
  189. "rootfstype=${mmcrootfstype}\0" \
  190. "nandargs=run setconsole; setenv bootargs console=${console} " \
  191. "${optargs} " \
  192. "root=${nandroot} " \
  193. "rootfstype=${nandrootfstype}\0" \
  194. "fdtaddr=0x86000000\0" \
  195. "loadfdtimage=mmc rescan; " \
  196. "fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
  197. "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
  198. "run mmcargs; " \
  199. "run common_bootargs; " \
  200. "run dump_bootargs; " \
  201. "run loadzimage; " \
  202. "run loadfdtimage; " \
  203. "bootz ${loadaddr} - ${fdtaddr}\0" \
  204. "mmcramboot=echo 'Booting uImage kernel from mmc w/ramdisk...'; " \
  205. "run ramargs; " \
  206. "run common_bootargs; " \
  207. "run dump_bootargs; " \
  208. "run loaduimage; " \
  209. "run loadramdisk; " \
  210. "bootm ${loadaddr} ${ramdiskaddr}\0" \
  211. "mmcrambootz=echo 'Booting zImage kernel from mmc w/ramdisk...'; " \
  212. "run ramargs; " \
  213. "run common_bootargs; " \
  214. "run dump_bootargs; " \
  215. "run loadzimage; " \
  216. "run loadramdisk; " \
  217. "run loadfdtimage; " \
  218. "bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr}\0; " \
  219. "tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
  220. "run ramargs; " \
  221. "run common_bootargs; " \
  222. "run dump_bootargs; " \
  223. "tftpboot ${loadaddr} ${uimage}; " \
  224. "tftpboot ${ramdiskaddr} ${ramdiskimage}; " \
  225. "bootm ${loadaddr} ${ramdiskaddr}\0"
  226. #define CONFIG_BOOTCOMMAND \
  227. "run autoboot"
  228. /* Miscellaneous configurable options */
  229. #define CONFIG_AUTO_COMPLETE
  230. /* memtest works on */
  231. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
  232. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  233. 0x01F00000) /* 31MB */
  234. /* FLASH and environment organization */
  235. /* **** PISMO SUPPORT *** */
  236. #if defined(CONFIG_CMD_NAND)
  237. #define CONFIG_SYS_FLASH_BASE NAND_BASE
  238. #elif defined(CONFIG_CMD_ONENAND)
  239. #define CONFIG_SYS_FLASH_BASE ONENAND_MAP
  240. #endif
  241. /* Monitor at start of flash */
  242. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  243. #define CONFIG_ENV_IS_IN_NAND 1
  244. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  245. #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
  246. #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  247. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
  248. #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
  249. #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  250. /* SMSC922x Ethernet */
  251. #if defined(CONFIG_CMD_NET)
  252. #define CONFIG_SMC911X
  253. #define CONFIG_SMC911X_32_BIT
  254. #define CONFIG_SMC911X_BASE 0x08000000
  255. #endif /* (CONFIG_CMD_NET) */
  256. /* Defines for SPL */
  257. #define CONFIG_SPL_OMAP3_ID_NAND
  258. /* NAND: SPL falcon mode configs */
  259. #ifdef CONFIG_SPL_OS_BOOT
  260. #define CONFIG_CMD_SPL_NAND_OFS 0x240000
  261. #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
  262. #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
  263. #endif
  264. #endif /* __CONFIG_H */