sh_eth.h 15 KB

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  1. /*
  2. * sh_eth.h - Driver for Renesas SuperH ethernet controller.
  3. *
  4. * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
  5. * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
  6. * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <netdev.h>
  11. #include <asm/types.h>
  12. #define SHETHER_NAME "sh_eth"
  13. #if defined(CONFIG_SH)
  14. /* Malloc returns addresses in the P1 area (cacheable). However we need to
  15. use area P2 (non-cacheable) */
  16. #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
  17. /* The ethernet controller needs to use physical addresses */
  18. #if defined(CONFIG_SH_32BIT)
  19. #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
  20. #else
  21. #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
  22. #endif
  23. #elif defined(CONFIG_ARM)
  24. #define inl readl
  25. #define outl writel
  26. #define ADDR_TO_PHY(addr) ((int)(addr))
  27. #define ADDR_TO_P2(addr) (addr)
  28. #endif /* defined(CONFIG_SH) */
  29. /* base padding size is 16 */
  30. #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
  31. #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
  32. #endif
  33. /* Number of supported ports */
  34. #define MAX_PORT_NUM 2
  35. /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
  36. buffers must be a multiple of 32 bytes */
  37. #define MAX_BUF_SIZE (48 * 32)
  38. /* The number of tx descriptors must be large enough to point to 5 or more
  39. frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
  40. We use one descriptor per frame */
  41. #define NUM_TX_DESC 8
  42. /* The size of the tx descriptor is determined by how much padding is used.
  43. 4, 20, or 52 bytes of padding can be used */
  44. #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  45. /* Tx descriptor. We always use 3 bytes of padding */
  46. struct tx_desc_s {
  47. volatile u32 td0;
  48. u32 td1;
  49. u32 td2; /* Buffer start */
  50. u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
  51. };
  52. /* There is no limitation in the number of rx descriptors */
  53. #define NUM_RX_DESC 8
  54. /* The size of the rx descriptor is determined by how much padding is used.
  55. 4, 20, or 52 bytes of padding can be used */
  56. #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  57. /* aligned cache line size */
  58. #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
  59. /* Rx descriptor. We always use 4 bytes of padding */
  60. struct rx_desc_s {
  61. volatile u32 rd0;
  62. volatile u32 rd1;
  63. u32 rd2; /* Buffer start */
  64. u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
  65. };
  66. struct sh_eth_info {
  67. struct tx_desc_s *tx_desc_alloc;
  68. struct tx_desc_s *tx_desc_base;
  69. struct tx_desc_s *tx_desc_cur;
  70. struct rx_desc_s *rx_desc_alloc;
  71. struct rx_desc_s *rx_desc_base;
  72. struct rx_desc_s *rx_desc_cur;
  73. u8 *rx_buf_alloc;
  74. u8 *rx_buf_base;
  75. u8 mac_addr[6];
  76. u8 phy_addr;
  77. struct eth_device *dev;
  78. struct phy_device *phydev;
  79. };
  80. struct sh_eth_dev {
  81. int port;
  82. struct sh_eth_info port_info[MAX_PORT_NUM];
  83. };
  84. /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
  85. enum {
  86. /* E-DMAC registers */
  87. EDSR = 0,
  88. EDMR,
  89. EDTRR,
  90. EDRRR,
  91. EESR,
  92. EESIPR,
  93. TDLAR,
  94. TDFAR,
  95. TDFXR,
  96. TDFFR,
  97. RDLAR,
  98. RDFAR,
  99. RDFXR,
  100. RDFFR,
  101. TRSCER,
  102. RMFCR,
  103. TFTR,
  104. FDR,
  105. RMCR,
  106. EDOCR,
  107. TFUCR,
  108. RFOCR,
  109. FCFTR,
  110. RPADIR,
  111. TRIMD,
  112. RBWAR,
  113. TBRAR,
  114. /* Ether registers */
  115. ECMR,
  116. ECSR,
  117. ECSIPR,
  118. PIR,
  119. PSR,
  120. RDMLR,
  121. PIPR,
  122. RFLR,
  123. IPGR,
  124. APR,
  125. MPR,
  126. PFTCR,
  127. PFRCR,
  128. RFCR,
  129. RFCF,
  130. TPAUSER,
  131. TPAUSECR,
  132. BCFR,
  133. BCFRR,
  134. GECMR,
  135. BCULR,
  136. MAHR,
  137. MALR,
  138. TROCR,
  139. CDCR,
  140. LCCR,
  141. CNDCR,
  142. CEFCR,
  143. FRECR,
  144. TSFRCR,
  145. TLFRCR,
  146. CERCR,
  147. CEECR,
  148. RMIIMR, /* R8A7790 */
  149. MAFCR,
  150. RTRATE,
  151. CSMR,
  152. RMII_MII,
  153. /* This value must be written at last. */
  154. SH_ETH_MAX_REGISTER_OFFSET,
  155. };
  156. static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  157. [EDSR] = 0x0000,
  158. [EDMR] = 0x0400,
  159. [EDTRR] = 0x0408,
  160. [EDRRR] = 0x0410,
  161. [EESR] = 0x0428,
  162. [EESIPR] = 0x0430,
  163. [TDLAR] = 0x0010,
  164. [TDFAR] = 0x0014,
  165. [TDFXR] = 0x0018,
  166. [TDFFR] = 0x001c,
  167. [RDLAR] = 0x0030,
  168. [RDFAR] = 0x0034,
  169. [RDFXR] = 0x0038,
  170. [RDFFR] = 0x003c,
  171. [TRSCER] = 0x0438,
  172. [RMFCR] = 0x0440,
  173. [TFTR] = 0x0448,
  174. [FDR] = 0x0450,
  175. [RMCR] = 0x0458,
  176. [RPADIR] = 0x0460,
  177. [FCFTR] = 0x0468,
  178. [CSMR] = 0x04E4,
  179. [ECMR] = 0x0500,
  180. [ECSR] = 0x0510,
  181. [ECSIPR] = 0x0518,
  182. [PIR] = 0x0520,
  183. [PSR] = 0x0528,
  184. [PIPR] = 0x052c,
  185. [RFLR] = 0x0508,
  186. [APR] = 0x0554,
  187. [MPR] = 0x0558,
  188. [PFTCR] = 0x055c,
  189. [PFRCR] = 0x0560,
  190. [TPAUSER] = 0x0564,
  191. [GECMR] = 0x05b0,
  192. [BCULR] = 0x05b4,
  193. [MAHR] = 0x05c0,
  194. [MALR] = 0x05c8,
  195. [TROCR] = 0x0700,
  196. [CDCR] = 0x0708,
  197. [LCCR] = 0x0710,
  198. [CEFCR] = 0x0740,
  199. [FRECR] = 0x0748,
  200. [TSFRCR] = 0x0750,
  201. [TLFRCR] = 0x0758,
  202. [RFCR] = 0x0760,
  203. [CERCR] = 0x0768,
  204. [CEECR] = 0x0770,
  205. [MAFCR] = 0x0778,
  206. [RMII_MII] = 0x0790,
  207. };
  208. #if defined(SH_ETH_TYPE_RZ)
  209. static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
  210. [EDSR] = 0x0000,
  211. [EDMR] = 0x0400,
  212. [EDTRR] = 0x0408,
  213. [EDRRR] = 0x0410,
  214. [EESR] = 0x0428,
  215. [EESIPR] = 0x0430,
  216. [TDLAR] = 0x0010,
  217. [TDFAR] = 0x0014,
  218. [TDFXR] = 0x0018,
  219. [TDFFR] = 0x001c,
  220. [RDLAR] = 0x0030,
  221. [RDFAR] = 0x0034,
  222. [RDFXR] = 0x0038,
  223. [RDFFR] = 0x003c,
  224. [TRSCER] = 0x0438,
  225. [RMFCR] = 0x0440,
  226. [TFTR] = 0x0448,
  227. [FDR] = 0x0450,
  228. [RMCR] = 0x0458,
  229. [RPADIR] = 0x0460,
  230. [FCFTR] = 0x0468,
  231. [CSMR] = 0x04E4,
  232. [ECMR] = 0x0500,
  233. [ECSR] = 0x0510,
  234. [ECSIPR] = 0x0518,
  235. [PSR] = 0x0528,
  236. [PIPR] = 0x052c,
  237. [RFLR] = 0x0508,
  238. [APR] = 0x0554,
  239. [MPR] = 0x0558,
  240. [PFTCR] = 0x055c,
  241. [PFRCR] = 0x0560,
  242. [TPAUSER] = 0x0564,
  243. [GECMR] = 0x05b0,
  244. [BCULR] = 0x05b4,
  245. [MAHR] = 0x05c0,
  246. [MALR] = 0x05c8,
  247. [TROCR] = 0x0700,
  248. [CDCR] = 0x0708,
  249. [LCCR] = 0x0710,
  250. [CEFCR] = 0x0740,
  251. [FRECR] = 0x0748,
  252. [TSFRCR] = 0x0750,
  253. [TLFRCR] = 0x0758,
  254. [RFCR] = 0x0760,
  255. [CERCR] = 0x0768,
  256. [CEECR] = 0x0770,
  257. [MAFCR] = 0x0778,
  258. [RMII_MII] = 0x0790,
  259. };
  260. #endif
  261. static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
  262. [ECMR] = 0x0100,
  263. [RFLR] = 0x0108,
  264. [ECSR] = 0x0110,
  265. [ECSIPR] = 0x0118,
  266. [PIR] = 0x0120,
  267. [PSR] = 0x0128,
  268. [RDMLR] = 0x0140,
  269. [IPGR] = 0x0150,
  270. [APR] = 0x0154,
  271. [MPR] = 0x0158,
  272. [TPAUSER] = 0x0164,
  273. [RFCF] = 0x0160,
  274. [TPAUSECR] = 0x0168,
  275. [BCFRR] = 0x016c,
  276. [MAHR] = 0x01c0,
  277. [MALR] = 0x01c8,
  278. [TROCR] = 0x01d0,
  279. [CDCR] = 0x01d4,
  280. [LCCR] = 0x01d8,
  281. [CNDCR] = 0x01dc,
  282. [CEFCR] = 0x01e4,
  283. [FRECR] = 0x01e8,
  284. [TSFRCR] = 0x01ec,
  285. [TLFRCR] = 0x01f0,
  286. [RFCR] = 0x01f4,
  287. [MAFCR] = 0x01f8,
  288. [RTRATE] = 0x01fc,
  289. [EDMR] = 0x0000,
  290. [EDTRR] = 0x0008,
  291. [EDRRR] = 0x0010,
  292. [TDLAR] = 0x0018,
  293. [RDLAR] = 0x0020,
  294. [EESR] = 0x0028,
  295. [EESIPR] = 0x0030,
  296. [TRSCER] = 0x0038,
  297. [RMFCR] = 0x0040,
  298. [TFTR] = 0x0048,
  299. [FDR] = 0x0050,
  300. [RMCR] = 0x0058,
  301. [TFUCR] = 0x0064,
  302. [RFOCR] = 0x0068,
  303. [RMIIMR] = 0x006C,
  304. [FCFTR] = 0x0070,
  305. [RPADIR] = 0x0078,
  306. [TRIMD] = 0x007c,
  307. [RBWAR] = 0x00c8,
  308. [RDFAR] = 0x00cc,
  309. [TBRAR] = 0x00d4,
  310. [TDFAR] = 0x00d8,
  311. };
  312. /* Register Address */
  313. #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
  314. #define SH_ETH_TYPE_GETHER
  315. #define BASE_IO_ADDR 0xfee00000
  316. #elif defined(CONFIG_CPU_SH7757) || \
  317. defined(CONFIG_CPU_SH7752) || \
  318. defined(CONFIG_CPU_SH7753)
  319. #if defined(CONFIG_SH_ETHER_USE_GETHER)
  320. #define SH_ETH_TYPE_GETHER
  321. #define BASE_IO_ADDR 0xfee00000
  322. #else
  323. #define SH_ETH_TYPE_ETHER
  324. #define BASE_IO_ADDR 0xfef00000
  325. #endif
  326. #elif defined(CONFIG_CPU_SH7724)
  327. #define SH_ETH_TYPE_ETHER
  328. #define BASE_IO_ADDR 0xA4600000
  329. #elif defined(CONFIG_R8A7740)
  330. #define SH_ETH_TYPE_GETHER
  331. #define BASE_IO_ADDR 0xE9A00000
  332. #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
  333. defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
  334. #define SH_ETH_TYPE_ETHER
  335. #define BASE_IO_ADDR 0xEE700200
  336. #elif defined(CONFIG_R7S72100)
  337. #define SH_ETH_TYPE_RZ
  338. #define BASE_IO_ADDR 0xE8203000
  339. #endif
  340. /*
  341. * Register's bits
  342. * Copy from Linux driver source code
  343. */
  344. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  345. /* EDSR */
  346. enum EDSR_BIT {
  347. EDSR_ENT = 0x01, EDSR_ENR = 0x02,
  348. };
  349. #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
  350. #endif
  351. /* EDMR */
  352. enum DMAC_M_BIT {
  353. EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
  354. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  355. EDMR_SRST = 0x03, /* Receive/Send reset */
  356. EMDR_DESC_R = 0x30, /* Descriptor reserve size */
  357. EDMR_EL = 0x40, /* Litte endian */
  358. #elif defined(SH_ETH_TYPE_ETHER)
  359. EDMR_SRST = 0x01,
  360. EMDR_DESC_R = 0x30, /* Descriptor reserve size */
  361. EDMR_EL = 0x40, /* Litte endian */
  362. #else
  363. EDMR_SRST = 0x01,
  364. #endif
  365. };
  366. #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
  367. # define EMDR_DESC EDMR_DL1
  368. #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
  369. # define EMDR_DESC EDMR_DL0
  370. #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
  371. # define EMDR_DESC 0
  372. #endif
  373. /* RFLR */
  374. #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
  375. /* EDTRR */
  376. enum DMAC_T_BIT {
  377. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  378. EDTRR_TRNS = 0x03,
  379. #else
  380. EDTRR_TRNS = 0x01,
  381. #endif
  382. };
  383. /* GECMR */
  384. enum GECMR_BIT {
  385. #if defined(CONFIG_CPU_SH7757) || \
  386. defined(CONFIG_CPU_SH7752) || \
  387. defined(CONFIG_CPU_SH7753)
  388. GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
  389. #else
  390. GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
  391. #endif
  392. };
  393. /* EDRRR*/
  394. enum EDRRR_R_BIT {
  395. EDRRR_R = 0x01,
  396. };
  397. /* TPAUSER */
  398. enum TPAUSER_BIT {
  399. TPAUSER_TPAUSE = 0x0000ffff,
  400. TPAUSER_UNLIMITED = 0,
  401. };
  402. /* BCFR */
  403. enum BCFR_BIT {
  404. BCFR_RPAUSE = 0x0000ffff,
  405. BCFR_UNLIMITED = 0,
  406. };
  407. /* PIR */
  408. enum PIR_BIT {
  409. PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
  410. };
  411. /* PSR */
  412. enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
  413. /* EESR */
  414. enum EESR_BIT {
  415. #if defined(SH_ETH_TYPE_ETHER)
  416. EESR_TWB = 0x40000000,
  417. #else
  418. EESR_TWB = 0xC0000000,
  419. EESR_TC1 = 0x20000000,
  420. EESR_TUC = 0x10000000,
  421. EESR_ROC = 0x80000000,
  422. #endif
  423. EESR_TABT = 0x04000000,
  424. EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
  425. #if defined(SH_ETH_TYPE_ETHER)
  426. EESR_ADE = 0x00800000,
  427. #endif
  428. EESR_ECI = 0x00400000,
  429. EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
  430. EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
  431. EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
  432. #if defined(SH_ETH_TYPE_ETHER)
  433. EESR_CND = 0x00000800,
  434. #endif
  435. EESR_DLC = 0x00000400,
  436. EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
  437. EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
  438. EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
  439. EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
  440. EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
  441. };
  442. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  443. # define TX_CHECK (EESR_TC1 | EESR_FTC)
  444. # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
  445. | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
  446. # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
  447. #else
  448. # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
  449. # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
  450. | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
  451. # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
  452. #endif
  453. /* EESIPR */
  454. enum DMAC_IM_BIT {
  455. DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
  456. DMAC_M_RABT = 0x02000000,
  457. DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
  458. DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
  459. DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
  460. DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
  461. DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
  462. DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
  463. DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
  464. DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
  465. DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
  466. DMAC_M_RINT1 = 0x00000001,
  467. };
  468. /* Receive descriptor bit */
  469. enum RD_STS_BIT {
  470. RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
  471. RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
  472. RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
  473. RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
  474. RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
  475. RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
  476. RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
  477. RD_RFS1 = 0x00000001,
  478. };
  479. #define RDF1ST RD_RFP1
  480. #define RDFEND RD_RFP0
  481. #define RD_RFP (RD_RFP1|RD_RFP0)
  482. /* RDFFR*/
  483. enum RDFFR_BIT {
  484. RDFFR_RDLF = 0x01,
  485. };
  486. /* FCFTR */
  487. enum FCFTR_BIT {
  488. FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
  489. FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
  490. FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
  491. };
  492. #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
  493. #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
  494. /* Transfer descriptor bit */
  495. enum TD_STS_BIT {
  496. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
  497. defined(SH_ETH_TYPE_RZ)
  498. TD_TACT = 0x80000000,
  499. #else
  500. TD_TACT = 0x7fffffff,
  501. #endif
  502. TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
  503. TD_TFP0 = 0x10000000,
  504. };
  505. #define TDF1ST TD_TFP1
  506. #define TDFEND TD_TFP0
  507. #define TD_TFP (TD_TFP1|TD_TFP0)
  508. /* RMCR */
  509. enum RECV_RST_BIT { RMCR_RST = 0x01, };
  510. /* ECMR */
  511. enum FELIC_MODE_BIT {
  512. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  513. ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
  514. ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
  515. #endif
  516. ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
  517. ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
  518. ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
  519. ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
  520. ECMR_PRM = 0x00000001,
  521. #ifdef CONFIG_CPU_SH7724
  522. ECMR_RTM = 0x00000010,
  523. #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
  524. defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
  525. ECMR_RTM = 0x00000004,
  526. #endif
  527. };
  528. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  529. #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
  530. ECMR_RXF | ECMR_TXF | ECMR_MCT)
  531. #elif defined(SH_ETH_TYPE_ETHER)
  532. #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
  533. #else
  534. #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
  535. #endif
  536. /* ECSR */
  537. enum ECSR_STATUS_BIT {
  538. #if defined(SH_ETH_TYPE_ETHER)
  539. ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
  540. #endif
  541. ECSR_LCHNG = 0x04,
  542. ECSR_MPD = 0x02, ECSR_ICD = 0x01,
  543. };
  544. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  545. # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
  546. #else
  547. # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
  548. ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
  549. #endif
  550. /* ECSIPR */
  551. enum ECSIPR_STATUS_MASK_BIT {
  552. #if defined(SH_ETH_TYPE_ETHER)
  553. ECSIPR_BRCRXIP = 0x20,
  554. ECSIPR_PSRTOIP = 0x10,
  555. #elif defined(SH_ETY_TYPE_GETHER)
  556. ECSIPR_PSRTOIP = 0x10,
  557. ECSIPR_PHYIP = 0x08,
  558. #endif
  559. ECSIPR_LCHNGIP = 0x04,
  560. ECSIPR_MPDIP = 0x02,
  561. ECSIPR_ICDIP = 0x01,
  562. };
  563. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  564. # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
  565. #else
  566. # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
  567. ECSIPR_ICDIP | ECSIPR_MPDIP)
  568. #endif
  569. /* APR */
  570. enum APR_BIT {
  571. APR_AP = 0x00000004,
  572. };
  573. /* MPR */
  574. enum MPR_BIT {
  575. MPR_MP = 0x00000006,
  576. };
  577. /* TRSCER */
  578. enum DESC_I_BIT {
  579. DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
  580. DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
  581. DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
  582. DESC_I_RINT1 = 0x0001,
  583. };
  584. /* RPADIR */
  585. enum RPADIR_BIT {
  586. RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
  587. RPADIR_PADR = 0x0003f,
  588. };
  589. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  590. # define RPADIR_INIT (0x00)
  591. #else
  592. # define RPADIR_INIT (RPADIR_PADS1)
  593. #endif
  594. /* FDR */
  595. enum FIFO_SIZE_BIT {
  596. FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
  597. };
  598. static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
  599. int enum_index)
  600. {
  601. #if defined(SH_ETH_TYPE_GETHER)
  602. const u16 *reg_offset = sh_eth_offset_gigabit;
  603. #elif defined(SH_ETH_TYPE_ETHER)
  604. const u16 *reg_offset = sh_eth_offset_fast_sh4;
  605. #elif defined(SH_ETH_TYPE_RZ)
  606. const u16 *reg_offset = sh_eth_offset_rz;
  607. #else
  608. #error
  609. #endif
  610. return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
  611. }
  612. static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
  613. int enum_index)
  614. {
  615. outl(data, sh_eth_reg_addr(eth, enum_index));
  616. }
  617. static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
  618. int enum_index)
  619. {
  620. return inl(sh_eth_reg_addr(eth, enum_index));
  621. }