macb.c 19 KB

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  1. /*
  2. * Copyright (C) 2005-2006 Atmel Corporation
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. /*
  8. * The u-boot networking stack is a little weird. It seems like the
  9. * networking core allocates receive buffers up front without any
  10. * regard to the hardware that's supposed to actually receive those
  11. * packets.
  12. *
  13. * The MACB receives packets into 128-byte receive buffers, so the
  14. * buffers allocated by the core isn't very practical to use. We'll
  15. * allocate our own, but we need one such buffer in case a packet
  16. * wraps around the DMA ring so that we have to copy it.
  17. *
  18. * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
  19. * configuration header. This way, the core allocates one RX buffer
  20. * and one TX buffer, each of which can hold a ethernet packet of
  21. * maximum size.
  22. *
  23. * For some reason, the networking core unconditionally specifies a
  24. * 32-byte packet "alignment" (which really should be called
  25. * "padding"). MACB shouldn't need that, but we'll refrain from any
  26. * core modifications here...
  27. */
  28. #include <net.h>
  29. #include <netdev.h>
  30. #include <malloc.h>
  31. #include <miiphy.h>
  32. #include <linux/mii.h>
  33. #include <asm/io.h>
  34. #include <asm/dma-mapping.h>
  35. #include <asm/arch/clk.h>
  36. #include <asm-generic/errno.h>
  37. #include "macb.h"
  38. #define MACB_RX_BUFFER_SIZE 4096
  39. #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
  40. #define MACB_TX_RING_SIZE 16
  41. #define MACB_TX_TIMEOUT 1000
  42. #define MACB_AUTONEG_TIMEOUT 5000000
  43. struct macb_dma_desc {
  44. u32 addr;
  45. u32 ctrl;
  46. };
  47. #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
  48. #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
  49. #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
  50. #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
  51. #define RXADDR_USED 0x00000001
  52. #define RXADDR_WRAP 0x00000002
  53. #define RXBUF_FRMLEN_MASK 0x00000fff
  54. #define RXBUF_FRAME_START 0x00004000
  55. #define RXBUF_FRAME_END 0x00008000
  56. #define RXBUF_TYPEID_MATCH 0x00400000
  57. #define RXBUF_ADDR4_MATCH 0x00800000
  58. #define RXBUF_ADDR3_MATCH 0x01000000
  59. #define RXBUF_ADDR2_MATCH 0x02000000
  60. #define RXBUF_ADDR1_MATCH 0x04000000
  61. #define RXBUF_BROADCAST 0x80000000
  62. #define TXBUF_FRMLEN_MASK 0x000007ff
  63. #define TXBUF_FRAME_END 0x00008000
  64. #define TXBUF_NOCRC 0x00010000
  65. #define TXBUF_EXHAUSTED 0x08000000
  66. #define TXBUF_UNDERRUN 0x10000000
  67. #define TXBUF_MAXRETRY 0x20000000
  68. #define TXBUF_WRAP 0x40000000
  69. #define TXBUF_USED 0x80000000
  70. struct macb_device {
  71. void *regs;
  72. unsigned int rx_tail;
  73. unsigned int tx_head;
  74. unsigned int tx_tail;
  75. void *rx_buffer;
  76. void *tx_buffer;
  77. struct macb_dma_desc *rx_ring;
  78. struct macb_dma_desc *tx_ring;
  79. unsigned long rx_buffer_dma;
  80. unsigned long rx_ring_dma;
  81. unsigned long tx_ring_dma;
  82. struct macb_dma_desc *dummy_desc;
  83. unsigned long dummy_desc_dma;
  84. const struct device *dev;
  85. struct eth_device netdev;
  86. unsigned short phy_addr;
  87. struct mii_dev *bus;
  88. };
  89. #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
  90. static int macb_is_gem(struct macb_device *macb)
  91. {
  92. return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
  93. }
  94. #ifndef cpu_is_sama5d2
  95. #define cpu_is_sama5d2() 0
  96. #endif
  97. #ifndef cpu_is_sama5d4
  98. #define cpu_is_sama5d4() 0
  99. #endif
  100. static int gem_is_gigabit_capable(struct macb_device *macb)
  101. {
  102. /*
  103. * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
  104. * configured to support only 10/100.
  105. */
  106. return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
  107. }
  108. static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
  109. {
  110. unsigned long netctl;
  111. unsigned long netstat;
  112. unsigned long frame;
  113. netctl = macb_readl(macb, NCR);
  114. netctl |= MACB_BIT(MPE);
  115. macb_writel(macb, NCR, netctl);
  116. frame = (MACB_BF(SOF, 1)
  117. | MACB_BF(RW, 1)
  118. | MACB_BF(PHYA, macb->phy_addr)
  119. | MACB_BF(REGA, reg)
  120. | MACB_BF(CODE, 2)
  121. | MACB_BF(DATA, value));
  122. macb_writel(macb, MAN, frame);
  123. do {
  124. netstat = macb_readl(macb, NSR);
  125. } while (!(netstat & MACB_BIT(IDLE)));
  126. netctl = macb_readl(macb, NCR);
  127. netctl &= ~MACB_BIT(MPE);
  128. macb_writel(macb, NCR, netctl);
  129. }
  130. static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
  131. {
  132. unsigned long netctl;
  133. unsigned long netstat;
  134. unsigned long frame;
  135. netctl = macb_readl(macb, NCR);
  136. netctl |= MACB_BIT(MPE);
  137. macb_writel(macb, NCR, netctl);
  138. frame = (MACB_BF(SOF, 1)
  139. | MACB_BF(RW, 2)
  140. | MACB_BF(PHYA, macb->phy_addr)
  141. | MACB_BF(REGA, reg)
  142. | MACB_BF(CODE, 2));
  143. macb_writel(macb, MAN, frame);
  144. do {
  145. netstat = macb_readl(macb, NSR);
  146. } while (!(netstat & MACB_BIT(IDLE)));
  147. frame = macb_readl(macb, MAN);
  148. netctl = macb_readl(macb, NCR);
  149. netctl &= ~MACB_BIT(MPE);
  150. macb_writel(macb, NCR, netctl);
  151. return MACB_BFEXT(DATA, frame);
  152. }
  153. void __weak arch_get_mdio_control(const char *name)
  154. {
  155. return;
  156. }
  157. #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
  158. int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
  159. {
  160. struct eth_device *dev = eth_get_dev_by_name(devname);
  161. struct macb_device *macb = to_macb(dev);
  162. if (macb->phy_addr != phy_adr)
  163. return -1;
  164. arch_get_mdio_control(devname);
  165. *value = macb_mdio_read(macb, reg);
  166. return 0;
  167. }
  168. int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
  169. {
  170. struct eth_device *dev = eth_get_dev_by_name(devname);
  171. struct macb_device *macb = to_macb(dev);
  172. if (macb->phy_addr != phy_adr)
  173. return -1;
  174. arch_get_mdio_control(devname);
  175. macb_mdio_write(macb, reg, value);
  176. return 0;
  177. }
  178. #endif
  179. #define RX 1
  180. #define TX 0
  181. static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
  182. {
  183. if (rx)
  184. invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
  185. MACB_RX_DMA_DESC_SIZE);
  186. else
  187. invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
  188. MACB_TX_DMA_DESC_SIZE);
  189. }
  190. static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
  191. {
  192. if (rx)
  193. flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
  194. MACB_RX_DMA_DESC_SIZE);
  195. else
  196. flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
  197. MACB_TX_DMA_DESC_SIZE);
  198. }
  199. static inline void macb_flush_rx_buffer(struct macb_device *macb)
  200. {
  201. flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
  202. MACB_RX_BUFFER_SIZE);
  203. }
  204. static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
  205. {
  206. invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
  207. MACB_RX_BUFFER_SIZE);
  208. }
  209. #if defined(CONFIG_CMD_NET)
  210. static int macb_send(struct eth_device *netdev, void *packet, int length)
  211. {
  212. struct macb_device *macb = to_macb(netdev);
  213. unsigned long paddr, ctrl;
  214. unsigned int tx_head = macb->tx_head;
  215. int i;
  216. paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
  217. ctrl = length & TXBUF_FRMLEN_MASK;
  218. ctrl |= TXBUF_FRAME_END;
  219. if (tx_head == (MACB_TX_RING_SIZE - 1)) {
  220. ctrl |= TXBUF_WRAP;
  221. macb->tx_head = 0;
  222. } else {
  223. macb->tx_head++;
  224. }
  225. macb->tx_ring[tx_head].ctrl = ctrl;
  226. macb->tx_ring[tx_head].addr = paddr;
  227. barrier();
  228. macb_flush_ring_desc(macb, TX);
  229. /* Do we need check paddr and length is dcache line aligned? */
  230. flush_dcache_range(paddr, paddr + length);
  231. macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
  232. /*
  233. * I guess this is necessary because the networking core may
  234. * re-use the transmit buffer as soon as we return...
  235. */
  236. for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
  237. barrier();
  238. macb_invalidate_ring_desc(macb, TX);
  239. ctrl = macb->tx_ring[tx_head].ctrl;
  240. if (ctrl & TXBUF_USED)
  241. break;
  242. udelay(1);
  243. }
  244. dma_unmap_single(packet, length, paddr);
  245. if (i <= MACB_TX_TIMEOUT) {
  246. if (ctrl & TXBUF_UNDERRUN)
  247. printf("%s: TX underrun\n", netdev->name);
  248. if (ctrl & TXBUF_EXHAUSTED)
  249. printf("%s: TX buffers exhausted in mid frame\n",
  250. netdev->name);
  251. } else {
  252. printf("%s: TX timeout\n", netdev->name);
  253. }
  254. /* No one cares anyway */
  255. return 0;
  256. }
  257. static void reclaim_rx_buffers(struct macb_device *macb,
  258. unsigned int new_tail)
  259. {
  260. unsigned int i;
  261. i = macb->rx_tail;
  262. macb_invalidate_ring_desc(macb, RX);
  263. while (i > new_tail) {
  264. macb->rx_ring[i].addr &= ~RXADDR_USED;
  265. i++;
  266. if (i > MACB_RX_RING_SIZE)
  267. i = 0;
  268. }
  269. while (i < new_tail) {
  270. macb->rx_ring[i].addr &= ~RXADDR_USED;
  271. i++;
  272. }
  273. barrier();
  274. macb_flush_ring_desc(macb, RX);
  275. macb->rx_tail = new_tail;
  276. }
  277. static int macb_recv(struct eth_device *netdev)
  278. {
  279. struct macb_device *macb = to_macb(netdev);
  280. unsigned int rx_tail = macb->rx_tail;
  281. void *buffer;
  282. int length;
  283. int wrapped = 0;
  284. u32 status;
  285. for (;;) {
  286. macb_invalidate_ring_desc(macb, RX);
  287. if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
  288. return -1;
  289. status = macb->rx_ring[rx_tail].ctrl;
  290. if (status & RXBUF_FRAME_START) {
  291. if (rx_tail != macb->rx_tail)
  292. reclaim_rx_buffers(macb, rx_tail);
  293. wrapped = 0;
  294. }
  295. if (status & RXBUF_FRAME_END) {
  296. buffer = macb->rx_buffer + 128 * macb->rx_tail;
  297. length = status & RXBUF_FRMLEN_MASK;
  298. macb_invalidate_rx_buffer(macb);
  299. if (wrapped) {
  300. unsigned int headlen, taillen;
  301. headlen = 128 * (MACB_RX_RING_SIZE
  302. - macb->rx_tail);
  303. taillen = length - headlen;
  304. memcpy((void *)net_rx_packets[0],
  305. buffer, headlen);
  306. memcpy((void *)net_rx_packets[0] + headlen,
  307. macb->rx_buffer, taillen);
  308. buffer = (void *)net_rx_packets[0];
  309. }
  310. net_process_received_packet(buffer, length);
  311. if (++rx_tail >= MACB_RX_RING_SIZE)
  312. rx_tail = 0;
  313. reclaim_rx_buffers(macb, rx_tail);
  314. } else {
  315. if (++rx_tail >= MACB_RX_RING_SIZE) {
  316. wrapped = 1;
  317. rx_tail = 0;
  318. }
  319. }
  320. barrier();
  321. }
  322. return 0;
  323. }
  324. static void macb_phy_reset(struct macb_device *macb)
  325. {
  326. struct eth_device *netdev = &macb->netdev;
  327. int i;
  328. u16 status, adv;
  329. adv = ADVERTISE_CSMA | ADVERTISE_ALL;
  330. macb_mdio_write(macb, MII_ADVERTISE, adv);
  331. printf("%s: Starting autonegotiation...\n", netdev->name);
  332. macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
  333. | BMCR_ANRESTART));
  334. for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
  335. status = macb_mdio_read(macb, MII_BMSR);
  336. if (status & BMSR_ANEGCOMPLETE)
  337. break;
  338. udelay(100);
  339. }
  340. if (status & BMSR_ANEGCOMPLETE)
  341. printf("%s: Autonegotiation complete\n", netdev->name);
  342. else
  343. printf("%s: Autonegotiation timed out (status=0x%04x)\n",
  344. netdev->name, status);
  345. }
  346. #ifdef CONFIG_MACB_SEARCH_PHY
  347. static int macb_phy_find(struct macb_device *macb)
  348. {
  349. int i;
  350. u16 phy_id;
  351. /* Search for PHY... */
  352. for (i = 0; i < 32; i++) {
  353. macb->phy_addr = i;
  354. phy_id = macb_mdio_read(macb, MII_PHYSID1);
  355. if (phy_id != 0xffff) {
  356. printf("%s: PHY present at %d\n", macb->netdev.name, i);
  357. return 1;
  358. }
  359. }
  360. /* PHY isn't up to snuff */
  361. printf("%s: PHY not found\n", macb->netdev.name);
  362. return 0;
  363. }
  364. #endif /* CONFIG_MACB_SEARCH_PHY */
  365. static int macb_phy_init(struct macb_device *macb)
  366. {
  367. struct eth_device *netdev = &macb->netdev;
  368. #ifdef CONFIG_PHYLIB
  369. struct phy_device *phydev;
  370. #endif
  371. u32 ncfgr;
  372. u16 phy_id, status, adv, lpa;
  373. int media, speed, duplex;
  374. int i;
  375. arch_get_mdio_control(netdev->name);
  376. #ifdef CONFIG_MACB_SEARCH_PHY
  377. /* Auto-detect phy_addr */
  378. if (!macb_phy_find(macb))
  379. return 0;
  380. #endif /* CONFIG_MACB_SEARCH_PHY */
  381. /* Check if the PHY is up to snuff... */
  382. phy_id = macb_mdio_read(macb, MII_PHYSID1);
  383. if (phy_id == 0xffff) {
  384. printf("%s: No PHY present\n", netdev->name);
  385. return 0;
  386. }
  387. #ifdef CONFIG_PHYLIB
  388. /* need to consider other phy interface mode */
  389. phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
  390. PHY_INTERFACE_MODE_RGMII);
  391. if (!phydev) {
  392. printf("phy_connect failed\n");
  393. return -ENODEV;
  394. }
  395. phy_config(phydev);
  396. #endif
  397. status = macb_mdio_read(macb, MII_BMSR);
  398. if (!(status & BMSR_LSTATUS)) {
  399. /* Try to re-negotiate if we don't have link already. */
  400. macb_phy_reset(macb);
  401. for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
  402. status = macb_mdio_read(macb, MII_BMSR);
  403. if (status & BMSR_LSTATUS)
  404. break;
  405. udelay(100);
  406. }
  407. }
  408. if (!(status & BMSR_LSTATUS)) {
  409. printf("%s: link down (status: 0x%04x)\n",
  410. netdev->name, status);
  411. return 0;
  412. }
  413. /* First check for GMAC and that it is GiB capable */
  414. if (gem_is_gigabit_capable(macb)) {
  415. lpa = macb_mdio_read(macb, MII_STAT1000);
  416. if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
  417. duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
  418. printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
  419. netdev->name,
  420. duplex ? "full" : "half",
  421. lpa);
  422. ncfgr = macb_readl(macb, NCFGR);
  423. ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  424. ncfgr |= GEM_BIT(GBE);
  425. if (duplex)
  426. ncfgr |= MACB_BIT(FD);
  427. macb_writel(macb, NCFGR, ncfgr);
  428. return 1;
  429. }
  430. }
  431. /* fall back for EMAC checking */
  432. adv = macb_mdio_read(macb, MII_ADVERTISE);
  433. lpa = macb_mdio_read(macb, MII_LPA);
  434. media = mii_nway_result(lpa & adv);
  435. speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  436. ? 1 : 0);
  437. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  438. printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
  439. netdev->name,
  440. speed ? "100" : "10",
  441. duplex ? "full" : "half",
  442. lpa);
  443. ncfgr = macb_readl(macb, NCFGR);
  444. ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
  445. if (speed)
  446. ncfgr |= MACB_BIT(SPD);
  447. if (duplex)
  448. ncfgr |= MACB_BIT(FD);
  449. macb_writel(macb, NCFGR, ncfgr);
  450. return 1;
  451. }
  452. static int gmac_init_multi_queues(struct macb_device *macb)
  453. {
  454. int i, num_queues = 1;
  455. u32 queue_mask;
  456. /* bit 0 is never set but queue 0 always exists */
  457. queue_mask = gem_readl(macb, DCFG6) & 0xff;
  458. queue_mask |= 0x1;
  459. for (i = 1; i < MACB_MAX_QUEUES; i++)
  460. if (queue_mask & (1 << i))
  461. num_queues++;
  462. macb->dummy_desc->ctrl = TXBUF_USED;
  463. macb->dummy_desc->addr = 0;
  464. flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
  465. MACB_TX_DUMMY_DMA_DESC_SIZE);
  466. for (i = 1; i < num_queues; i++)
  467. gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
  468. return 0;
  469. }
  470. static int macb_init(struct eth_device *netdev, bd_t *bd)
  471. {
  472. struct macb_device *macb = to_macb(netdev);
  473. unsigned long paddr;
  474. int i;
  475. /*
  476. * macb_halt should have been called at some point before now,
  477. * so we'll assume the controller is idle.
  478. */
  479. /* initialize DMA descriptors */
  480. paddr = macb->rx_buffer_dma;
  481. for (i = 0; i < MACB_RX_RING_SIZE; i++) {
  482. if (i == (MACB_RX_RING_SIZE - 1))
  483. paddr |= RXADDR_WRAP;
  484. macb->rx_ring[i].addr = paddr;
  485. macb->rx_ring[i].ctrl = 0;
  486. paddr += 128;
  487. }
  488. macb_flush_ring_desc(macb, RX);
  489. macb_flush_rx_buffer(macb);
  490. for (i = 0; i < MACB_TX_RING_SIZE; i++) {
  491. macb->tx_ring[i].addr = 0;
  492. if (i == (MACB_TX_RING_SIZE - 1))
  493. macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
  494. else
  495. macb->tx_ring[i].ctrl = TXBUF_USED;
  496. }
  497. macb_flush_ring_desc(macb, TX);
  498. macb->rx_tail = 0;
  499. macb->tx_head = 0;
  500. macb->tx_tail = 0;
  501. macb_writel(macb, RBQP, macb->rx_ring_dma);
  502. macb_writel(macb, TBQP, macb->tx_ring_dma);
  503. if (macb_is_gem(macb)) {
  504. /* Check the multi queue and initialize the queue for tx */
  505. gmac_init_multi_queues(macb);
  506. /*
  507. * When the GMAC IP with GE feature, this bit is used to
  508. * select interface between RGMII and GMII.
  509. * When the GMAC IP without GE feature, this bit is used
  510. * to select interface between RMII and MII.
  511. */
  512. #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
  513. gem_writel(macb, UR, GEM_BIT(RGMII));
  514. #else
  515. gem_writel(macb, UR, 0);
  516. #endif
  517. } else {
  518. /* choose RMII or MII mode. This depends on the board */
  519. #ifdef CONFIG_RMII
  520. #ifdef CONFIG_AT91FAMILY
  521. macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
  522. #else
  523. macb_writel(macb, USRIO, 0);
  524. #endif
  525. #else
  526. #ifdef CONFIG_AT91FAMILY
  527. macb_writel(macb, USRIO, MACB_BIT(CLKEN));
  528. #else
  529. macb_writel(macb, USRIO, MACB_BIT(MII));
  530. #endif
  531. #endif /* CONFIG_RMII */
  532. }
  533. if (!macb_phy_init(macb))
  534. return -1;
  535. /* Enable TX and RX */
  536. macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
  537. return 0;
  538. }
  539. static void macb_halt(struct eth_device *netdev)
  540. {
  541. struct macb_device *macb = to_macb(netdev);
  542. u32 ncr, tsr;
  543. /* Halt the controller and wait for any ongoing transmission to end. */
  544. ncr = macb_readl(macb, NCR);
  545. ncr |= MACB_BIT(THALT);
  546. macb_writel(macb, NCR, ncr);
  547. do {
  548. tsr = macb_readl(macb, TSR);
  549. } while (tsr & MACB_BIT(TGO));
  550. /* Disable TX and RX, and clear statistics */
  551. macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
  552. }
  553. static int macb_write_hwaddr(struct eth_device *dev)
  554. {
  555. struct macb_device *macb = to_macb(dev);
  556. u32 hwaddr_bottom;
  557. u16 hwaddr_top;
  558. /* set hardware address */
  559. hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
  560. dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
  561. macb_writel(macb, SA1B, hwaddr_bottom);
  562. hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
  563. macb_writel(macb, SA1T, hwaddr_top);
  564. return 0;
  565. }
  566. static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
  567. {
  568. u32 config;
  569. unsigned long macb_hz = get_macb_pclk_rate(id);
  570. if (macb_hz < 20000000)
  571. config = MACB_BF(CLK, MACB_CLK_DIV8);
  572. else if (macb_hz < 40000000)
  573. config = MACB_BF(CLK, MACB_CLK_DIV16);
  574. else if (macb_hz < 80000000)
  575. config = MACB_BF(CLK, MACB_CLK_DIV32);
  576. else
  577. config = MACB_BF(CLK, MACB_CLK_DIV64);
  578. return config;
  579. }
  580. static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
  581. {
  582. u32 config;
  583. unsigned long macb_hz = get_macb_pclk_rate(id);
  584. if (macb_hz < 20000000)
  585. config = GEM_BF(CLK, GEM_CLK_DIV8);
  586. else if (macb_hz < 40000000)
  587. config = GEM_BF(CLK, GEM_CLK_DIV16);
  588. else if (macb_hz < 80000000)
  589. config = GEM_BF(CLK, GEM_CLK_DIV32);
  590. else if (macb_hz < 120000000)
  591. config = GEM_BF(CLK, GEM_CLK_DIV48);
  592. else if (macb_hz < 160000000)
  593. config = GEM_BF(CLK, GEM_CLK_DIV64);
  594. else
  595. config = GEM_BF(CLK, GEM_CLK_DIV96);
  596. return config;
  597. }
  598. /*
  599. * Get the DMA bus width field of the network configuration register that we
  600. * should program. We find the width from decoding the design configuration
  601. * register to find the maximum supported data bus width.
  602. */
  603. static u32 macb_dbw(struct macb_device *macb)
  604. {
  605. switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
  606. case 4:
  607. return GEM_BF(DBW, GEM_DBW128);
  608. case 2:
  609. return GEM_BF(DBW, GEM_DBW64);
  610. case 1:
  611. default:
  612. return GEM_BF(DBW, GEM_DBW32);
  613. }
  614. }
  615. int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
  616. {
  617. struct macb_device *macb;
  618. struct eth_device *netdev;
  619. u32 ncfgr;
  620. macb = malloc(sizeof(struct macb_device));
  621. if (!macb) {
  622. printf("Error: Failed to allocate memory for MACB%d\n", id);
  623. return -1;
  624. }
  625. memset(macb, 0, sizeof(struct macb_device));
  626. netdev = &macb->netdev;
  627. macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
  628. &macb->rx_buffer_dma);
  629. macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
  630. &macb->rx_ring_dma);
  631. macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
  632. &macb->tx_ring_dma);
  633. macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
  634. &macb->dummy_desc_dma);
  635. /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
  636. macb->regs = regs;
  637. macb->phy_addr = phy_addr;
  638. if (macb_is_gem(macb))
  639. sprintf(netdev->name, "gmac%d", id);
  640. else
  641. sprintf(netdev->name, "macb%d", id);
  642. netdev->init = macb_init;
  643. netdev->halt = macb_halt;
  644. netdev->send = macb_send;
  645. netdev->recv = macb_recv;
  646. netdev->write_hwaddr = macb_write_hwaddr;
  647. /*
  648. * Do some basic initialization so that we at least can talk
  649. * to the PHY
  650. */
  651. if (macb_is_gem(macb)) {
  652. ncfgr = gem_mdc_clk_div(id, macb);
  653. ncfgr |= macb_dbw(macb);
  654. } else {
  655. ncfgr = macb_mdc_clk_div(id, macb);
  656. }
  657. macb_writel(macb, NCFGR, ncfgr);
  658. eth_register(netdev);
  659. #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
  660. miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
  661. macb->bus = miiphy_get_dev_by_name(netdev->name);
  662. #endif
  663. return 0;
  664. }
  665. #endif