denali_spd_ddr2.c 39 KB

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  1. /*
  2. * arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
  3. * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
  4. * DDR2 controller, specifically the 440EPx/GRx.
  5. *
  6. * (C) Copyright 2007-2008
  7. * Larry Johnson, lrj@acm.org.
  8. *
  9. * Based primarily on arch/powerpc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
  10. *
  11. * (C) Copyright 2007
  12. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13. *
  14. * COPYRIGHT AMCC CORPORATION 2004
  15. *
  16. * SPDX-License-Identifier: GPL-2.0+
  17. */
  18. /* define DEBUG for debugging output (obviously ;-)) */
  19. #if 0
  20. #define DEBUG
  21. #endif
  22. #include <common.h>
  23. #include <command.h>
  24. #include <asm/ppc4xx.h>
  25. #include <i2c.h>
  26. #include <asm/io.h>
  27. #include <asm/processor.h>
  28. #include <asm/mmu.h>
  29. #include <asm/cache.h>
  30. #if defined(CONFIG_SPD_EEPROM) && \
  31. (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
  32. /*-----------------------------------------------------------------------------+
  33. * Defines
  34. *-----------------------------------------------------------------------------*/
  35. #define MAXDIMMS 2
  36. #define MAXRANKS 2
  37. #define ONE_BILLION 1000000000
  38. #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  39. #define DLL_DQS_DELAY 0x19
  40. #define DLL_DQS_BYPASS 0x0B
  41. #define DQS_OUT_SHIFT 0x7F
  42. /*
  43. * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  44. * region. Right now the cache should still be disabled in U-Boot because of the
  45. * EMAC driver, that need it's buffer descriptor to be located in non cached
  46. * memory.
  47. *
  48. * If at some time this restriction doesn't apply anymore, just define
  49. * CONFIG_4xx_DCACHE in the board config file and this code should setup
  50. * everything correctly.
  51. */
  52. #if defined(CONFIG_4xx_DCACHE)
  53. #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
  54. #else
  55. #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
  56. #endif
  57. /*-----------------------------------------------------------------------------+
  58. * Prototypes
  59. *-----------------------------------------------------------------------------*/
  60. extern int denali_wait_for_dlllock(void);
  61. extern void denali_core_search_data_eye(void);
  62. extern void dcbz_area(u32 start_address, u32 num_bytes);
  63. /*
  64. * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  65. */
  66. void __spd_ddr_init_hang(void)
  67. {
  68. hang();
  69. }
  70. void spd_ddr_init_hang(void)
  71. __attribute__ ((weak, alias("__spd_ddr_init_hang")));
  72. #if defined(DEBUG)
  73. static void print_mcsr(void)
  74. {
  75. printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR));
  76. }
  77. static void denali_sdram_register_dump(void)
  78. {
  79. unsigned int sdram_data;
  80. printf("\n Register Dump:\n");
  81. mfsdram(DDR0_00, sdram_data);
  82. printf(" DDR0_00 = 0x%08X", sdram_data);
  83. mfsdram(DDR0_01, sdram_data);
  84. printf(" DDR0_01 = 0x%08X\n", sdram_data);
  85. mfsdram(DDR0_02, sdram_data);
  86. printf(" DDR0_02 = 0x%08X", sdram_data);
  87. mfsdram(DDR0_03, sdram_data);
  88. printf(" DDR0_03 = 0x%08X\n", sdram_data);
  89. mfsdram(DDR0_04, sdram_data);
  90. printf(" DDR0_04 = 0x%08X", sdram_data);
  91. mfsdram(DDR0_05, sdram_data);
  92. printf(" DDR0_05 = 0x%08X\n", sdram_data);
  93. mfsdram(DDR0_06, sdram_data);
  94. printf(" DDR0_06 = 0x%08X", sdram_data);
  95. mfsdram(DDR0_07, sdram_data);
  96. printf(" DDR0_07 = 0x%08X\n", sdram_data);
  97. mfsdram(DDR0_08, sdram_data);
  98. printf(" DDR0_08 = 0x%08X", sdram_data);
  99. mfsdram(DDR0_09, sdram_data);
  100. printf(" DDR0_09 = 0x%08X\n", sdram_data);
  101. mfsdram(DDR0_10, sdram_data);
  102. printf(" DDR0_10 = 0x%08X", sdram_data);
  103. mfsdram(DDR0_11, sdram_data);
  104. printf(" DDR0_11 = 0x%08X\n", sdram_data);
  105. mfsdram(DDR0_12, sdram_data);
  106. printf(" DDR0_12 = 0x%08X", sdram_data);
  107. mfsdram(DDR0_14, sdram_data);
  108. printf(" DDR0_14 = 0x%08X\n", sdram_data);
  109. mfsdram(DDR0_17, sdram_data);
  110. printf(" DDR0_17 = 0x%08X", sdram_data);
  111. mfsdram(DDR0_18, sdram_data);
  112. printf(" DDR0_18 = 0x%08X\n", sdram_data);
  113. mfsdram(DDR0_19, sdram_data);
  114. printf(" DDR0_19 = 0x%08X", sdram_data);
  115. mfsdram(DDR0_20, sdram_data);
  116. printf(" DDR0_20 = 0x%08X\n", sdram_data);
  117. mfsdram(DDR0_21, sdram_data);
  118. printf(" DDR0_21 = 0x%08X", sdram_data);
  119. mfsdram(DDR0_22, sdram_data);
  120. printf(" DDR0_22 = 0x%08X\n", sdram_data);
  121. mfsdram(DDR0_23, sdram_data);
  122. printf(" DDR0_23 = 0x%08X", sdram_data);
  123. mfsdram(DDR0_24, sdram_data);
  124. printf(" DDR0_24 = 0x%08X\n", sdram_data);
  125. mfsdram(DDR0_25, sdram_data);
  126. printf(" DDR0_25 = 0x%08X", sdram_data);
  127. mfsdram(DDR0_26, sdram_data);
  128. printf(" DDR0_26 = 0x%08X\n", sdram_data);
  129. mfsdram(DDR0_27, sdram_data);
  130. printf(" DDR0_27 = 0x%08X", sdram_data);
  131. mfsdram(DDR0_28, sdram_data);
  132. printf(" DDR0_28 = 0x%08X\n", sdram_data);
  133. mfsdram(DDR0_31, sdram_data);
  134. printf(" DDR0_31 = 0x%08X", sdram_data);
  135. mfsdram(DDR0_32, sdram_data);
  136. printf(" DDR0_32 = 0x%08X\n", sdram_data);
  137. mfsdram(DDR0_33, sdram_data);
  138. printf(" DDR0_33 = 0x%08X", sdram_data);
  139. mfsdram(DDR0_34, sdram_data);
  140. printf(" DDR0_34 = 0x%08X\n", sdram_data);
  141. mfsdram(DDR0_35, sdram_data);
  142. printf(" DDR0_35 = 0x%08X", sdram_data);
  143. mfsdram(DDR0_36, sdram_data);
  144. printf(" DDR0_36 = 0x%08X\n", sdram_data);
  145. mfsdram(DDR0_37, sdram_data);
  146. printf(" DDR0_37 = 0x%08X", sdram_data);
  147. mfsdram(DDR0_38, sdram_data);
  148. printf(" DDR0_38 = 0x%08X\n", sdram_data);
  149. mfsdram(DDR0_39, sdram_data);
  150. printf(" DDR0_39 = 0x%08X", sdram_data);
  151. mfsdram(DDR0_40, sdram_data);
  152. printf(" DDR0_40 = 0x%08X\n", sdram_data);
  153. mfsdram(DDR0_41, sdram_data);
  154. printf(" DDR0_41 = 0x%08X", sdram_data);
  155. mfsdram(DDR0_42, sdram_data);
  156. printf(" DDR0_42 = 0x%08X\n", sdram_data);
  157. mfsdram(DDR0_43, sdram_data);
  158. printf(" DDR0_43 = 0x%08X", sdram_data);
  159. mfsdram(DDR0_44, sdram_data);
  160. printf(" DDR0_44 = 0x%08X\n", sdram_data);
  161. }
  162. #else
  163. static inline void denali_sdram_register_dump(void)
  164. {
  165. }
  166. inline static void print_mcsr(void)
  167. {
  168. }
  169. #endif /* defined(DEBUG) */
  170. static int is_ecc_enabled(void)
  171. {
  172. u32 val;
  173. mfsdram(DDR0_22, val);
  174. return 0x3 == DDR0_22_CTRL_RAW_DECODE(val);
  175. }
  176. static unsigned char spd_read(u8 chip, unsigned int addr)
  177. {
  178. u8 data[2];
  179. if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) {
  180. debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr);
  181. return 0;
  182. }
  183. debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n",
  184. chip, addr, data[0]);
  185. return data[0];
  186. }
  187. static unsigned long get_tcyc(unsigned char reg)
  188. {
  189. /*
  190. * Byte 9, et al: Cycle time for CAS Latency=X, is split into two
  191. * nibbles: the higher order nibble (bits 4-7) designates the cycle time
  192. * to a granularity of 1ns; the value presented by the lower order
  193. * nibble (bits 0-3) has a granularity of .1ns and is added to the value
  194. * designated by the higher nibble. In addition, four lines of the lower
  195. * order nibble are assigned to support +.25, +.33, +.66, and +.75.
  196. */
  197. unsigned char subfield_b = reg & 0x0F;
  198. switch (subfield_b & 0x0F) {
  199. case 0x0:
  200. case 0x1:
  201. case 0x2:
  202. case 0x3:
  203. case 0x4:
  204. case 0x5:
  205. case 0x6:
  206. case 0x7:
  207. case 0x8:
  208. case 0x9:
  209. return 1000 * (reg >> 4) + 100 * subfield_b;
  210. case 0xA:
  211. return 1000 * (reg >> 4) + 250;
  212. case 0xB:
  213. return 1000 * (reg >> 4) + 333;
  214. case 0xC:
  215. return 1000 * (reg >> 4) + 667;
  216. case 0xD:
  217. return 1000 * (reg >> 4) + 750;
  218. }
  219. return 0;
  220. }
  221. /*------------------------------------------------------------------
  222. * Find the installed DIMMs, make sure that the are DDR2, and fill
  223. * in the dimm_ranks array. Then dimm_ranks[dimm_num] > 0 iff the
  224. * DIMM and dimm_num is present.
  225. * Note: Because there are only two chip-select lines, it is assumed
  226. * that a board with a single socket can support two ranks on that
  227. * socket, while a board with two sockets can support only one rank
  228. * on each socket.
  229. *-----------------------------------------------------------------*/
  230. static void get_spd_info(unsigned long dimm_ranks[],
  231. unsigned long *ranks,
  232. unsigned char const iic0_dimm_addr[],
  233. unsigned long num_dimm_banks)
  234. {
  235. unsigned long dimm_num;
  236. unsigned long dimm_found = false;
  237. unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
  238. unsigned char num_of_bytes;
  239. unsigned char total_size;
  240. *ranks = 0;
  241. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  242. num_of_bytes = 0;
  243. total_size = 0;
  244. num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
  245. total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
  246. if ((num_of_bytes != 0) && (total_size != 0)) {
  247. unsigned char const dimm_type =
  248. spd_read(iic0_dimm_addr[dimm_num], 2);
  249. unsigned long ranks_on_dimm =
  250. (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1;
  251. if (8 != dimm_type) {
  252. switch (dimm_type) {
  253. case 1:
  254. printf("ERROR: Standard Fast Page Mode "
  255. "DRAM DIMM");
  256. break;
  257. case 2:
  258. printf("ERROR: EDO DIMM");
  259. break;
  260. case 3:
  261. printf("ERROR: Pipelined Nibble DIMM");
  262. break;
  263. case 4:
  264. printf("ERROR: SDRAM DIMM");
  265. break;
  266. case 5:
  267. printf("ERROR: Multiplexed ROM DIMM");
  268. break;
  269. case 6:
  270. printf("ERROR: SGRAM DIMM");
  271. break;
  272. case 7:
  273. printf("ERROR: DDR1 DIMM");
  274. break;
  275. default:
  276. printf("ERROR: Unknown DIMM (type %d)",
  277. (unsigned int)dimm_type);
  278. break;
  279. }
  280. printf(" detected in slot %lu.\n", dimm_num);
  281. printf("Only DDR2 SDRAM DIMMs are supported."
  282. "\n");
  283. printf("Replace the module with a DDR2 DIMM."
  284. "\n\n");
  285. spd_ddr_init_hang();
  286. }
  287. dimm_found = true;
  288. debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
  289. "\n", dimm_num, ranks_on_dimm);
  290. if (ranks_on_dimm > max_ranks_per_dimm) {
  291. printf("WARNING: DRAM DIMM in slot %lu has %lu "
  292. "ranks.\n", dimm_num, ranks_on_dimm);
  293. if (1 == max_ranks_per_dimm) {
  294. printf("Only one rank will be used.\n");
  295. } else {
  296. printf
  297. ("Only two ranks will be used.\n");
  298. }
  299. ranks_on_dimm = max_ranks_per_dimm;
  300. }
  301. dimm_ranks[dimm_num] = ranks_on_dimm;
  302. *ranks += ranks_on_dimm;
  303. } else {
  304. dimm_ranks[dimm_num] = 0;
  305. debug("DIMM slot %lu: Not populated\n", dimm_num);
  306. }
  307. }
  308. if (dimm_found == false) {
  309. printf("ERROR: No memory installed.\n");
  310. printf("Install at least one DDR2 DIMM.\n\n");
  311. spd_ddr_init_hang();
  312. }
  313. debug("Total number of ranks = %ld\n", *ranks);
  314. }
  315. /*------------------------------------------------------------------
  316. * For the memory DIMMs installed, this routine verifies that
  317. * frequency previously calculated is supported.
  318. *-----------------------------------------------------------------*/
  319. static void check_frequency(unsigned long *dimm_ranks,
  320. unsigned char const iic0_dimm_addr[],
  321. unsigned long num_dimm_banks,
  322. unsigned long sdram_freq)
  323. {
  324. unsigned long dimm_num;
  325. unsigned long cycle_time;
  326. unsigned long calc_cycle_time;
  327. /*
  328. * calc_cycle_time is calculated from DDR frequency set by board/chip
  329. * and is expressed in picoseconds to match the way DIMM cycle time is
  330. * calculated below.
  331. */
  332. calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq);
  333. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  334. if (dimm_ranks[dimm_num]) {
  335. cycle_time =
  336. get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
  337. debug("cycle_time=%ld ps\n", cycle_time);
  338. if (cycle_time > (calc_cycle_time + 10)) {
  339. /*
  340. * the provided sdram cycle_time is too small
  341. * for the available DIMM cycle_time. The
  342. * additionnal 10ps is here to accept a small
  343. * incertainty.
  344. */
  345. printf
  346. ("ERROR: DRAM DIMM detected with cycle_time %d ps in "
  347. "slot %d \n while calculated cycle time is %d ps.\n",
  348. (unsigned int)cycle_time,
  349. (unsigned int)dimm_num,
  350. (unsigned int)calc_cycle_time);
  351. printf
  352. ("Replace the DIMM, or change DDR frequency via "
  353. "strapping bits.\n\n");
  354. spd_ddr_init_hang();
  355. }
  356. }
  357. }
  358. }
  359. /*------------------------------------------------------------------
  360. * This routine gets size information for the installed memory
  361. * DIMMs.
  362. *-----------------------------------------------------------------*/
  363. static void get_dimm_size(unsigned long dimm_ranks[],
  364. unsigned char const iic0_dimm_addr[],
  365. unsigned long num_dimm_banks,
  366. unsigned long *const rows,
  367. unsigned long *const banks,
  368. unsigned long *const cols, unsigned long *const width)
  369. {
  370. unsigned long dimm_num;
  371. *rows = 0;
  372. *banks = 0;
  373. *cols = 0;
  374. *width = 0;
  375. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  376. if (dimm_ranks[dimm_num]) {
  377. unsigned long t;
  378. /* Rows */
  379. t = spd_read(iic0_dimm_addr[dimm_num], 3);
  380. if (0 == *rows) {
  381. *rows = t;
  382. } else if (t != *rows) {
  383. printf("ERROR: DRAM DIMM modules do not all "
  384. "have the same number of rows.\n\n");
  385. spd_ddr_init_hang();
  386. }
  387. /* Banks */
  388. t = spd_read(iic0_dimm_addr[dimm_num], 17);
  389. if (0 == *banks) {
  390. *banks = t;
  391. } else if (t != *banks) {
  392. printf("ERROR: DRAM DIMM modules do not all "
  393. "have the same number of banks.\n\n");
  394. spd_ddr_init_hang();
  395. }
  396. /* Columns */
  397. t = spd_read(iic0_dimm_addr[dimm_num], 4);
  398. if (0 == *cols) {
  399. *cols = t;
  400. } else if (t != *cols) {
  401. printf("ERROR: DRAM DIMM modules do not all "
  402. "have the same number of columns.\n\n");
  403. spd_ddr_init_hang();
  404. }
  405. /* Data width */
  406. t = spd_read(iic0_dimm_addr[dimm_num], 6);
  407. if (0 == *width) {
  408. *width = t;
  409. } else if (t != *width) {
  410. printf("ERROR: DRAM DIMM modules do not all "
  411. "have the same data width.\n\n");
  412. spd_ddr_init_hang();
  413. }
  414. }
  415. }
  416. debug("Number of rows = %ld\n", *rows);
  417. debug("Number of columns = %ld\n", *cols);
  418. debug("Number of banks = %ld\n", *banks);
  419. debug("Data width = %ld\n", *width);
  420. if (*rows > 14) {
  421. printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
  422. *rows);
  423. printf("Only modules with 14 or fewer rows are supported.\n\n");
  424. spd_ddr_init_hang();
  425. }
  426. if (4 != *banks && 8 != *banks) {
  427. printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks);
  428. printf("Only modules with 4 or 8 banks are supported.\n\n");
  429. spd_ddr_init_hang();
  430. }
  431. if (*cols > 12) {
  432. printf("ERROR: DRAM DIMM modules have %lu address columns.\n",
  433. *cols);
  434. printf("Only modules with 12 or fewer columns are "
  435. "supported.\n\n");
  436. spd_ddr_init_hang();
  437. }
  438. if (32 != *width && 40 != *width && 64 != *width && 72 != *width) {
  439. printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n",
  440. *width);
  441. printf("Only modules with widths of 32, 40, 64, and 72 bits "
  442. "are supported.\n\n");
  443. spd_ddr_init_hang();
  444. }
  445. }
  446. /*------------------------------------------------------------------
  447. * Only 1.8V modules are supported. This routine verifies this.
  448. *-----------------------------------------------------------------*/
  449. static void check_voltage_type(unsigned long dimm_ranks[],
  450. unsigned char const iic0_dimm_addr[],
  451. unsigned long num_dimm_banks)
  452. {
  453. unsigned long dimm_num;
  454. unsigned long voltage_type;
  455. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  456. if (dimm_ranks[dimm_num]) {
  457. voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
  458. if (0x05 != voltage_type) { /* 1.8V for DDR2 */
  459. printf("ERROR: Slot %lu provides 1.8V for DDR2 "
  460. "DIMMs.\n", dimm_num);
  461. switch (voltage_type) {
  462. case 0x00:
  463. printf("This DIMM is 5.0 Volt/TTL.\n");
  464. break;
  465. case 0x01:
  466. printf("This DIMM is LVTTL.\n");
  467. break;
  468. case 0x02:
  469. printf("This DIMM is 1.5 Volt.\n");
  470. break;
  471. case 0x03:
  472. printf("This DIMM is 3.3 Volt/TTL.\n");
  473. break;
  474. case 0x04:
  475. printf("This DIMM is 2.5 Volt.\n");
  476. break;
  477. default:
  478. printf("This DIMM is an unknown "
  479. "voltage.\n");
  480. break;
  481. }
  482. printf("Replace it with a 1.8V DDR2 DIMM.\n\n");
  483. spd_ddr_init_hang();
  484. }
  485. }
  486. }
  487. }
  488. static void program_ddr0_03(unsigned long dimm_ranks[],
  489. unsigned char const iic0_dimm_addr[],
  490. unsigned long num_dimm_banks,
  491. unsigned long sdram_freq,
  492. unsigned long rows, unsigned long *cas_latency)
  493. {
  494. unsigned long dimm_num;
  495. unsigned long cas_index;
  496. unsigned long cycle_2_0_clk;
  497. unsigned long cycle_3_0_clk;
  498. unsigned long cycle_4_0_clk;
  499. unsigned long cycle_5_0_clk;
  500. unsigned long max_2_0_tcyc_ps = 100;
  501. unsigned long max_3_0_tcyc_ps = 100;
  502. unsigned long max_4_0_tcyc_ps = 100;
  503. unsigned long max_5_0_tcyc_ps = 100;
  504. unsigned char cas_available = 0x3C; /* value for DDR2 */
  505. u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2);
  506. unsigned int const tcyc_addr[3] = { 9, 23, 25 };
  507. /*------------------------------------------------------------------
  508. * Get the board configuration info.
  509. *-----------------------------------------------------------------*/
  510. debug("sdram_freq = %ld\n", sdram_freq);
  511. /*------------------------------------------------------------------
  512. * Handle the timing. We need to find the worst case timing of all
  513. * the dimm modules installed.
  514. *-----------------------------------------------------------------*/
  515. /* loop through all the DIMM slots on the board */
  516. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  517. /* If a dimm is installed in a particular slot ... */
  518. if (dimm_ranks[dimm_num]) {
  519. unsigned char const cas_bit =
  520. spd_read(iic0_dimm_addr[dimm_num], 18);
  521. unsigned char cas_mask;
  522. cas_available &= cas_bit;
  523. for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) {
  524. if (cas_bit & cas_mask)
  525. break;
  526. }
  527. debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n",
  528. cas_bit, cas_mask);
  529. for (cas_index = 0; cas_index < 3;
  530. cas_mask >>= 1, cas_index++) {
  531. unsigned long cycle_time_ps;
  532. if (!(cas_available & cas_mask)) {
  533. continue;
  534. }
  535. cycle_time_ps =
  536. get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
  537. tcyc_addr[cas_index]));
  538. debug("cas_index = %ld: cycle_time_ps = %ld\n",
  539. cas_index, cycle_time_ps);
  540. /*
  541. * DDR2 devices use the following bitmask for CAS latency:
  542. * Bit 7 6 5 4 3 2 1 0
  543. * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
  544. */
  545. switch (cas_mask) {
  546. case 0x20:
  547. max_5_0_tcyc_ps =
  548. max(max_5_0_tcyc_ps, cycle_time_ps);
  549. break;
  550. case 0x10:
  551. max_4_0_tcyc_ps =
  552. max(max_4_0_tcyc_ps, cycle_time_ps);
  553. break;
  554. case 0x08:
  555. max_3_0_tcyc_ps =
  556. max(max_3_0_tcyc_ps, cycle_time_ps);
  557. break;
  558. case 0x04:
  559. max_2_0_tcyc_ps =
  560. max(max_2_0_tcyc_ps, cycle_time_ps);
  561. break;
  562. }
  563. }
  564. }
  565. }
  566. debug("cas_available (bit map) = 0x%02X\n", cas_available);
  567. /*------------------------------------------------------------------
  568. * Set the SDRAM mode, SDRAM_MMODE
  569. *-----------------------------------------------------------------*/
  570. /* add 10 here because of rounding problems */
  571. cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10;
  572. cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
  573. cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
  574. cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
  575. debug("cycle_2_0_clk = %ld\n", cycle_2_0_clk);
  576. debug("cycle_3_0_clk = %ld\n", cycle_3_0_clk);
  577. debug("cycle_4_0_clk = %ld\n", cycle_4_0_clk);
  578. debug("cycle_5_0_clk = %ld\n", cycle_5_0_clk);
  579. if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
  580. *cas_latency = 2;
  581. ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) |
  582. DDR0_03_CASLAT_LIN_ENCODE(0x4);
  583. } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) {
  584. *cas_latency = 3;
  585. ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) |
  586. DDR0_03_CASLAT_LIN_ENCODE(0x6);
  587. } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) {
  588. *cas_latency = 4;
  589. ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) |
  590. DDR0_03_CASLAT_LIN_ENCODE(0x8);
  591. } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) {
  592. *cas_latency = 5;
  593. ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) |
  594. DDR0_03_CASLAT_LIN_ENCODE(0xA);
  595. } else {
  596. printf("ERROR: Cannot find a supported CAS latency with the "
  597. "installed DIMMs.\n");
  598. printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, "
  599. "and 5.0 are supported.\n");
  600. printf("Make sure the PLB speed is within the supported range "
  601. "of the DIMMs.\n");
  602. printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld "
  603. "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk,
  604. cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
  605. spd_ddr_init_hang();
  606. }
  607. debug("CAS latency = %ld\n", *cas_latency);
  608. mtsdram(DDR0_03, ddr0_03);
  609. }
  610. static void program_ddr0_04(unsigned long dimm_ranks[],
  611. unsigned char const iic0_dimm_addr[],
  612. unsigned long num_dimm_banks,
  613. unsigned long sdram_freq)
  614. {
  615. unsigned long dimm_num;
  616. unsigned long t_rc_ps = 0;
  617. unsigned long t_rrd_ps = 0;
  618. unsigned long t_rtp_ps = 0;
  619. unsigned long t_rc_clk;
  620. unsigned long t_rrd_clk;
  621. unsigned long t_rtp_clk;
  622. /*------------------------------------------------------------------
  623. * Handle the timing. We need to find the worst case timing of all
  624. * the dimm modules installed.
  625. *-----------------------------------------------------------------*/
  626. /* loop through all the DIMM slots on the board */
  627. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  628. /* If a dimm is installed in a particular slot ... */
  629. if (dimm_ranks[dimm_num]) {
  630. unsigned long ps;
  631. /* tRC */
  632. ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41);
  633. switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) {
  634. case 0x1:
  635. ps += 250;
  636. break;
  637. case 0x2:
  638. ps += 333;
  639. break;
  640. case 0x3:
  641. ps += 500;
  642. break;
  643. case 0x4:
  644. ps += 667;
  645. break;
  646. case 0x5:
  647. ps += 750;
  648. break;
  649. }
  650. t_rc_ps = max(t_rc_ps, ps);
  651. /* tRRD */
  652. ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28);
  653. t_rrd_ps = max(t_rrd_ps, ps);
  654. /* tRTP */
  655. ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38);
  656. t_rtp_ps = max(t_rtp_ps, ps);
  657. }
  658. }
  659. debug("t_rc_ps = %ld\n", t_rc_ps);
  660. t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
  661. debug("t_rrd_ps = %ld\n", t_rrd_ps);
  662. t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
  663. debug("t_rtp_ps = %ld\n", t_rtp_ps);
  664. t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
  665. mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
  666. DDR0_04_TRRD_ENCODE(t_rrd_clk) |
  667. DDR0_04_TRTP_ENCODE(t_rtp_clk));
  668. }
  669. static void program_ddr0_05(unsigned long dimm_ranks[],
  670. unsigned char const iic0_dimm_addr[],
  671. unsigned long num_dimm_banks,
  672. unsigned long sdram_freq)
  673. {
  674. unsigned long dimm_num;
  675. unsigned long t_rp_ps = 0;
  676. unsigned long t_ras_ps = 0;
  677. unsigned long t_rp_clk;
  678. unsigned long t_ras_clk;
  679. u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2);
  680. /*------------------------------------------------------------------
  681. * Handle the timing. We need to find the worst case timing of all
  682. * the dimm modules installed.
  683. *-----------------------------------------------------------------*/
  684. /* loop through all the DIMM slots on the board */
  685. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  686. /* If a dimm is installed in a particular slot ... */
  687. if (dimm_ranks[dimm_num]) {
  688. unsigned long ps;
  689. /* tRP */
  690. ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27);
  691. t_rp_ps = max(t_rp_ps, ps);
  692. /* tRAS */
  693. ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30);
  694. t_ras_ps = max(t_ras_ps, ps);
  695. }
  696. }
  697. debug("t_rp_ps = %ld\n", t_rp_ps);
  698. t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
  699. debug("t_ras_ps = %ld\n", t_ras_ps);
  700. t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
  701. mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
  702. DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
  703. }
  704. static void program_ddr0_06(unsigned long dimm_ranks[],
  705. unsigned char const iic0_dimm_addr[],
  706. unsigned long num_dimm_banks,
  707. unsigned long sdram_freq)
  708. {
  709. unsigned long dimm_num;
  710. unsigned char spd_40;
  711. unsigned long t_wtr_ps = 0;
  712. unsigned long t_rfc_ps = 0;
  713. unsigned long t_wtr_clk;
  714. unsigned long t_rfc_clk;
  715. u32 ddr0_06 =
  716. DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200);
  717. /*------------------------------------------------------------------
  718. * Handle the timing. We need to find the worst case timing of all
  719. * the dimm modules installed.
  720. *-----------------------------------------------------------------*/
  721. /* loop through all the DIMM slots on the board */
  722. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  723. /* If a dimm is installed in a particular slot ... */
  724. if (dimm_ranks[dimm_num]) {
  725. unsigned long ps;
  726. /* tWTR */
  727. ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37);
  728. t_wtr_ps = max(t_wtr_ps, ps);
  729. /* tRFC */
  730. ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42);
  731. spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40);
  732. ps += 256000 * (spd_40 & 0x01);
  733. switch ((spd_40 & 0x0E) >> 1) {
  734. case 0x1:
  735. ps += 250;
  736. break;
  737. case 0x2:
  738. ps += 333;
  739. break;
  740. case 0x3:
  741. ps += 500;
  742. break;
  743. case 0x4:
  744. ps += 667;
  745. break;
  746. case 0x5:
  747. ps += 750;
  748. break;
  749. }
  750. t_rfc_ps = max(t_rfc_ps, ps);
  751. }
  752. }
  753. debug("t_wtr_ps = %ld\n", t_wtr_ps);
  754. t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
  755. debug("t_rfc_ps = %ld\n", t_rfc_ps);
  756. t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
  757. mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
  758. DDR0_06_TRFC_ENCODE(t_rfc_clk));
  759. }
  760. static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks)
  761. {
  762. unsigned long csmap;
  763. if (2 == ranks) {
  764. /* Both chip selects in use */
  765. csmap = 0x03;
  766. } else {
  767. /* One chip select in use */
  768. csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2;
  769. }
  770. mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) |
  771. DDR0_10_CS_MAP_ENCODE(csmap) |
  772. DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0));
  773. }
  774. static void program_ddr0_11(unsigned long sdram_freq)
  775. {
  776. unsigned long const t_xsnr_ps = 200000; /* 200 ns */
  777. unsigned long t_xsnr_clk;
  778. debug("t_xsnr_ps = %ld\n", t_xsnr_ps);
  779. t_xsnr_clk =
  780. (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
  781. mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
  782. DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200));
  783. }
  784. static void program_ddr0_22(unsigned long dimm_ranks[],
  785. unsigned char const iic0_dimm_addr[],
  786. unsigned long num_dimm_banks, unsigned long width)
  787. {
  788. #if defined(CONFIG_DDR_ECC)
  789. unsigned long dimm_num;
  790. unsigned long ecc_available = width >= 64;
  791. u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
  792. DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
  793. DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS);
  794. /* loop through all the DIMM slots on the board */
  795. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  796. /* If a dimm is installed in a particular slot ... */
  797. if (dimm_ranks[dimm_num]) {
  798. /* Check for ECC */
  799. if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
  800. 0x02)) {
  801. ecc_available = false;
  802. }
  803. }
  804. }
  805. if (ecc_available) {
  806. debug("ECC found on all DIMMs present\n");
  807. mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3));
  808. } else {
  809. debug("ECC not found on some or all DIMMs present\n");
  810. mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0));
  811. }
  812. #else
  813. mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) |
  814. DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
  815. DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
  816. DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS));
  817. #endif /* defined(CONFIG_DDR_ECC) */
  818. }
  819. static void program_ddr0_24(unsigned long ranks)
  820. {
  821. u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */
  822. DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0);
  823. if (2 == ranks) {
  824. /* Both chip selects in use */
  825. ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) |
  826. DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2);
  827. } else {
  828. /* One chip select in use */
  829. /* One of the two fields added to ddr0_24 is a "don't care" */
  830. ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) |
  831. DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1);
  832. }
  833. mtsdram(DDR0_24, ddr0_24);
  834. }
  835. static void program_ddr0_26(unsigned long sdram_freq)
  836. {
  837. unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */
  838. /* TODO: check definition of tRAS_MAX */
  839. unsigned long const t_ras_max_ps = 9 * t_ref_ps;
  840. unsigned long t_ras_max_clk;
  841. unsigned long t_ref_clk;
  842. /* Round down t_ras_max_clk and t_ref_clk */
  843. debug("t_ras_max_ps = %ld\n", t_ras_max_ps);
  844. t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
  845. debug("t_ref_ps = %ld\n", t_ref_ps);
  846. t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
  847. mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
  848. DDR0_26_TREF_ENCODE(t_ref_clk));
  849. }
  850. static void program_ddr0_27(unsigned long sdram_freq)
  851. {
  852. unsigned long const t_init_ps = 200000000; /* 200 us. init */
  853. unsigned long t_init_clk;
  854. debug("t_init_ps = %ld\n", t_init_ps);
  855. t_init_clk =
  856. (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
  857. mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
  858. DDR0_27_TINIT_ENCODE(t_init_clk));
  859. }
  860. static void program_ddr0_43(unsigned long dimm_ranks[],
  861. unsigned char const iic0_dimm_addr[],
  862. unsigned long num_dimm_banks,
  863. unsigned long sdram_freq,
  864. unsigned long cols, unsigned long banks)
  865. {
  866. unsigned long dimm_num;
  867. unsigned long t_wr_ps = 0;
  868. unsigned long t_wr_clk;
  869. u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) |
  870. DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) |
  871. DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0);
  872. /*------------------------------------------------------------------
  873. * Handle the timing. We need to find the worst case timing of all
  874. * the dimm modules installed.
  875. *-----------------------------------------------------------------*/
  876. /* loop through all the DIMM slots on the board */
  877. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  878. /* If a dimm is installed in a particular slot ... */
  879. if (dimm_ranks[dimm_num]) {
  880. unsigned long ps;
  881. ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36);
  882. t_wr_ps = max(t_wr_ps, ps);
  883. }
  884. }
  885. debug("t_wr_ps = %ld\n", t_wr_ps);
  886. t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
  887. mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
  888. }
  889. static void program_ddr0_44(unsigned long dimm_ranks[],
  890. unsigned char const iic0_dimm_addr[],
  891. unsigned long num_dimm_banks,
  892. unsigned long sdram_freq)
  893. {
  894. unsigned long dimm_num;
  895. unsigned long t_rcd_ps = 0;
  896. unsigned long t_rcd_clk;
  897. /*------------------------------------------------------------------
  898. * Handle the timing. We need to find the worst case timing of all
  899. * the dimm modules installed.
  900. *-----------------------------------------------------------------*/
  901. /* loop through all the DIMM slots on the board */
  902. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  903. /* If a dimm is installed in a particular slot ... */
  904. if (dimm_ranks[dimm_num]) {
  905. unsigned long ps;
  906. ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29);
  907. t_rcd_ps = max(t_rcd_ps, ps);
  908. }
  909. }
  910. debug("t_rcd_ps = %ld\n", t_rcd_ps);
  911. t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
  912. mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
  913. }
  914. /*-----------------------------------------------------------------------------+
  915. * initdram. Initializes the 440EPx/GPx DDR SDRAM controller.
  916. * Note: This routine runs from flash with a stack set up in the chip's
  917. * sram space. It is important that the routine does not require .sbss, .bss or
  918. * .data sections. It also cannot call routines that require these sections.
  919. *-----------------------------------------------------------------------------*/
  920. /*-----------------------------------------------------------------------------
  921. * Function: initdram
  922. * Description: Configures SDRAM memory banks for DDR operation.
  923. * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  924. * via the IIC bus and then configures the DDR SDRAM memory
  925. * banks appropriately. If Auto Memory Configuration is
  926. * not used, it is assumed that no DIMM is plugged
  927. *-----------------------------------------------------------------------------*/
  928. phys_size_t initdram(int board_type)
  929. {
  930. unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
  931. unsigned long dimm_ranks[MAXDIMMS];
  932. unsigned long ranks;
  933. unsigned long rows;
  934. unsigned long banks;
  935. unsigned long cols;
  936. unsigned long width;
  937. unsigned long const sdram_freq = get_bus_freq(0);
  938. unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */
  939. unsigned long cas_latency = 0; /* to quiet initialization warning */
  940. unsigned long dram_size;
  941. debug("\nEntering initdram()\n");
  942. /*------------------------------------------------------------------
  943. * Stop the DDR-SDRAM controller.
  944. *-----------------------------------------------------------------*/
  945. mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
  946. /*
  947. * Make sure I2C controller is initialized
  948. * before continuing.
  949. */
  950. /* switch to correct I2C bus */
  951. i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  952. /*------------------------------------------------------------------
  953. * Clear out the serial presence detect buffers.
  954. * Perform IIC reads from the dimm. Fill in the spds.
  955. * Check to see if the dimm slots are populated
  956. *-----------------------------------------------------------------*/
  957. get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
  958. /*------------------------------------------------------------------
  959. * Check the frequency supported for the dimms plugged.
  960. *-----------------------------------------------------------------*/
  961. check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
  962. /*------------------------------------------------------------------
  963. * Check and get size information.
  964. *-----------------------------------------------------------------*/
  965. get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
  966. &cols, &width);
  967. /*------------------------------------------------------------------
  968. * Check the voltage type for the dimms plugged.
  969. *-----------------------------------------------------------------*/
  970. check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
  971. /*------------------------------------------------------------------
  972. * Program registers for SDRAM controller.
  973. *-----------------------------------------------------------------*/
  974. mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
  975. DDR0_00_DLL_START_POINT_DECODE(0x0A));
  976. mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
  977. DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
  978. DDR0_01_INT_MASK_ENCODE(0xFF));
  979. program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
  980. rows, &cas_latency);
  981. program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
  982. program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
  983. program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
  984. /*
  985. * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia
  986. * board SDRAM, but may be overly conservative.
  987. */
  988. mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
  989. DDR0_07_TFAW_ENCODE(13) |
  990. DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
  991. DDR0_07_AREFRESH_ENCODE(0));
  992. mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
  993. DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
  994. DDR0_08_DDRII_ENCODE(1));
  995. mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
  996. DDR0_09_RTT_0_ENCODE(0x1) |
  997. DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
  998. DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
  999. program_ddr0_10(dimm_ranks, ranks);
  1000. program_ddr0_11(sdram_freq);
  1001. mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
  1002. mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
  1003. DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
  1004. DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
  1005. mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
  1006. mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
  1007. DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
  1008. DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
  1009. DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
  1010. mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
  1011. DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
  1012. DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
  1013. DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
  1014. mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
  1015. DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
  1016. DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
  1017. DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
  1018. mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
  1019. DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
  1020. DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
  1021. DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
  1022. program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
  1023. mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
  1024. DDR0_23_FWC_ENCODE(0));
  1025. program_ddr0_24(ranks);
  1026. program_ddr0_26(sdram_freq);
  1027. program_ddr0_27(sdram_freq);
  1028. mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
  1029. DDR0_28_EMRS2_DATA_ENCODE(0x0000));
  1030. mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
  1031. mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
  1032. DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
  1033. program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
  1034. cols, banks);
  1035. program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
  1036. denali_sdram_register_dump();
  1037. dram_size = (width >= 64) ? 8 : 4;
  1038. dram_size *= 1 << cols;
  1039. dram_size *= banks;
  1040. dram_size *= 1 << rows;
  1041. dram_size *= ranks;
  1042. debug("dram_size = %lu\n", dram_size);
  1043. /* Start the SDRAM controller */
  1044. mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
  1045. denali_wait_for_dlllock();
  1046. #if defined(CONFIG_DDR_DATA_EYE)
  1047. /*
  1048. * Map the first 1 MiB of memory in the TLB, and perform the data eye
  1049. * search.
  1050. */
  1051. program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
  1052. denali_core_search_data_eye();
  1053. denali_sdram_register_dump();
  1054. remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
  1055. #endif
  1056. #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
  1057. program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
  1058. sync();
  1059. /* Zero the memory */
  1060. debug("Zeroing SDRAM...");
  1061. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  1062. dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
  1063. #else
  1064. #error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
  1065. #endif
  1066. /* Write modified dcache lines back to memory */
  1067. clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
  1068. debug("Completed\n");
  1069. sync();
  1070. remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
  1071. #if defined(CONFIG_DDR_ECC)
  1072. /*
  1073. * If ECC is enabled, clear and enable interrupts
  1074. */
  1075. if (is_ecc_enabled()) {
  1076. u32 val;
  1077. sync();
  1078. /* Clear error status */
  1079. mfsdram(DDR0_00, val);
  1080. mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
  1081. /* Set 'int_mask' parameter to functionnal value */
  1082. mfsdram(DDR0_01, val);
  1083. mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
  1084. DDR0_01_INT_MASK_ALL_OFF);
  1085. #if defined(CONFIG_DDR_DATA_EYE)
  1086. /*
  1087. * Running denali_core_search_data_eye() when ECC is enabled
  1088. * causes non-ECC machine checks. This clears them.
  1089. */
  1090. print_mcsr();
  1091. mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
  1092. print_mcsr();
  1093. #endif
  1094. sync();
  1095. }
  1096. #endif /* defined(CONFIG_DDR_ECC) */
  1097. #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
  1098. program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
  1099. return dram_size;
  1100. }
  1101. void board_add_ram_info(int use_default)
  1102. {
  1103. u32 val;
  1104. printf(" (ECC");
  1105. if (!is_ecc_enabled()) {
  1106. printf(" not");
  1107. }
  1108. printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
  1109. mfsdram(DDR0_03, val);
  1110. printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
  1111. }
  1112. #endif /* CONFIG_SPD_EEPROM */