Kconfig 1.3 KB

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  1. #
  2. # Cache controllers
  3. #
  4. menu "Cache Controller drivers"
  5. config CACHE
  6. bool "Enable Driver Model for Cache controllers"
  7. depends on DM
  8. help
  9. Enable driver model for cache controllers that are found on
  10. most CPU's. Cache is memory that the CPU can access directly and
  11. is usually located on the same chip. This uclass can be used for
  12. configuring settings that be found from a device tree file.
  13. config L2X0_CACHE
  14. tristate "PL310 cache driver"
  15. select CACHE
  16. depends on ARM
  17. help
  18. This driver is for the PL310 cache controller commonly found on
  19. ARMv7(32-bit) devices. The driver configures the cache settings
  20. found in the device tree.
  21. config V5L2_CACHE
  22. bool "Andes V5L2 cache driver"
  23. select CACHE
  24. depends on RISCV_NDS_CACHE
  25. help
  26. Support Andes V5L2 cache controller in AE350 platform.
  27. It will configure tag and data ram timing control from the
  28. device tree and enable L2 cache.
  29. config NCORE_CACHE
  30. bool "Arteris Ncore cache coherent unit driver"
  31. select CACHE
  32. help
  33. This driver is for the Arteris Ncore cache coherent unit (CCU)
  34. controller. The driver initializes cache directories and coherent
  35. agent interfaces.
  36. config SIFIVE_CCACHE
  37. bool "SiFive composable cache"
  38. select CACHE
  39. help
  40. This driver is for SiFive Composable L2/L3 cache. It enables cache
  41. ways of composable cache.
  42. endmenu