eXalion.h 16 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /* ------------------------------------------------------------------------- */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MPC824X 1
  18. /* #define CONFIG_MPC8240 1 */
  19. #define CONFIG_MPC8245 1
  20. #define CONFIG_EXALION 1
  21. #define CONFIG_SYS_TEXT_BASE 0xFFF00000
  22. #if defined (CONFIG_MPC8240)
  23. /* #warning ---------- eXalion with MPC8240 --------------- */
  24. #elif defined (CONFIG_MPC8245)
  25. /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */
  26. #elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
  27. #error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
  28. #else
  29. #error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  30. #endif
  31. /* older kernels need clock in MHz newer in Hz */
  32. /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */
  33. #undef CONFIG_CLOCKS_IN_MHZ
  34. #define CONFIG_BOOTDELAY 10
  35. /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
  36. /*
  37. * BOOTP options
  38. */
  39. #define CONFIG_BOOTP_BOOTFILESIZE
  40. #define CONFIG_BOOTP_BOOTPATH
  41. #define CONFIG_BOOTP_GATEWAY
  42. #define CONFIG_BOOTP_HOSTNAME
  43. /*
  44. * Command line configuration.
  45. */
  46. #include <config_cmd_default.h>
  47. #define CONFIG_CMD_FLASH
  48. #define CONFIG_CMD_SDRAM
  49. #define CONFIG_CMD_I2C
  50. #define CONFIG_CMD_IDE
  51. #define CONFIG_CMD_FAT
  52. #define CONFIG_CMD_SAVEENV
  53. #define CONFIG_CMD_PCI
  54. /*-----------------------------------------------------------------------
  55. * Miscellaneous configurable options
  56. */
  57. #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
  58. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  59. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  60. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  61. #define CONFIG_SYS_MAXARGS 8 /* max number of command args */
  62. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  63. #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
  64. #define CONFIG_MISC_INIT_R 1
  65. /*-----------------------------------------------------------------------
  66. * Start addresses for the final memory configuration
  67. * (Set up by the startup code)
  68. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  69. */
  70. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  71. #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */
  72. /* return real value. */
  73. #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
  74. #undef CONFIG_SYS_RAMBOOT
  75. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  76. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  77. /*-----------------------------------------------------------------------
  78. * Definitions for initial stack pointer and data area
  79. */
  80. #define CONFIG_SYS_INIT_DATA_SIZE 128
  81. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  82. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  83. #define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
  84. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  85. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  86. #if defined (CONFIG_MPC8240)
  87. #define CONFIG_SYS_FLASH_BASE 0xFFE00000
  88. #define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */
  89. #elif defined (CONFIG_MPC8245)
  90. #define CONFIG_SYS_FLASH_BASE 0xFFC00000
  91. #define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */
  92. #else
  93. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  94. #endif
  95. #define CONFIG_ENV_IS_IN_FLASH 1
  96. #define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */
  97. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for environment */
  98. #define CONFIG_ENV_ADDR 0xFFFC0000
  99. #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
  100. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  101. #define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
  102. #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
  103. #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
  104. #define CONFIG_SYS_EUMB_ADDR 0xFC000000
  105. /* #define CONFIG_SYS_ISA_MEM 0xFD000000 */
  106. #define CONFIG_SYS_ISA_IO 0xFE000000
  107. /*-----------------------------------------------------------------------
  108. * FLASH organization
  109. */
  110. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
  111. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
  112. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  113. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  114. #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE
  115. #define FLASH_BASE1_PRELIM 0
  116. /*-----------------------------------------------------------------------
  117. * FLASH and environment organization
  118. */
  119. #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
  120. #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
  121. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
  122. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  123. #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
  124. #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
  125. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  126. /*-----------------------------------------------------------------------
  127. * PCI stuff
  128. */
  129. #define CONFIG_PCI 1 /* include pci support */
  130. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  131. #undef CONFIG_PCI_PNP
  132. #define CONFIG_EEPRO100 1
  133. #define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */
  134. #define PCI_ENET0_IOADDR 0x80000000
  135. #define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */
  136. #define PCI_ENET1_IOADDR 0x81000000
  137. #define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */
  138. #define PCI_ENET2_IOADDR 0x82000000
  139. #define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */
  140. #define PCI_ENET3_IOADDR 0x83000000
  141. /*-----------------------------------------------------------------------
  142. * NS16550 Configuration
  143. */
  144. #define CONFIG_SYS_NS16550 1
  145. #define CONFIG_SYS_NS16550_SERIAL 1
  146. #define CONFIG_CONS_INDEX 1
  147. #define CONFIG_BAUDRATE 38400
  148. #define CONFIG_SYS_NS16550_REG_SIZE 1
  149. #if (CONFIG_CONS_INDEX == 1)
  150. #define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */
  151. #else
  152. #define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
  153. #endif
  154. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8)
  155. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500)
  156. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600)
  157. /*-----------------------------------------------------------------------
  158. * select i2c support configuration
  159. *
  160. * Supported configurations are {none, software, hardware} drivers.
  161. * If the software driver is chosen, there are some additional
  162. * configuration items that the driver uses to drive the port pins.
  163. */
  164. #define CONFIG_HARD_I2C 1 /* To enable I2C support */
  165. #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  166. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  167. #define CONFIG_SYS_I2C_SLAVE 0x7F
  168. /*-----------------------------------------------------------------------
  169. * Low Level Configuration Settings
  170. * (address mappings, register initial values, etc.)
  171. * You should know what you are doing if you make changes here.
  172. */
  173. #define CONFIG_SYS_HZ 1000
  174. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  175. #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
  176. /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */
  177. #if defined (CONFIG_MPC8245)
  178. /* Bit-field values for PMCR2. */
  179. #if defined (CONFIG_133MHZ_DRAM)
  180. #define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */
  181. #define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */
  182. #endif
  183. /* Bit-field values for MIOCR1. */
  184. #if !defined (CONFIG_133MHZ_DRAM)
  185. #define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */
  186. #endif
  187. /* Bit-field values for MIOCR2. */
  188. #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */
  189. /* - note bottom 3 bits MUST be 0 */
  190. #endif
  191. /* Bit-field values for MCCR1. */
  192. #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
  193. #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
  194. /* Bit-field values for MCCR2. */
  195. #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
  196. #if defined (CONFIG_133MHZ_DRAM)
  197. #define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */
  198. #else /* refresh cycles */
  199. #define CONFIG_SYS_REFINT 750
  200. #endif
  201. /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
  202. #if defined (CONFIG_133MHZ_DRAM)
  203. #define CONFIG_SYS_BSTOPRE 1023
  204. #else
  205. #define CONFIG_SYS_BSTOPRE 250
  206. #endif
  207. /* Bit-field values for MCCR3. */
  208. /* the following are for SDRAM only */
  209. #if defined (CONFIG_133MHZ_DRAM)
  210. #define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */
  211. #else
  212. #define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */
  213. #endif
  214. #if defined (CONFIG_MPC8240)
  215. #define CONFIG_SYS_RDLAT 2 /* data latency from read command */
  216. #endif
  217. /* Bit-field values for MCCR4. */
  218. #if defined (CONFIG_133MHZ_DRAM)
  219. #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
  220. #define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */
  221. #define CONFIG_SYS_ACTORW 5 /* Activate to R/W */
  222. #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
  223. #else
  224. #if 0
  225. #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
  226. #define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
  227. #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
  228. #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
  229. #endif
  230. #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
  231. #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
  232. #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
  233. #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
  234. #endif
  235. #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
  236. #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
  237. #define CONFIG_SYS_REGDIMM 0
  238. #if defined (CONFIG_MPC8240)
  239. #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0
  240. #elif defined (CONFIG_MPC8245)
  241. #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
  242. #define CONFIG_SYS_EXTROM 0
  243. #else
  244. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  245. #endif
  246. /*-----------------------------------------------------------------------
  247. memory bank settings
  248. * only bits 20-29 are actually used from these vales to set the
  249. * start/end address the upper two bits will be 0, and the lower 20
  250. * bits will be set to 0x00000 for a start address, or 0xfffff for an
  251. * end address
  252. */
  253. #define CONFIG_SYS_BANK0_START 0x00000000
  254. #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
  255. #define CONFIG_SYS_BANK0_ENABLE 1
  256. #define CONFIG_SYS_BANK1_START 0x3ff00000
  257. #define CONFIG_SYS_BANK1_END 0x3fffffff
  258. #define CONFIG_SYS_BANK1_ENABLE 0
  259. #define CONFIG_SYS_BANK2_START 0x3ff00000
  260. #define CONFIG_SYS_BANK2_END 0x3fffffff
  261. #define CONFIG_SYS_BANK2_ENABLE 0
  262. #define CONFIG_SYS_BANK3_START 0x3ff00000
  263. #define CONFIG_SYS_BANK3_END 0x3fffffff
  264. #define CONFIG_SYS_BANK3_ENABLE 0
  265. #define CONFIG_SYS_BANK4_START 0x00000000
  266. #define CONFIG_SYS_BANK4_END 0x00000000
  267. #define CONFIG_SYS_BANK4_ENABLE 0
  268. #define CONFIG_SYS_BANK5_START 0x00000000
  269. #define CONFIG_SYS_BANK5_END 0x00000000
  270. #define CONFIG_SYS_BANK5_ENABLE 0
  271. #define CONFIG_SYS_BANK6_START 0x00000000
  272. #define CONFIG_SYS_BANK6_END 0x00000000
  273. #define CONFIG_SYS_BANK6_ENABLE 0
  274. #define CONFIG_SYS_BANK7_START 0x00000000
  275. #define CONFIG_SYS_BANK7_END 0x00000000
  276. #define CONFIG_SYS_BANK7_ENABLE 0
  277. /*-----------------------------------------------------------------------
  278. * Memory bank enable bitmask, specifying which of the banks defined above
  279. are actually present. MSB is for bank #7, LSB is for bank #0.
  280. */
  281. #define CONFIG_SYS_BANK_ENABLE 0x01
  282. #if defined (CONFIG_MPC8240)
  283. #define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */
  284. /* see 8240 book for bit definitions */
  285. #elif defined (CONFIG_MPC8245)
  286. #if defined (CONFIG_133MHZ_DRAM)
  287. #define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */
  288. #else
  289. #define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */
  290. #endif
  291. #else
  292. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  293. #endif
  294. #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
  295. /* currently accessed page in memory */
  296. /* see 8240 book for details */
  297. /*-----------------------------------------------------------------------
  298. * Block Address Translation (BAT) register settings.
  299. */
  300. /* SDRAM 0 - 256MB */
  301. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  302. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  303. /* stack in DCACHE @ 1GB (no backing mem) */
  304. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
  305. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  306. /* PCI memory */
  307. #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  308. #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  309. /* Flash, config addrs, etc */
  310. #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  311. #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  312. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  313. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  314. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  315. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  316. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  317. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  318. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  319. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  320. /*-----------------------------------------------------------------------
  321. * Cache Configuration
  322. */
  323. #define CONFIG_SYS_CACHELINE_SIZE 32
  324. #if defined(CONFIG_CMD_KGDB)
  325. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  326. #endif
  327. /* values according to the manual */
  328. #define CONFIG_DRAM_50MHZ 1
  329. #define CONFIG_SDRAM_50MHZ
  330. #undef NR_8259_INTS
  331. #define NR_8259_INTS 1
  332. /*-----------------------------------------------------------------------
  333. * IDE/ATA stuff
  334. */
  335. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
  336. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */
  337. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */
  338. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
  339. #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
  340. #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
  341. #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
  342. #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
  343. #define CONFIG_ATAPI
  344. #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
  345. #undef CONFIG_IDE_LED /* no led for ide supported */
  346. #undef CONFIG_IDE_RESET /* reset for ide supported... */
  347. #undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
  348. /*-----------------------------------------------------------------------
  349. * DISK Partition support
  350. */
  351. #define CONFIG_DOS_PARTITION
  352. /*-----------------------------------------------------------------------
  353. * For booting Linux, the board info and command line data
  354. * have to be in the first 8 MB of memory, since this is
  355. * the maximum mapped by the Linux kernel during initialization.
  356. */
  357. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  358. #endif /* __CONFIG_H */