clk-jh7110.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022 Starfive, Inc.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clk.h>
  9. #include <clk-uclass.h>
  10. #include <clk.h>
  11. #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  12. #include <dm/device.h>
  13. #include <dm/devres.h>
  14. #include <dm.h>
  15. #include <malloc.h>
  16. #include <log.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/io.h>
  19. #define STARFIVE_CLK_ENABLE_SHIFT 31 /*[31]*/
  20. #define STARFIVE_CLK_INVERT_SHIFT 30 /*[30]*/
  21. #define STARFIVE_CLK_MUX_SHIFT 24 /*[29:24]*/
  22. #define STARFIVE_CLK_DIV_SHIFT 0 /*[23:0]*/
  23. #define SYS_OFFSET(id) ((id) * 4)
  24. #define STG_OFFSET(id) (((id) - JH7110_CLK_SYS_REG_END) * 4)
  25. #define AON_OFFSET(id) (((id) - JH7110_CLK_STG_REG_END) * 4)
  26. #define VOUT_OFFSET(id) (((id) - JH7110_CLK_VOUT_START) * 4)
  27. struct jh7110_clk_priv {
  28. void __iomem *sys;
  29. void __iomem *stg;
  30. void __iomem *aon;
  31. void __iomem *vout;
  32. };
  33. static const char *cpu_root_sels[2] = {
  34. [0] = "osc",
  35. [1] = "pll0_out",
  36. };
  37. static const char *perh_root_sels[2] = {
  38. [0] = "pll0_out",
  39. [1] = "pll2_out",
  40. };
  41. static const char *bus_root_sels[2] = {
  42. [0] = "osc",
  43. [1] = "pll2_out",
  44. };
  45. static const char *qspi_ref_sels[2] = {
  46. [0] = "osc",
  47. [1] = "u0_cdns_qspi_ref_src",
  48. };
  49. static const char *gmac5_tx_sels[2] = {
  50. [0] = "gmac1_gtxclk",
  51. [1] = "gmac1_rmii_rtx",
  52. };
  53. static const char *u0_dw_gmac5_axi64_clk_tx_sels[2] = {
  54. [0] = "gmac0_gtxclk",
  55. [1] = "gmac0_rmii_rtx",
  56. };
  57. static const char *mclk_sels[2] = {
  58. [0] = "mclk_inner",
  59. [1] = "mclk_ext",
  60. };
  61. static const char *u0_i2stx_4ch_bclk_sels[2] = {
  62. [0] = "i2stx_4ch0_bclk_mst",
  63. [1] = "i2stx_bclk_ext",
  64. };
  65. static const char *u0_dc8200_clk_pix_sels[2] = {
  66. [0] = "dc8200_pix0",
  67. [1] = "hdmitx0_pixelclk",
  68. };
  69. static const char *dom_vout_top_lcd_clk_sels[2] = {
  70. [0] = "u0_dc8200_clk_pix0_out",
  71. [1] = "u0_dc8200_clk_pix1_out",
  72. };
  73. static const char *u0_cdns_dsitx_clk_sels[2] = {
  74. [0] = "dc8200_pix0",
  75. [1] = "hdmitx0_pixelclk",
  76. };
  77. static ulong starfive_clk_get_rate(struct clk *clk)
  78. {
  79. struct clk *c;
  80. int ret;
  81. debug("%s(#%lu)\n", __func__, clk->id);
  82. ret = clk_get_by_id(clk->id, &c);
  83. if (ret)
  84. return ret;
  85. return clk_get_rate(c);
  86. }
  87. static ulong starfive_clk_set_rate(struct clk *clk, unsigned long rate)
  88. {
  89. struct clk *c;
  90. int ret;
  91. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  92. ret = clk_get_by_id(clk->id, &c);
  93. if (ret)
  94. return ret;
  95. return clk_set_rate(c, rate);
  96. }
  97. static int __starfive_clk_enable(struct clk *clk, bool enable)
  98. {
  99. struct clk *c;
  100. int ret;
  101. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  102. ret = clk_get_by_id(clk->id, &c);
  103. if (ret)
  104. return ret;
  105. if (enable)
  106. ret = clk_enable(c);
  107. else
  108. ret = clk_disable(c);
  109. return ret;
  110. }
  111. static int starfive_clk_disable(struct clk *clk)
  112. {
  113. return __starfive_clk_enable(clk, 0);
  114. }
  115. static int starfive_clk_enable(struct clk *clk)
  116. {
  117. return __starfive_clk_enable(clk, 1);
  118. }
  119. static int starfive_clk_set_parent(struct clk *clk, struct clk *parent)
  120. {
  121. struct clk *c, *cp;
  122. int ret;
  123. debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
  124. ret = clk_get_by_id(clk->id, &c);
  125. if (ret)
  126. return ret;
  127. ret = clk_get_by_id(parent->id, &cp);
  128. if (ret)
  129. return ret;
  130. ret = clk_set_parent(c, cp);
  131. c->dev->parent = cp->dev;
  132. return ret;
  133. }
  134. static const struct clk_ops starfive_clk_ops = {
  135. .set_rate = starfive_clk_set_rate,
  136. .get_rate = starfive_clk_get_rate,
  137. .enable = starfive_clk_enable,
  138. .disable = starfive_clk_disable,
  139. .set_parent = starfive_clk_set_parent,
  140. };
  141. static struct clk *starfive_clk_mux(void __iomem *reg,
  142. const char *name,
  143. unsigned int offset,
  144. u8 width,
  145. const char * const *parent_names,
  146. u8 num_parents)
  147. {
  148. return clk_register_mux(NULL, name, parent_names, num_parents, 0,
  149. reg + offset, STARFIVE_CLK_MUX_SHIFT, width, 0);
  150. }
  151. static struct clk *starfive_clk_gate(void __iomem *reg,
  152. const char *name,
  153. const char *parent_name,
  154. unsigned int offset)
  155. {
  156. return clk_register_gate(NULL, name, parent_name, 0, reg+offset,
  157. STARFIVE_CLK_ENABLE_SHIFT, 0, NULL);
  158. }
  159. static struct clk *starfive_clk_fix_factor(void __iomem *reg,
  160. const char *name,
  161. const char *parent_name,
  162. unsigned int mult,
  163. unsigned int div)
  164. {
  165. return clk_register_fixed_factor(NULL, name, parent_name,
  166. 0, mult, div);
  167. }
  168. static struct clk *starfive_clk_divider(void __iomem *reg,
  169. const char *name,
  170. const char *parent_name,
  171. unsigned int offset,
  172. u8 width)
  173. {
  174. return clk_register_divider(NULL, name, parent_name, 0, reg+offset, 0,
  175. width, CLK_DIVIDER_ONE_BASED);
  176. }
  177. static struct clk *starfive_clk_composite(void __iomem *reg,
  178. const char *name,
  179. const char * const *parent_names,
  180. unsigned int num_parents,
  181. unsigned int offset,
  182. unsigned int mux_width,
  183. unsigned int gate_width,
  184. unsigned int div_width)
  185. {
  186. struct clk *clk = ERR_PTR(-ENOMEM);
  187. struct clk_divider *div = NULL;
  188. struct clk_gate *gate = NULL;
  189. struct clk_mux *mux = NULL;
  190. int mask_arry[4] = {0x1, 0x3, 0x7, 0xF};
  191. int mask;
  192. if (mux_width) {
  193. if (mux_width > 4)
  194. goto fail;
  195. else
  196. mask = mask_arry[mux_width-1];
  197. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  198. if (!mux)
  199. goto fail;
  200. mux->reg = reg + offset;
  201. mux->mask = mask;
  202. mux->shift = STARFIVE_CLK_MUX_SHIFT;
  203. mux->num_parents = num_parents;
  204. mux->flags = 0;
  205. mux->parent_names = parent_names;
  206. }
  207. if (gate_width) {
  208. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  209. if (!gate)
  210. goto fail;
  211. gate->reg = reg + offset;
  212. gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT;
  213. gate->flags = 0;
  214. }
  215. if (div_width) {
  216. div = kzalloc(sizeof(*div), GFP_KERNEL);
  217. if (!div)
  218. goto fail;
  219. div->reg = reg + offset;
  220. if ((offset == SYS_OFFSET(JH7110_UART3_CLK_CORE)) ||
  221. (offset == SYS_OFFSET(JH7110_UART4_CLK_CORE)) ||
  222. (offset == SYS_OFFSET(JH7110_UART5_CLK_CORE))) {
  223. div->shift = 8;
  224. div->width = 8;
  225. } else {
  226. div->shift = STARFIVE_CLK_DIV_SHIFT;
  227. div->width = div_width;
  228. }
  229. div->flags = CLK_DIVIDER_ONE_BASED;
  230. div->table = NULL;
  231. }
  232. clk = clk_register_composite(NULL, name,
  233. parent_names, num_parents,
  234. &mux->clk, &clk_mux_ops,
  235. &div->clk, &clk_divider_ops,
  236. &gate->clk, &clk_gate_ops, 0);
  237. if (IS_ERR(clk))
  238. goto fail;
  239. return clk;
  240. fail:
  241. kfree(gate);
  242. kfree(div);
  243. kfree(mux);
  244. return ERR_CAST(clk);
  245. }
  246. static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg,
  247. const char *name,
  248. const char *parent_names,
  249. unsigned int offset,
  250. unsigned int mux_width,
  251. unsigned int gate_width,
  252. unsigned int div_width)
  253. {
  254. const char * const *parents;
  255. parents = &parent_names;
  256. return starfive_clk_composite(reg, name, parents, 1, offset,
  257. mux_width, gate_width, div_width);
  258. }
  259. static struct clk *starfive_clk_gate_divider(void __iomem *reg,
  260. const char *name,
  261. const char *parent,
  262. unsigned int offset,
  263. unsigned int width)
  264. {
  265. const char * const *parent_names;
  266. parent_names = &parent;
  267. return starfive_clk_composite(reg, name, parent_names, 1,
  268. offset, 0, 1, width);
  269. }
  270. static int jh7110_clk_init(struct udevice *dev)
  271. {
  272. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  273. struct starfive_pll_freq conf;
  274. u64 pll;
  275. pll = starfive_jh7110_pll_get_rate(PLL0, &conf);
  276. clk_dm(JH7110_PLL0_OUT,
  277. starfive_clk_fix_factor(priv->sys,
  278. "pll0_out", "osc", conf.fbdiv,
  279. conf.prediv * conf.postdiv1));
  280. pll = starfive_jh7110_pll_get_rate(PLL1, &conf);
  281. clk_dm(JH7110_PLL1_OUT,
  282. starfive_clk_fix_factor(priv->sys,
  283. "pll1_out", "osc", conf.fbdiv,
  284. conf.prediv * conf.postdiv1));
  285. pll = starfive_jh7110_pll_get_rate(PLL2, &conf);
  286. clk_dm(JH7110_PLL2_OUT,
  287. starfive_clk_fix_factor(priv->sys,
  288. "pll2_out", "osc", conf.fbdiv,
  289. conf.prediv * conf.postdiv1));
  290. /*root*/
  291. clk_dm(JH7110_CPU_ROOT,
  292. starfive_clk_mux(priv->sys, "cpu_root",
  293. SYS_OFFSET(JH7110_CPU_ROOT), 1,
  294. cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
  295. clk_dm(JH7110_CPU_CORE,
  296. starfive_clk_divider(priv->sys,
  297. "cpu_core", "cpu_root",
  298. SYS_OFFSET(JH7110_CPU_CORE), 3));
  299. clk_dm(JH7110_CPU_BUS,
  300. starfive_clk_divider(priv->sys,
  301. "cpu_bus", "cpu_core",
  302. SYS_OFFSET(JH7110_CPU_BUS), 2));
  303. clk_dm(JH7110_DDR_ROOT,
  304. starfive_clk_fix_factor(priv->sys,
  305. "ddr_root", "pll1_out", 1, 1));
  306. clk_dm(JH7110_GMACUSB_ROOT,
  307. starfive_clk_fix_factor(priv->sys,
  308. "gmacusb_root", "pll0_out", 1, 1));
  309. clk_dm(JH7110_PERH_ROOT,
  310. starfive_clk_composite(priv->sys,
  311. "perh_root",
  312. perh_root_sels, ARRAY_SIZE(perh_root_sels),
  313. SYS_OFFSET(JH7110_PERH_ROOT), 1, 0, 2));
  314. clk_dm(JH7110_BUS_ROOT,
  315. starfive_clk_mux(priv->sys, "bus_root",
  316. SYS_OFFSET(JH7110_BUS_ROOT), 1,
  317. bus_root_sels, ARRAY_SIZE(bus_root_sels)));
  318. clk_dm(JH7110_AXI_CFG0,
  319. starfive_clk_divider(priv->sys,
  320. "axi_cfg0", "bus_root",
  321. SYS_OFFSET(JH7110_AXI_CFG0), 2));
  322. clk_dm(JH7110_STG_AXIAHB,
  323. starfive_clk_divider(priv->sys,
  324. "stg_axiahb", "axi_cfg0",
  325. SYS_OFFSET(JH7110_STG_AXIAHB), 2));
  326. clk_dm(JH7110_AHB0,
  327. starfive_clk_gate(priv->sys,
  328. "ahb0", "stg_axiahb",
  329. SYS_OFFSET(JH7110_AHB0)));
  330. clk_dm(JH7110_AHB1,
  331. starfive_clk_gate(priv->sys,
  332. "ahb1", "stg_axiahb",
  333. SYS_OFFSET(JH7110_AHB1)));
  334. clk_dm(JH7110_APB_BUS_FUNC,
  335. starfive_clk_divider(priv->sys,
  336. "apb_bus_func", "stg_axiahb",
  337. SYS_OFFSET(JH7110_APB_BUS_FUNC), 4));
  338. clk_dm(JH7110_PCLK2_MUX_FUNC_PCLK,
  339. starfive_clk_fix_factor(priv->sys,
  340. "u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1));
  341. clk_dm(JH7110_U2_PCLK_MUX_PCLK,
  342. starfive_clk_fix_factor(priv->sys,
  343. "u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1));
  344. clk_dm(JH7110_APB_BUS,
  345. starfive_clk_fix_factor(priv->sys,
  346. "apb_bus", "u2_pclk_mux_pclk", 1, 1));
  347. clk_dm(JH7110_APB0,
  348. starfive_clk_gate(priv->sys,
  349. "apb0", "apb_bus",
  350. SYS_OFFSET(JH7110_APB0)));
  351. clk_dm(JH7110_APB12,
  352. starfive_clk_fix_factor(priv->sys,
  353. "apb12", "apb_bus", 1, 1));
  354. clk_dm(JH7110_AON_APB,
  355. starfive_clk_fix_factor(priv->sys,
  356. "aon_apb", "apb_bus_func", 1, 1));
  357. /*QSPI*/
  358. clk_dm(JH7110_QSPI_CLK_AHB,
  359. starfive_clk_gate(priv->sys,
  360. "u0_cdns_qspi_clk_ahb", "ahb1",
  361. SYS_OFFSET(JH7110_QSPI_CLK_AHB)));
  362. clk_dm(JH7110_QSPI_CLK_APB,
  363. starfive_clk_gate(priv->sys,
  364. "u0_cdns_qspi_clk_apb", "apb12",
  365. SYS_OFFSET(JH7110_QSPI_CLK_APB)));
  366. clk_dm(JH7110_QSPI_REF_SRC,
  367. starfive_clk_divider(priv->sys,
  368. "u0_cdns_qspi_ref_src", "gmacusb_root",
  369. SYS_OFFSET(JH7110_QSPI_REF_SRC), 5));
  370. clk_dm(JH7110_QSPI_CLK_REF,
  371. starfive_clk_composite(priv->sys,
  372. "u0_cdns_qspi_clk_ref",
  373. qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
  374. SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0));
  375. /*SDIO*/
  376. clk_dm(JH7110_SDIO0_CLK_AHB,
  377. starfive_clk_gate(priv->sys,
  378. "u0_dw_sdio_clk_ahb", "ahb0",
  379. SYS_OFFSET(JH7110_SDIO0_CLK_AHB)));
  380. clk_dm(JH7110_SDIO1_CLK_AHB,
  381. starfive_clk_gate(priv->sys,
  382. "u1_dw_sdio_clk_ahb", "ahb0",
  383. SYS_OFFSET(JH7110_SDIO1_CLK_AHB)));
  384. clk_dm(JH7110_SDIO0_CLK_SDCARD,
  385. starfive_clk_fix_parent_composite(priv->sys,
  386. "u0_dw_sdio_clk_sdcard", "axi_cfg0",
  387. SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4));
  388. clk_dm(JH7110_SDIO1_CLK_SDCARD,
  389. starfive_clk_fix_parent_composite(priv->sys,
  390. "u1_dw_sdio_clk_sdcard", "axi_cfg0",
  391. SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4));
  392. /*STG*/
  393. clk_dm(JH7110_USB_125M,
  394. starfive_clk_divider(priv->sys,
  395. "usb_125m", "gmacusb_root",
  396. SYS_OFFSET(JH7110_USB_125M), 4));
  397. /*GMAC1*/
  398. clk_dm(JH7110_GMAC5_CLK_AHB,
  399. starfive_clk_gate(priv->sys,
  400. "u1_dw_gmac5_axi64_clk_ahb", "ahb0",
  401. SYS_OFFSET(JH7110_GMAC5_CLK_AHB)));
  402. clk_dm(JH7110_GMAC5_CLK_AXI,
  403. starfive_clk_gate(priv->sys,
  404. "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb",
  405. SYS_OFFSET(JH7110_GMAC5_CLK_AXI)));
  406. clk_dm(JH7110_GMAC_SRC,
  407. starfive_clk_divider(priv->sys,
  408. "gmac_src", "gmacusb_root",
  409. SYS_OFFSET(JH7110_GMAC_SRC), 3));
  410. clk_dm(JH7110_GMAC1_GTXCLK,
  411. starfive_clk_divider(priv->sys,
  412. "gmac1_gtxclk", "gmacusb_root",
  413. SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4));
  414. clk_dm(JH7110_GMAC1_GTXC,
  415. starfive_clk_gate(priv->sys,
  416. "gmac1_gtxc", "gmac1_gtxclk",
  417. SYS_OFFSET(JH7110_GMAC1_GTXC)));
  418. clk_dm(JH7110_GMAC1_RMII_RTX,
  419. starfive_clk_divider(priv->sys,
  420. "gmac1_rmii_rtx", "gmac1_rmii_refin",
  421. SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5));
  422. clk_dm(JH7110_GMAC5_CLK_PTP,
  423. starfive_clk_gate_divider(priv->sys,
  424. "u1_dw_gmac5_axi64_clk_ptp", "gmac_src",
  425. SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5));
  426. clk_dm(JH7110_GMAC5_CLK_TX,
  427. starfive_clk_composite(priv->sys,
  428. "u1_dw_gmac5_axi64_clk_tx",
  429. gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels),
  430. SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0));
  431. /*GMAC0*/
  432. clk_dm(JH7110_AON_AHB,
  433. starfive_clk_fix_factor(priv->sys, "aon_ahb",
  434. "stg_axiahb", 1, 1));
  435. clk_dm(JH7110_GMAC0_GTXCLK,
  436. starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk",
  437. "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4));
  438. clk_dm(JH7110_GMAC0_PTP,
  439. starfive_clk_gate_divider(priv->sys, "gmac0_ptp",
  440. "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5));
  441. clk_dm(JH7110_GMAC0_GTXC,
  442. starfive_clk_gate(priv->sys,
  443. "gmac0_gtxc", "gmac0_gtxclk",
  444. SYS_OFFSET(JH7110_GMAC0_GTXC)));
  445. /*UART0*/
  446. clk_dm(JH7110_UART0_CLK_APB,
  447. starfive_clk_gate(priv->sys,
  448. "u0_dw_uart_clk_apb", "apb0",
  449. SYS_OFFSET(JH7110_UART0_CLK_APB)));
  450. clk_dm(JH7110_UART0_CLK_CORE,
  451. starfive_clk_gate(priv->sys,
  452. "u0_dw_uart_clk_core", "osc",
  453. SYS_OFFSET(JH7110_UART0_CLK_CORE)));
  454. /*UART1*/
  455. clk_dm(JH7110_UART1_CLK_APB,
  456. starfive_clk_gate(priv->sys,
  457. "u1_dw_uart_clk_apb", "apb0",
  458. SYS_OFFSET(JH7110_UART1_CLK_APB)));
  459. clk_dm(JH7110_UART1_CLK_CORE,
  460. starfive_clk_gate(priv->sys,
  461. "u1_dw_uart_clk_core", "osc",
  462. SYS_OFFSET(JH7110_UART1_CLK_CORE)));
  463. /*UART2*/
  464. clk_dm(JH7110_UART2_CLK_APB,
  465. starfive_clk_gate(priv->sys,
  466. "u2_dw_uart_clk_apb", "apb0",
  467. SYS_OFFSET(JH7110_UART2_CLK_APB)));
  468. clk_dm(JH7110_UART2_CLK_CORE,
  469. starfive_clk_gate(priv->sys,
  470. "u2_dw_uart_clk_core", "osc",
  471. SYS_OFFSET(JH7110_UART2_CLK_CORE)));
  472. /*UART3*/
  473. clk_dm(JH7110_UART3_CLK_APB,
  474. starfive_clk_gate(priv->sys,
  475. "u3_dw_uart_clk_apb", "apb0",
  476. SYS_OFFSET(JH7110_UART3_CLK_APB)));
  477. clk_dm(JH7110_UART3_CLK_CORE,
  478. starfive_clk_gate_divider(priv->sys,
  479. "u3_dw_uart_clk_core", "perh_root",
  480. SYS_OFFSET(JH7110_UART3_CLK_CORE), 8));
  481. /*UART4*/
  482. clk_dm(JH7110_UART4_CLK_APB,
  483. starfive_clk_gate(priv->sys,
  484. "u4_dw_uart_clk_apb", "apb0",
  485. SYS_OFFSET(JH7110_UART4_CLK_APB)));
  486. clk_dm(JH7110_UART4_CLK_CORE,
  487. starfive_clk_gate_divider(priv->sys,
  488. "u4_dw_uart_clk_core", "perh_root",
  489. SYS_OFFSET(JH7110_UART4_CLK_CORE), 8));
  490. /*UART5*/
  491. clk_dm(JH7110_UART5_CLK_APB,
  492. starfive_clk_gate(priv->sys,
  493. "u5_dw_uart_clk_apb", "apb0",
  494. SYS_OFFSET(JH7110_UART5_CLK_APB)));
  495. clk_dm(JH7110_UART5_CLK_CORE,
  496. starfive_clk_gate_divider(priv->sys,
  497. "u5_dw_uart_clk_core", "perh_root",
  498. SYS_OFFSET(JH7110_UART5_CLK_CORE), 8));
  499. clk_dm(JH7110_STG_APB,
  500. starfive_clk_fix_factor(priv->stg,
  501. "stg_apb", "apb_bus", 1, 1));
  502. /*USB*/
  503. clk_dm(JH7110_USB0_CLK_USB_APB,
  504. starfive_clk_gate(priv->stg,
  505. "u0_cdn_usb_clk_usb_apb", "stg_apb",
  506. STG_OFFSET(JH7110_USB0_CLK_USB_APB)));
  507. clk_dm(JH7110_USB0_CLK_UTMI_APB,
  508. starfive_clk_gate(priv->stg,
  509. "u0_cdn_usb_clk_utmi_apb", "stg_apb",
  510. STG_OFFSET(JH7110_USB0_CLK_UTMI_APB)));
  511. clk_dm(JH7110_USB0_CLK_AXI,
  512. starfive_clk_gate(priv->stg,
  513. "u0_cdn_usb_clk_axi", "stg_axiahb",
  514. STG_OFFSET(JH7110_USB0_CLK_AXI)));
  515. clk_dm(JH7110_USB0_CLK_LPM,
  516. starfive_clk_gate_divider(priv->stg,
  517. "u0_cdn_usb_clk_lpm", "osc",
  518. STG_OFFSET(JH7110_USB0_CLK_LPM), 2));
  519. clk_dm(JH7110_USB0_CLK_STB,
  520. starfive_clk_gate_divider(priv->stg,
  521. "u0_cdn_usb_clk_stb", "osc",
  522. STG_OFFSET(JH7110_USB0_CLK_STB), 3));
  523. clk_dm(JH7110_USB0_CLK_APP_125,
  524. starfive_clk_gate(priv->stg,
  525. "u0_cdn_usb_clk_app_125", "usb_125m",
  526. STG_OFFSET(JH7110_USB0_CLK_APP_125)));
  527. clk_dm(JH7110_USB0_REFCLK,
  528. starfive_clk_divider(priv->stg,
  529. "u0_cdn_usb_refclk", "osc",
  530. STG_OFFSET(JH7110_USB0_REFCLK), 2));
  531. /*GMAC1*/
  532. clk_dm(JH7110_U0_GMAC5_CLK_AHB,
  533. starfive_clk_gate(priv->aon,
  534. "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb",
  535. AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB)));
  536. clk_dm(JH7110_U0_GMAC5_CLK_AXI,
  537. starfive_clk_gate(priv->aon,
  538. "u0_dw_gmac5_axi64_clk_axi", "aon_ahb",
  539. AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI)));
  540. clk_dm(JH7110_GMAC0_RMII_RTX,
  541. starfive_clk_divider(priv->aon,
  542. "gmac0_rmii_rtx", "gmac0_rmii_refin",
  543. AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5));
  544. clk_dm(JH7110_U0_GMAC5_CLK_PTP,
  545. starfive_clk_fix_factor(priv->aon,
  546. "u0_dw_gmac5_axi64_clk_ptp",
  547. "gmac0_ptp", 1, 1));
  548. clk_dm(JH7110_U0_GMAC5_CLK_TX,
  549. starfive_clk_composite(priv->aon,
  550. "u0_dw_gmac5_axi64_clk_tx",
  551. u0_dw_gmac5_axi64_clk_tx_sels,
  552. ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels),
  553. AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0));
  554. /*otp*/
  555. clk_dm(JH7110_OTPC_CLK_APB,
  556. starfive_clk_gate(priv->aon,
  557. "u0_otpc_clk_apb", "aon_apb",
  558. AON_OFFSET(JH7110_OTPC_CLK_APB)));
  559. /*vout*/
  560. clk_dm(JH7110_VOUT_ROOT,
  561. starfive_clk_fix_factor(priv->sys,
  562. "vout_root", "pll2_out", 1, 1));
  563. clk_dm(JH7110_AUDIO_ROOT,
  564. starfive_clk_divider(priv->sys,
  565. "audio_root", "pll2_out",
  566. SYS_OFFSET(JH7110_AUDIO_ROOT), 5));
  567. clk_dm(JH7110_VOUT_SRC,
  568. starfive_clk_gate(priv->sys,
  569. "u0_dom_vout_top_clk_vout_src", "vout_root",
  570. SYS_OFFSET(JH7110_VOUT_SRC)));
  571. clk_dm(JH7110_VOUT_AXI,
  572. starfive_clk_divider(priv->sys,
  573. "vout_axi", "vout_root",
  574. SYS_OFFSET(JH7110_VOUT_AXI), 3));
  575. clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AXI,
  576. starfive_clk_gate(priv->sys,
  577. "u0_dom_vout_top_vout_axi", "vout_axi",
  578. SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AXI)));
  579. clk_dm(JH7110_NOC_BUS_CLK_DISP_AXI,
  580. starfive_clk_gate(priv->sys,
  581. "u0_sft7110_noc_bus_clk_disp_axi", "vout_axi",
  582. SYS_OFFSET(JH7110_NOC_BUS_CLK_DISP_AXI)));
  583. clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AHB,
  584. starfive_clk_gate(priv->sys,
  585. "u0_dom_vout_top_clk_vout_ahb", "ahb1",
  586. SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AHB)));
  587. clk_dm(JH7110_MCLK_INNER,
  588. starfive_clk_divider(priv->sys,
  589. "mclk_inner", "audio_root",
  590. SYS_OFFSET(JH7110_MCLK_INNER), 5));
  591. clk_dm(JH7110_MCLK,
  592. starfive_clk_mux(priv->sys, "mclk",
  593. SYS_OFFSET(JH7110_MCLK), 1,
  594. mclk_sels, ARRAY_SIZE(mclk_sels)));
  595. clk_dm(JH7110_I2STX_4CH0_BCLK_MST,
  596. starfive_clk_gate_divider(priv->sys,
  597. "i2stx_4ch0_bclk_mst", "mclk",
  598. SYS_OFFSET(JH7110_I2STX_4CH0_BCLK_MST), 5));
  599. clk_dm(JH7110_I2STX0_4CHBCLK,
  600. starfive_clk_mux(priv->sys, "u0_i2stx_4ch_bclk",
  601. SYS_OFFSET(JH7110_I2STX0_4CHBCLK), 1,
  602. u0_i2stx_4ch_bclk_sels, ARRAY_SIZE(u0_i2stx_4ch_bclk_sels)));
  603. clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK,
  604. starfive_clk_fix_factor(priv->sys,
  605. "u0_dom_vout_top_clk_hdmitx0_bclk",
  606. "u0_i2stx_4ch_bclk", 1, 1));
  607. clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
  608. starfive_clk_gate(priv->sys,
  609. "u0_dom_vout_top_clk_hdmitx0_mclk", "mclk",
  610. SYS_OFFSET(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK)));
  611. clk_dm(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
  612. starfive_clk_divider(priv->sys,
  613. "u0_dom_vout_top_clk_mipiphy_ref", "osc",
  614. SYS_OFFSET(JH7110_MCLK_INNER), 2));
  615. return 0;
  616. }
  617. static int jh7110_clk_vout_init(struct udevice *dev)
  618. {
  619. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  620. clk_dm(JH7110_DISP_ROOT,
  621. starfive_clk_fix_factor(priv->vout,
  622. "disp_root", "u0_dom_vout_top_clk_vout_src",
  623. 1, 1));
  624. clk_dm(JH7110_DISP_AXI,
  625. starfive_clk_fix_factor(priv->vout,
  626. "disp_axi", "u0_dom_vout_top_vout_axi",
  627. 1, 1));
  628. clk_dm(JH7110_DISP_AHB,
  629. starfive_clk_fix_factor(priv->vout,
  630. "disp_ahb", "u0_dom_vout_top_clk_vout_ahb",
  631. 1, 1));
  632. clk_dm(JH7110_HDMITX0_MCLK,
  633. starfive_clk_fix_factor(priv->vout,
  634. "hdmitx0_mclk", "u0_dom_vout_top_clk_hdmitx0_mclk",
  635. 1, 1));
  636. clk_dm(JH7110_HDMITX0_SCK,
  637. starfive_clk_fix_factor(priv->vout,
  638. "hdmitx0_sck", "u0_dom_vout_top_clk_hdmitx0_bclk",
  639. 1, 1));
  640. clk_dm(JH7110_APB,
  641. starfive_clk_divider(priv->vout,
  642. "apb", "disp_ahb",
  643. VOUT_OFFSET(JH7110_APB), 5));
  644. clk_dm(JH7110_U0_PCLK_MUX_FUNC_PCLK,
  645. starfive_clk_fix_factor(priv->vout,
  646. "u0_pclk_mux_func_pclk", "apb",
  647. 1, 1));
  648. clk_dm(JH7110_DISP_APB,
  649. starfive_clk_fix_factor(priv->vout,
  650. "disp_apb", "u0_pclk_mux_func_pclk",
  651. 1, 1));
  652. clk_dm(JH7110_TX_ESC,
  653. starfive_clk_divider(priv->vout,
  654. "tx_esc", "disp_ahb",
  655. VOUT_OFFSET(JH7110_TX_ESC), 5));
  656. clk_dm(JH7110_DC8200_PIX0,
  657. starfive_clk_divider(priv->vout,
  658. "dc8200_pix0", "disp_root",
  659. VOUT_OFFSET(JH7110_DC8200_PIX0), 6));
  660. clk_dm(JH7110_DSI_SYS,
  661. starfive_clk_divider(priv->vout,
  662. "dsi_sys", "disp_root",
  663. VOUT_OFFSET(JH7110_DSI_SYS), 5));
  664. clk_dm(JH7110_U0_DC8200_CLK_PIX0,
  665. starfive_clk_composite(priv->vout,
  666. "u0_dc8200_clk_pix0",
  667. u0_dc8200_clk_pix_sels,
  668. ARRAY_SIZE(u0_dc8200_clk_pix_sels),
  669. VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX0), 1, 1, 0));
  670. clk_dm(JH7110_U0_DC8200_CLK_PIX1,
  671. starfive_clk_composite(priv->vout,
  672. "u0_dc8200_clk_pix1",
  673. u0_dc8200_clk_pix_sels,
  674. ARRAY_SIZE(u0_dc8200_clk_pix_sels),
  675. VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX1), 1, 1, 0));
  676. clk_dm(JH7110_U0_DC8200_CLK_AXI,
  677. starfive_clk_gate(priv->vout,
  678. "u0_dc8200_clk_axi", "disp_axi",
  679. VOUT_OFFSET(JH7110_U0_DC8200_CLK_AXI)));
  680. clk_dm(JH7110_U0_DC8200_CLK_CORE,
  681. starfive_clk_gate(priv->vout,
  682. "u0_dc8200_clk_core", "disp_axi",
  683. VOUT_OFFSET(JH7110_U0_DC8200_CLK_CORE)));
  684. clk_dm(JH7110_U0_DC8200_CLK_AHB,
  685. starfive_clk_gate(priv->vout,
  686. "u0_dc8200_clk_ahb", "disp_ahb",
  687. VOUT_OFFSET(JH7110_U0_DC8200_CLK_AHB)));
  688. clk_dm(JH7110_U0_DC8200_CLK_PIX0_OUT,
  689. starfive_clk_fix_factor(priv->vout,
  690. "u0_dc8200_clk_pix0_out", "u0_dc8200_clk_pix0",
  691. 1, 1));
  692. clk_dm(JH7110_U0_DC8200_CLK_PIX1_OUT,
  693. starfive_clk_fix_factor(priv->sys,
  694. "u0_dc8200_clk_pix1_out", "u0_dc8200_clk_pix1",
  695. 1, 1));
  696. clk_dm(JH7110_DOM_VOUT_TOP_LCD_CLK,
  697. starfive_clk_composite(priv->vout,
  698. "dom_vout_top_lcd_clk",
  699. dom_vout_top_lcd_clk_sels,
  700. ARRAY_SIZE(dom_vout_top_lcd_clk_sels),
  701. VOUT_OFFSET(JH7110_DOM_VOUT_TOP_LCD_CLK), 1, 1, 0));
  702. clk_dm(JH7110_U0_MIPITX_DPHY_CLK_TXESC,
  703. starfive_clk_gate(priv->vout,
  704. "u0_mipitx_dphy_clk_txesc", "tx_esc",
  705. VOUT_OFFSET(JH7110_U0_MIPITX_DPHY_CLK_TXESC)));
  706. clk_dm(JH7110_U0_CDNS_DSITX_CLK_SYS,
  707. starfive_clk_gate(priv->vout,
  708. "u0_cdns_dsiTx_clk_sys", "dsi_sys",
  709. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_SYS)));
  710. clk_dm(JH7110_U0_CDNS_DSITX_CLK_APB,
  711. starfive_clk_gate(priv->vout,
  712. "u0_cdns_dsiTx_clk_apb", "dsi_sys",
  713. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_APB)));
  714. clk_dm(JH7110_U0_CDNS_DSITX_CLK_TXESC,
  715. starfive_clk_gate(priv->vout,
  716. "u0_cdns_dsiTx_clk_txesc", "tx_esc",
  717. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_TXESC)));
  718. clk_dm(JH7110_U0_CDNS_DSITX_CLK_DPI,
  719. starfive_clk_composite(priv->vout,
  720. "u0_cdns_dsitx_clk_api",
  721. u0_cdns_dsitx_clk_sels,
  722. ARRAY_SIZE(u0_cdns_dsitx_clk_sels),
  723. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_DPI), 1, 1, 0));
  724. clk_dm(JH7110_U0_HDMI_TX_CLK_SYS,
  725. starfive_clk_gate(priv->vout,
  726. "u0_hdmi_tx_clk_sys", "disp_apb",
  727. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_SYS)));
  728. clk_dm(JH7110_U0_HDMI_TX_CLK_MCLK,
  729. starfive_clk_gate(priv->vout,
  730. "u0_hdmi_tx_clk_mclk", "hdmitx0_mclk",
  731. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_MCLK)));
  732. clk_dm(JH7110_U0_HDMI_TX_CLK_BCLK,
  733. starfive_clk_gate(priv->vout,
  734. "u0_hdmi_tx_clk_bclk", "hdmitx0_sck",
  735. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_BCLK)));
  736. return 0;
  737. }
  738. static int jh7110_clk_vout_probe(struct udevice *dev)
  739. {
  740. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  741. priv->vout = (void __iomem *)dev_read_addr(dev);
  742. if (!priv->vout)
  743. return -EINVAL;
  744. return jh7110_clk_vout_init(dev);
  745. }
  746. static int jh7110_clk_probe(struct udevice *dev)
  747. {
  748. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  749. priv->aon = dev_remap_addr_name(dev, "aon");
  750. if (!priv->aon)
  751. return -EINVAL;
  752. priv->sys = dev_remap_addr_name(dev, "sys");
  753. if (!priv->sys)
  754. return -EINVAL;
  755. priv->stg = dev_remap_addr_name(dev, "stg");
  756. if (!priv->stg)
  757. return -EINVAL;
  758. return jh7110_clk_init(dev);
  759. }
  760. static const struct udevice_id jh7110_clk_of_match[] = {
  761. { .compatible = "starfive,jh7110-clkgen" },
  762. { }
  763. };
  764. U_BOOT_DRIVER(jh7110_clk) = {
  765. .name = "jh7110_clk",
  766. .id = UCLASS_CLK,
  767. .of_match = jh7110_clk_of_match,
  768. .probe = jh7110_clk_probe,
  769. .ops = &starfive_clk_ops,
  770. .priv_auto = sizeof(struct jh7110_clk_priv),
  771. };
  772. static const struct udevice_id jh7110_clk_vout_of_match[] = {
  773. { .compatible = "starfive,jh7110-clk-vout" },
  774. { }
  775. };
  776. U_BOOT_DRIVER(jh7110_clk_vout) = {
  777. .name = "jh7110_clk_vout",
  778. .id = UCLASS_CLK,
  779. .of_match = jh7110_clk_vout_of_match,
  780. .probe = jh7110_clk_vout_probe,
  781. .ops = &starfive_clk_ops,
  782. .priv_auto = sizeof(struct jh7110_clk_priv),
  783. };