jh7110.dtsi 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /*
  3. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  4. * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
  5. */
  6. /dts-v1/;
  7. #include "jh7110_clk.dtsi"
  8. #include <dt-bindings/reset/starfive-jh7110.h>
  9. #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  10. #include <dt-bindings/clock/starfive-jh7110-isp.h>
  11. / {
  12. compatible = "starfive,jh7110";
  13. #address-cells = <2>;
  14. #size-cells = <2>;
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu0: cpu@0 {
  19. compatible = "sifive,u74-mc", "riscv";
  20. reg = <0>;
  21. d-cache-block-size = <64>;
  22. d-cache-sets = <64>;
  23. d-cache-size = <8192>;
  24. d-tlb-sets = <1>;
  25. d-tlb-size = <40>;
  26. device_type = "cpu";
  27. i-cache-block-size = <64>;
  28. i-cache-sets = <64>;
  29. i-cache-size = <16384>;
  30. i-tlb-sets = <1>;
  31. i-tlb-size = <40>;
  32. mmu-type = "riscv,sv39";
  33. next-level-cache = <&cachectrl>;
  34. riscv,isa = "rv64imacu";
  35. tlb-split;
  36. status = "disabled";
  37. cpu0intctrl: interrupt-controller {
  38. #interrupt-cells = <1>;
  39. compatible = "riscv,cpu-intc";
  40. interrupt-controller;
  41. };
  42. };
  43. cpu1: cpu@1 {
  44. compatible = "sifive,u74-mc", "riscv";
  45. reg = <1>;
  46. d-cache-block-size = <64>;
  47. d-cache-sets = <64>;
  48. d-cache-size = <32768>;
  49. d-tlb-sets = <1>;
  50. d-tlb-size = <40>;
  51. device_type = "cpu";
  52. i-cache-block-size = <64>;
  53. i-cache-sets = <64>;
  54. i-cache-size = <32768>;
  55. i-tlb-sets = <1>;
  56. i-tlb-size = <40>;
  57. mmu-type = "riscv,sv39";
  58. next-level-cache = <&cachectrl>;
  59. riscv,isa = "rv64imafdcbsux";
  60. tlb-split;
  61. status = "okay";
  62. cpu1intctrl: interrupt-controller {
  63. #interrupt-cells = <1>;
  64. compatible = "riscv,cpu-intc";
  65. interrupt-controller;
  66. };
  67. };
  68. cpu2: cpu@2 {
  69. compatible = "sifive,u74-mc", "riscv";
  70. reg = <2>;
  71. d-cache-block-size = <64>;
  72. d-cache-sets = <64>;
  73. d-cache-size = <32768>;
  74. d-tlb-sets = <1>;
  75. d-tlb-size = <40>;
  76. device_type = "cpu";
  77. i-cache-block-size = <64>;
  78. i-cache-sets = <64>;
  79. i-cache-size = <32768>;
  80. i-tlb-sets = <1>;
  81. i-tlb-size = <40>;
  82. mmu-type = "riscv,sv39";
  83. next-level-cache = <&cachectrl>;
  84. riscv,isa = "rv64imafdcbsux";
  85. tlb-split;
  86. status = "okay";
  87. cpu2intctrl: interrupt-controller {
  88. #interrupt-cells = <1>;
  89. compatible = "riscv,cpu-intc";
  90. interrupt-controller;
  91. };
  92. };
  93. cpu3: cpu@3 {
  94. compatible = "sifive,u74-mc", "riscv";
  95. reg = <3>;
  96. d-cache-block-size = <64>;
  97. d-cache-sets = <64>;
  98. d-cache-size = <32768>;
  99. d-tlb-sets = <1>;
  100. d-tlb-size = <40>;
  101. device_type = "cpu";
  102. i-cache-block-size = <64>;
  103. i-cache-sets = <64>;
  104. i-cache-size = <32768>;
  105. i-tlb-sets = <1>;
  106. i-tlb-size = <40>;
  107. mmu-type = "riscv,sv39";
  108. next-level-cache = <&cachectrl>;
  109. riscv,isa = "rv64imafdcbsux";
  110. tlb-split;
  111. status = "okay";
  112. cpu3intctrl: interrupt-controller {
  113. #interrupt-cells = <1>;
  114. compatible = "riscv,cpu-intc";
  115. interrupt-controller;
  116. };
  117. };
  118. cpu4: cpu@4 {
  119. compatible = "sifive,u74-mc", "riscv";
  120. reg = <4>;
  121. d-cache-block-size = <64>;
  122. d-cache-sets = <64>;
  123. d-cache-size = <32768>;
  124. d-tlb-sets = <1>;
  125. d-tlb-size = <40>;
  126. device_type = "cpu";
  127. i-cache-block-size = <64>;
  128. i-cache-sets = <64>;
  129. i-cache-size = <32768>;
  130. i-tlb-sets = <1>;
  131. i-tlb-size = <40>;
  132. mmu-type = "riscv,sv39";
  133. next-level-cache = <&cachectrl>;
  134. riscv,isa = "rv64imafdcbsux";
  135. tlb-split;
  136. status = "okay";
  137. cpu4intctrl: interrupt-controller {
  138. #interrupt-cells = <1>;
  139. compatible = "riscv,cpu-intc";
  140. interrupt-controller;
  141. };
  142. };
  143. };
  144. soc: soc {
  145. compatible = "simple-bus";
  146. interrupt-parent = <&plic>;
  147. #address-cells = <2>;
  148. #size-cells = <2>;
  149. #clock-cells = <1>;
  150. ranges;
  151. cachectrl: cache-controller@2010000 {
  152. compatible = "sifive,fu740-c000-ccache", "cache";
  153. reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
  154. reg-names = "control", "sideband";
  155. interrupts = <1 3 4 2>;
  156. cache-block-size = <64>;
  157. cache-level = <2>;
  158. cache-sets = <2048>;
  159. cache-size = <2097152>;
  160. cache-unified;
  161. };
  162. aon_syscon: aon_syscon@17010000 {
  163. compatible = "syscon";
  164. reg = <0x0 0x17010000 0x0 0x1000>;
  165. };
  166. stg_syscon: stg_syscon@10240000 {
  167. compatible = "syscon";
  168. reg = <0x0 0x10240000 0x0 0x1000>;
  169. };
  170. sys_syscon: sys_syscon@13030000 {
  171. compatible = "syscon";
  172. reg = <0x0 0x13030000 0x0 0x1000>;
  173. };
  174. clint: clint@2000000 {
  175. compatible = "riscv,clint0";
  176. reg = <0x0 0x2000000 0x0 0x10000>;
  177. reg-names = "control";
  178. interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
  179. &cpu1intctrl 3 &cpu1intctrl 7
  180. &cpu2intctrl 3 &cpu2intctrl 7
  181. &cpu3intctrl 3 &cpu3intctrl 7
  182. &cpu4intctrl 3 &cpu4intctrl 7>;
  183. #interrupt-cells = <1>;
  184. };
  185. plic: plic@c000000 {
  186. compatible = "riscv,plic0";
  187. reg = <0x0 0xc000000 0x0 0x4000000>;
  188. reg-names = "control";
  189. interrupts-extended = <&cpu0intctrl 11
  190. &cpu1intctrl 11 &cpu1intctrl 9
  191. &cpu2intctrl 11 &cpu2intctrl 9
  192. &cpu3intctrl 11 &cpu3intctrl 9
  193. &cpu4intctrl 11 &cpu4intctrl 9>;
  194. interrupt-controller;
  195. #interrupt-cells = <1>;
  196. riscv,max-priority = <7>;
  197. riscv,ndev = <136>;
  198. };
  199. clkgen: clock-controller {
  200. compatible = "starfive,jh7110-clkgen";
  201. reg = <0x0 0x13020000 0x0 0x10000>,
  202. <0x0 0x10230000 0x0 0x10000>,
  203. <0x0 0x17000000 0x0 0x10000>;
  204. reg-names = "sys", "stg", "aon";
  205. clocks = <&osc>, <&gmac1_rmii_refin>,
  206. <&gmac1_rgmii_rxin>,
  207. <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
  208. <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
  209. <&tdm_ext>, <&mclk_ext>,
  210. <&jtag_tck_inner>, <&bist_apb>,
  211. <&stg_apb>, <&clk_rtc>,
  212. <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
  213. clock-names = "osc", "gmac1_rmii_refin",
  214. "gmac1_rgmii_rxin",
  215. "i2stx_bclk_ext", "i2stx_lrck_ext",
  216. "i2srx_bclk_ext", "i2srx_lrck_ext",
  217. "tdm_ext", "mclk_ext",
  218. "jtag_tck_inner", "bist_apb",
  219. "stg_apb", "clk_rtc",
  220. "gmac0_rmii_refin", "gmac0_rgmii_rxin";
  221. #clock-cells = <1>;
  222. status = "okay";
  223. };
  224. clkvout: clock-controller@295C0000 {
  225. compatible = "starfive,jh7110-clk-vout";
  226. reg = <0x0 0x295C0000 0x0 0x10000>;
  227. reg-names = "vout";
  228. clocks = <&hdmitx0_pixelclk>,
  229. <&mipitx_dphy_rxesc>,
  230. <&mipitx_dphy_txbytehs>;
  231. clock-names = "hdmitx0_pixelclk",
  232. "mipitx_dphy_rxesc",
  233. "mipitx_dphy_txbytehs";
  234. #clock-cells = <1>;
  235. status = "okay";
  236. };
  237. clkisp: clock-controller@19810000 {
  238. compatible = "starfive,jh7110-clk-isp";
  239. reg = <0x0 0x19810000 0x0 0x10000>;
  240. reg-names = "isp";
  241. #clock-cells = <1>;
  242. clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
  243. <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
  244. <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
  245. clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
  246. "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
  247. "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi";
  248. resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
  249. <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
  250. reset-names = "rst_isp_top_n", "rst_isp_top_axi";
  251. status = "disabled";
  252. };
  253. qspi: spi@13010000 {
  254. compatible = "cdns,qspi-nor";
  255. #address-cells = <1>;
  256. #size-cells = <0>;
  257. reg = <0x0 0x13010000 0x0 0x10000
  258. 0x0 0x21000000 0x0 0x400000>;
  259. clocks = <&clkgen JH7110_QSPI_CLK_REF>;
  260. clock-names = "clk_ref";
  261. resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
  262. <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
  263. <&rstgen RSTN_U0_CDNS_QSPI_REF>;
  264. resets-names = "rst_apb", "rst_ahb", "rst_ref";
  265. cdns,fifo-depth = <256>;
  266. cdns,fifo-width = <4>;
  267. spi-max-frequency = <250000000>;
  268. nor_flash: nor-flash@0 {
  269. compatible = "jedec,spi-nor";
  270. reg=<0>;
  271. spi-max-frequency = <100000000>;
  272. cdns,tshsl-ns = <1>;
  273. cdns,tsd2d-ns = <1>;
  274. cdns,tchsh-ns = <1>;
  275. cdns,tslch-ns = <1>;
  276. };
  277. };
  278. otp: otp@17050000 {
  279. compatible = "starfive,jh7110-otp";
  280. reg = <0x0 0x17050000 0x0 0x10000>;
  281. clock-frequency = <4000000>;
  282. clocks = <&clkgen JH7110_OTPC_CLK_APB>;
  283. clock-names = "apb";
  284. };
  285. usbdrd30: usbdrd{
  286. compatible = "starfive,jh7110-cdns3";
  287. #address-cells = <2>;
  288. #size-cells = <2>;
  289. clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
  290. <&clkgen JH7110_USB0_CLK_LPM>,
  291. <&clkgen JH7110_USB0_CLK_STB>,
  292. <&clkgen JH7110_USB0_CLK_USB_APB>,
  293. <&clkgen JH7110_USB0_CLK_AXI>,
  294. <&clkgen JH7110_USB0_CLK_UTMI_APB>;
  295. clock-names = "app","lpm","stb","apb","axi","utmi";
  296. resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
  297. <&rstgen RSTN_U0_CDN_USB_APB>,
  298. <&rstgen RSTN_U0_CDN_USB_AXI>,
  299. <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
  300. reset-names = "pwrup","apb","axi","utmi";
  301. starfive,stg-syscon = <&stg_syscon 0x4>;
  302. starfive,sys-syscon = <&sys_syscon 0x18>;
  303. status = "disabled";
  304. usbdrd_cdns3: usb@10100000 {
  305. compatible = "cdns,usb3";
  306. reg = <0x0 0x10100000 0x0 0x10000>,
  307. <0x0 0x10110000 0x0 0x10000>,
  308. <0x0 0x10120000 0x0 0x10000>;
  309. reg-names = "otg", "xhci", "dev";
  310. interrupts = <108>, <109>, <110>;
  311. interrupt-names = "host", "peripheral", "otg";
  312. phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
  313. maximum-speed = "super-speed";
  314. };
  315. };
  316. timer: timer@13050000 {
  317. compatible = "starfive,si5-timers";
  318. reg = <0x0 0x13050000 0x0 0x10000>;
  319. interrupts = <69>, <70>, <71> ,<72>;
  320. interrupt-names = "timer0", "timer1",
  321. "timer2", "timer3";
  322. clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
  323. <&clkgen JH7110_TIMER_CLK_TIMER1>,
  324. <&clkgen JH7110_TIMER_CLK_TIMER2>,
  325. <&clkgen JH7110_TIMER_CLK_TIMER3>,
  326. <&clkgen JH7110_TIMER_CLK_APB>;
  327. clock-names = "timer0", "timer1",
  328. "timer2", "timer3", "apb_clk";
  329. clock-frequency = <2000000>;
  330. status = "okay";
  331. };
  332. wdog: wdog@13070000 {
  333. compatible = "starfive,dskit-wdt";
  334. reg = <0x0 0x13070000 0x0 0x10000>;
  335. interrupts = <68>;
  336. interrupt-names = "wdog";
  337. clock-frequency = <2000000>;
  338. clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
  339. <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
  340. clock-names = "core_clk", "apb_clk";
  341. resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
  342. <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
  343. reset-names = "rst_apb", "rst_core";
  344. timeout-sec = <15>;
  345. status = "okay";
  346. };
  347. rtc: rtc@17040000 {
  348. compatible = "starfive,rtc_hms";
  349. reg = <0x0 0x17040000 0x0 0x10000>;
  350. interrupts = <10>, <11>, <12>;
  351. interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
  352. clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
  353. <&clkgen JH7110_RTC_HMS_CLK_CAL>;
  354. clock-names = "pclk", "cal_clk";
  355. resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
  356. <&rstgen RSTN_U0_RTC_HMS_CAL>,
  357. <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
  358. reset-names = "rst_apb", "rst_cal", "rst_osc";
  359. rtc,cal-clock-freq = <1000000>;
  360. status = "okay";
  361. };
  362. pmu: pmu@17030000 {
  363. compatible = "starfive,jh7110-pmu";
  364. reg = <0x0 0x17030000 0x0 0x10000>;
  365. interrupts = <111>;
  366. status = "okay";
  367. };
  368. uart0: serial@10000000 {
  369. compatible = "snps,dw-apb-uart";
  370. reg = <0x0 0x10000000 0x0 0x10000>;
  371. reg-io-width = <4>;
  372. reg-shift = <2>;
  373. clocks = <&clkgen JH7110_UART0_CLK_CORE>,
  374. <&clkgen JH7110_UART0_CLK_APB>;
  375. clock-names = "baudclk", "apb_pclk";
  376. resets = <&rstgen RSTN_U0_DW_UART_APB>,
  377. <&rstgen RSTN_U0_DW_UART_CORE>;
  378. interrupts = <32>;
  379. status = "disabled";
  380. };
  381. uart1: serial@10010000 {
  382. compatible = "snps,dw-apb-uart";
  383. reg = <0x0 0x10010000 0x0 0x10000>;
  384. reg-io-width = <4>;
  385. reg-shift = <2>;
  386. clocks = <&clkgen JH7110_UART1_CLK_CORE>,
  387. <&clkgen JH7110_UART1_CLK_APB>;
  388. clock-names = "baudclk", "apb_pclk";
  389. resets = <&rstgen RSTN_U1_DW_UART_APB>,
  390. <&rstgen RSTN_U1_DW_UART_CORE>;
  391. interrupts = <33>;
  392. status = "disabled";
  393. };
  394. uart2: serial@10020000 {
  395. compatible = "snps,dw-apb-uart";
  396. reg = <0x0 0x10020000 0x0 0x10000>;
  397. reg-io-width = <4>;
  398. reg-shift = <2>;
  399. clocks = <&clkgen JH7110_UART2_CLK_CORE>,
  400. <&clkgen JH7110_UART2_CLK_APB>;
  401. clock-names = "baudclk", "apb_pclk";
  402. resets = <&rstgen RSTN_U2_DW_UART_APB>,
  403. <&rstgen RSTN_U2_DW_UART_CORE>;
  404. interrupts = <34>;
  405. status = "disabled";
  406. };
  407. uart3: serial@12000000 {
  408. compatible = "snps,dw-apb-uart";
  409. reg = <0x0 0x12000000 0x0 0x10000>;
  410. reg-io-width = <4>;
  411. reg-shift = <2>;
  412. clocks = <&clkgen JH7110_UART3_CLK_CORE>,
  413. <&clkgen JH7110_UART3_CLK_APB>;
  414. clock-names = "baudclk", "apb_pclk";
  415. resets = <&rstgen RSTN_U3_DW_UART_APB>,
  416. <&rstgen RSTN_U3_DW_UART_CORE>;
  417. interrupts = <45>;
  418. status = "disabled";
  419. };
  420. uart4: serial@12010000 {
  421. compatible = "snps,dw-apb-uart";
  422. reg = <0x0 0x12010000 0x0 0x10000>;
  423. reg-io-width = <4>;
  424. reg-shift = <2>;
  425. clocks = <&clkgen JH7110_UART4_CLK_CORE>,
  426. <&clkgen JH7110_UART4_CLK_APB>;
  427. clock-names = "baudclk", "apb_pclk";
  428. resets = <&rstgen RSTN_U4_DW_UART_APB>,
  429. <&rstgen RSTN_U4_DW_UART_CORE>;
  430. interrupts = <46>;
  431. status = "disabled";
  432. };
  433. uart5: serial@12020000 {
  434. compatible = "snps,dw-apb-uart";
  435. reg = <0x0 0x12020000 0x0 0x10000>;
  436. reg-io-width = <4>;
  437. reg-shift = <2>;
  438. clocks = <&clkgen JH7110_UART5_CLK_CORE>,
  439. <&clkgen JH7110_UART5_CLK_APB>;
  440. clock-names = "baudclk", "apb_pclk";
  441. resets = <&rstgen RSTN_U5_DW_UART_APB>,
  442. <&rstgen RSTN_U5_DW_UART_CORE>;
  443. interrupts = <47>;
  444. status = "disabled";
  445. };
  446. dma: dma-controller@16050000 {
  447. compatible = "starfive,axi-dma";
  448. reg = <0x0 0x16050000 0x0 0x10000>;
  449. clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
  450. <&clkgen JH7110_DMA1P_CLK_AHB>;
  451. clock-names = "core-clk", "cfgr-clk";
  452. resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
  453. <&rstgen RSTN_U0_DW_DMA1P_AHB>;
  454. reset-names = "rst_axi", "rst_ahb";
  455. interrupts = <73>;
  456. #dma-cells = <2>;
  457. dma-channels = <4>;
  458. snps,dma-masters = <1>;
  459. snps,data-width = <3>;
  460. snps,num-hs-if = <56>;
  461. snps,block-size = <65536 65536 65536 65536>;
  462. snps,priority = <0 1 2 3>;
  463. snps,axi-max-burst-len = <16>;
  464. status = "disabled";
  465. };
  466. gpio: gpio@13040000 {
  467. compatible = "starfive,jh7110-sys-pinctrl";
  468. reg = <0x0 0x13040000 0x0 0x10000>;
  469. reg-names = "control";
  470. interrupts = <91>;
  471. interrupt-controller;
  472. #gpio-cells = <2>;
  473. ngpios = <64>;
  474. status = "okay";
  475. };
  476. gpioa: gpio@17020000 {
  477. compatible = "starfive,jh7110-aon-pinctrl";
  478. reg = <0x0 0x17020000 0x0 0x10000>;
  479. reg-names = "control";
  480. interrupts = <90>;
  481. interrupt-controller;
  482. #gpio-cells = <2>;
  483. ngpios = <4>;
  484. status = "okay";
  485. };
  486. trng: trng@1600C000 {
  487. compatible = "starfive,trng";
  488. reg = <0x0 0x1600C000 0x0 0x4000>;
  489. clocks = <&clkgen JH7110_SEC_HCLK>,
  490. <&clkgen JH7110_SEC_MISCAHB_CLK>;
  491. clock-names = "hclk", "miscahb_clk";
  492. resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
  493. interrupts = <30>;
  494. status = "disabled";
  495. };
  496. sec_dma: sec_dma@16008000 {
  497. /*compatible = "arm,pl080", "arm,primecell";*/
  498. compatible = "starfive,pl080";
  499. reg = <0x0 0x16008000 0x0 0x4000>;
  500. reg-names = "sec_dma";
  501. interrupts = <29>;
  502. clocks = <&clkgen JH7110_SEC_HCLK>,
  503. <&clkgen JH7110_SEC_MISCAHB_CLK>;
  504. clock-names = "sec_hclk","sec_ahb";
  505. resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
  506. reset-names = "sec_hre";
  507. lli-bus-interface-ahb1;
  508. mem-bus-interface-ahb1;
  509. memcpy-burst-size = <256>;
  510. memcpy-bus-width = <32>;
  511. #dma-cells = <2>;
  512. status = "disabled";
  513. };
  514. crypto: crypto@16000000 {
  515. compatible = "starfive,jh7110-sec";
  516. reg = <0x0 0x16000000 0x0 0x4000>,
  517. <0x0 0x16008000 0x0 0x4000>;
  518. reg-names = "secreg","secdma";
  519. interrupts = <28>, <29>;
  520. interrupt-names = "secirq", "dmairq";
  521. clocks = <&clkgen JH7110_SEC_HCLK>,
  522. <&clkgen JH7110_SEC_MISCAHB_CLK>;
  523. clock-names = "sec_hclk","sec_ahb";
  524. resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
  525. reset-names = "sec_hre";
  526. enable-dma = "true";
  527. dmas = <&sec_dma 1 2>,
  528. <&sec_dma 0 2>;
  529. dma-names = "sec_m","sec_p";
  530. status = "disabled";
  531. };
  532. i2c6: i2c@12060000 {
  533. compatible = "snps,designware-i2c";
  534. reg = <0x0 0x12060000 0x0 0x10000>;
  535. clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
  536. <&clkgen JH7110_I2C6_CLK_APB>;
  537. clock-names = "ref", "pclk";
  538. resets = <&rstgen RSTN_U6_DW_I2C_APB>;
  539. interrupts = <51>;
  540. #address-cells = <1>;
  541. #size-cells = <0>;
  542. status = "disabled";
  543. };
  544. i2c0: i2c@10030000 {
  545. compatible = "snps,designware-i2c";
  546. reg = <0x0 0x10030000 0x0 0x10000>;
  547. clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
  548. <&clkgen JH7110_I2C0_CLK_APB>;
  549. clock-names = "ref", "pclk";
  550. resets = <&rstgen RSTN_U0_DW_I2C_APB>;
  551. interrupts = <35>;
  552. #address-cells = <1>;
  553. #size-cells = <0>;
  554. status = "disabled";
  555. };
  556. i2c1: i2c@10040000 {
  557. compatible = "snps,designware-i2c";
  558. reg = <0x0 0x10040000 0x0 0x10000>;
  559. clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
  560. <&clkgen JH7110_I2C1_CLK_APB>;
  561. clock-names = "ref", "pclk";
  562. resets = <&rstgen RSTN_U1_DW_I2C_APB>;
  563. interrupts = <36>;
  564. #address-cells = <1>;
  565. #size-cells = <0>;
  566. status = "disabled";
  567. };
  568. /* unremovable emmc as mmcblk0 */
  569. sdio0: sdio0@16010000 {
  570. compatible = "snps,dw-mshc";
  571. reg = <0x0 0x16010000 0x0 0x10000>;
  572. clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
  573. <&clkgen JH7110_SDIO0_CLK_SDCARD>;
  574. clock-names = "biu","ciu";
  575. resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
  576. reset-names = "reset";
  577. };
  578. sdio1: sdio1@16020000 {
  579. compatible = "snps,dw-mshc";
  580. reg = <0x0 0x16020000 0x0 0x10000>;
  581. clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
  582. <&clkgen JH7110_SDIO1_CLK_SDCARD>;
  583. clock-names = "biu","ciu";
  584. resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
  585. reset-names = "reset";
  586. };
  587. vin_sysctl: vin_sysctl@19800000 {
  588. compatible = "starfive,stf-vin";
  589. reg = <0x0 0x19800000 0x0 0x10000>,
  590. <0x0 0x19810000 0x0 0x10000>,
  591. <0x0 0x19820000 0x0 0x10000>,
  592. <0x0 0x19830000 0x0 0x10000>,
  593. <0x0 0x19840000 0x0 0x10000>,
  594. <0x0 0x19870000 0x0 0x30000>,
  595. <0x0 0x198a0000 0x0 0x30000>,
  596. <0x0 0x11840000 0x0 0x10000>,
  597. <0x0 0x17030000 0x0 0x10000>,
  598. <0x0 0x13020000 0x0 0x10000>;
  599. reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
  600. "isp0", "isp1", "trst", "pmu", "syscrg";
  601. clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
  602. <&clkisp JH7110_U0_VIN_PCLK>,
  603. <&clkisp JH7110_U0_VIN_SYS_CLK>,
  604. <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
  605. <&clkisp JH7110_DVP_INV>,
  606. <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
  607. <&clkisp JH7110_MIPI_RX0_PXL>,
  608. <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
  609. <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
  610. <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
  611. <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>;
  612. clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
  613. "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
  614. "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
  615. "clk_pixel_clk_if1", "clk_pixel_clk_if2",
  616. "clk_pixel_clk_if3";
  617. resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
  618. <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
  619. <&rstgen RSTN_U0_VIN_N_PCLK>,
  620. <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
  621. <&rstgen RSTN_U0_VIN_P_AXIRD>,
  622. <&rstgen RSTN_U0_VIN_P_AXIWR>,
  623. <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
  624. <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
  625. <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
  626. <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
  627. <&rstgen RSTN_U0_M31DPHY_HW>,
  628. <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>;
  629. reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
  630. "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
  631. "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
  632. "rst_m31dphy_hw", "rst_m31dphy_b09_always_on";
  633. interrupts = <92 87 86>;
  634. status = "disabled";
  635. };
  636. jpu: jpu@11900000 {
  637. compatible = "starfive,jpu";
  638. reg = <0x0 0x13090000 0x0 0x300>;
  639. interrupts = <14>;
  640. clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
  641. <&clkgen JH7110_CODAJ12_CLK_CORE>,
  642. <&clkgen JH7110_CODAJ12_CLK_APB>;
  643. clock-names = "axi_clk", "core_clk", "apb_clk";
  644. resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
  645. <&rstgen RSTN_U0_CODAJ12_CORE>,
  646. <&rstgen RSTN_U0_CODAJ12_APB>;
  647. reset-names = "rst_axi", "rst_core", "rst_apb";
  648. status = "disabled";
  649. };
  650. vpu_dec: vpu_dec@130A0000 {
  651. compatible = "starfive,vdec";
  652. reg = <0x0 0x130A0000 0x0 0x10000>;
  653. interrupts = <13>;
  654. clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
  655. <&clkgen JH7110_WAVE511_CLK_BPU>,
  656. <&clkgen JH7110_WAVE511_CLK_VCE>,
  657. <&clkgen JH7110_WAVE511_CLK_APB>,
  658. <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
  659. clock-names = "axi_clk",
  660. "bpu_clk",
  661. "vce_clk",
  662. "apb_clk",
  663. "noc_bus";
  664. resets = <&rstgen RSTN_U0_WAVE511_AXI>,
  665. <&rstgen RSTN_U0_WAVE511_BPU>,
  666. <&rstgen RSTN_U0_WAVE511_VCE>,
  667. <&rstgen RSTN_U0_WAVE511_APB>,
  668. <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
  669. reset-names = "rst_axi",
  670. "rst_bpu",
  671. "rst_vce",
  672. "rst_apb",
  673. "rst_sram";
  674. starfive,vdec_noc_ctrl;
  675. status = "disabled";
  676. };
  677. vpu_enc: vpu_enc@130B0000 {
  678. compatible = "starfive,venc";
  679. reg = <0x0 0x130B0000 0x0 0x10000>;
  680. interrupts = <15>;
  681. clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
  682. <&clkgen JH7110_WAVE420L_CLK_BPU>,
  683. <&clkgen JH7110_WAVE420L_CLK_VCE>,
  684. <&clkgen JH7110_WAVE420L_CLK_APB>,
  685. <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
  686. clock-names = "axi_clk",
  687. "bpu_clk",
  688. "vce_clk",
  689. "apb_clk",
  690. "noc_bus";
  691. resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
  692. <&rstgen RSTN_U0_WAVE420L_BPU>,
  693. <&rstgen RSTN_U0_WAVE420L_VCE>,
  694. <&rstgen RSTN_U0_WAVE420L_APB>,
  695. <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
  696. reset-names = "rst_axi",
  697. "rst_bpu",
  698. "rst_vce",
  699. "rst_apb",
  700. "rst_sram";
  701. starfive,venc_noc_ctrl;
  702. status = "disabled";
  703. };
  704. rstgen: reset-controller {
  705. compatible = "starfive,jh7110-reset";
  706. reg = <0x0 0x13020000 0x0 0x10000>,
  707. <0x0 0x10230000 0x0 0x10000>,
  708. <0x0 0x17000000 0x0 0x10000>,
  709. <0x0 0x19810000 0x0 0x10000>,
  710. <0x0 0x295C0000 0x0 0x10000>;
  711. reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
  712. #reset-cells = <1>;
  713. status = "okay";
  714. };
  715. stmmac_axi_setup: stmmac-axi-config {
  716. snps,wr_osr_lmt = <0xf>;
  717. snps,rd_osr_lmt = <0xf>;
  718. snps,blen = <256 128 64 32 0 0 0>;
  719. };
  720. gmac0: ethernet@16030000 {
  721. compatible = "starfive,jh7110-eqos-5.20";
  722. reg = <0x0 0x16030000 0x0 0x10000>;
  723. clock-names = "gtx",
  724. "tx",
  725. "ptp_ref",
  726. "stmmaceth",
  727. "pclk",
  728. "gtxc";
  729. clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
  730. <&clkgen JH7110_U0_GMAC5_CLK_TX>,
  731. <&clkgen JH7110_GMAC0_PTP>,
  732. <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
  733. <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
  734. <&clkgen JH7110_GMAC0_GTXC>;
  735. resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
  736. <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
  737. reset-names = "ahb", "stmmaceth";
  738. interrupts = <7>, <6>, <5> ;
  739. interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
  740. max-frame-size = <9000>;
  741. phy-mode = "rgmii-id";
  742. snps,multicast-filter-bins = <256>;
  743. snps,perfect-filter-entries = <128>;
  744. rx-fifo-depth = <262144>;
  745. tx-fifo-depth = <131072>;
  746. snps,fixed-burst;
  747. snps,no-pbl-x8;
  748. snps,force_thresh_dma_mode;
  749. snps,axi-config = <&stmmac_axi_setup>;
  750. snps,tso;
  751. snps,en-tx-lpi-clockgating;
  752. snps,en-lpi;
  753. snps,write-requests = <2>;
  754. snps,read-requests = <16>;
  755. snps,burst-map = <0x7>;
  756. snps,txpbl = <16>;
  757. snps,rxpbl = <16>;
  758. status = "disabled";
  759. };
  760. gmac1: ethernet@16040000 {
  761. compatible = "starfive,jh7110-eqos-5.20";
  762. reg = <0x0 0x16040000 0x0 0x10000>;
  763. clock-names = "gtx",
  764. "tx",
  765. "ptp_ref",
  766. "stmmaceth",
  767. "pclk",
  768. "gtxc";
  769. clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
  770. <&clkgen JH7110_GMAC5_CLK_TX>,
  771. <&clkgen JH7110_GMAC5_CLK_PTP>,
  772. <&clkgen JH7110_GMAC5_CLK_AHB>,
  773. <&clkgen JH7110_GMAC5_CLK_AXI>,
  774. <&clkgen JH7110_GMAC1_GTXC>;
  775. resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
  776. <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
  777. reset-names = "ahb", "stmmaceth";
  778. interrupts = <78>, <77>, <76> ;
  779. interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
  780. max-frame-size = <9000>;
  781. phy-mode = "rgmii-id";
  782. snps,multicast-filter-bins = <256>;
  783. snps,perfect-filter-entries = <128>;
  784. rx-fifo-depth = <262144>;
  785. tx-fifo-depth = <131072>;
  786. snps,fixed-burst;
  787. snps,no-pbl-x8;
  788. snps,force_thresh_dma_mode;
  789. snps,axi-config = <&stmmac_axi_setup>;
  790. snps,tso;
  791. snps,en-tx-lpi-clockgating;
  792. snps,en-lpi;
  793. snps,write-requests = <2>;
  794. snps,read-requests = <16>;
  795. snps,burst-map = <0x7>;
  796. snps,txpbl = <16>;
  797. snps,rxpbl = <16>;
  798. status = "disabled";
  799. };
  800. gpu: gpu@18000000 {
  801. compatible = "img-gpu";
  802. reg = <0x0 0x18000000 0x0 0x100000>,
  803. <0x0 0x130C000 0x0 0x10000>;
  804. clocks = <&clkgen JH7110_GPU_CLK_APB>,
  805. <&clkgen JH7110_GPU_RTC_TOGGLE>,
  806. <&clkgen JH7110_GPU_CORE_CLK>,
  807. <&clkgen JH7110_GPU_SYS_CLK>,
  808. <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
  809. clock-names = "clk_apb", "clk_rtc",
  810. "clk_core", "clk_sys",
  811. "clk_axi";
  812. resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
  813. <&rstgen RSTN_U0_IMG_GPU_DOMA>;
  814. reset-names = "rst_apb", "rst_doma";
  815. interrupts = <82>;
  816. current-clock = <8000000>;
  817. status = "disabled";
  818. };
  819. can0: can@130d0000 {
  820. compatible = "ipms,can";
  821. reg = <0x0 0x130d0000 0x0 0x1000>;
  822. interrupts = <112>;
  823. clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
  824. <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
  825. <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
  826. clock-names = "apb_clk", "core_clk", "timer_clk";
  827. resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
  828. <&rstgen RSTN_U0_CAN_CTRL_CORE>,
  829. <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
  830. reset-names = "rst_apb", "rst_core", "rst_timer";
  831. starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
  832. syscon,can_or_canfd = <0>;
  833. status = "disabled";
  834. };
  835. can1: can@130e0000 {
  836. compatible = "ipms,can";
  837. reg = <0x0 0x130e0000 0x0 0x1000>;
  838. interrupts = <113>;
  839. clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
  840. <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
  841. <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
  842. clock-names = "apb_clk", "core_clk", "timer_clk";
  843. resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
  844. <&rstgen RSTN_U1_CAN_CTRL_CORE>,
  845. <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
  846. reset-names = "rst_apb", "rst_core", "rst_timer";
  847. starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
  848. syscon,can_or_canfd = <0>;
  849. status = "disabled";
  850. };
  851. tdm: tdm@10090000 {
  852. compatible = "starfive,sf-tdm";
  853. reg = <0x0 0x10090000 0x0 0x1000>;
  854. reg-names = "tdm";
  855. clocks = <&clkgen JH7110_AHB0>,
  856. <&clkgen JH7110_TDM_CLK_AHB>,
  857. <&clkgen JH7110_APB0>,
  858. <&clkgen JH7110_TDM_CLK_APB>,
  859. <&clkgen JH7110_TDM_INTERNAL>;
  860. clock-names = "clk_ahb0", "clk_tdm_ahb",
  861. "clk_apb0", "clk_tdm_apb",
  862. "clk_tdm_intl";
  863. resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
  864. <&rstgen RSTN_U0_TDM16SLOT_APB>,
  865. <&rstgen RSTN_U0_TDM16SLOT_TDM>;
  866. reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
  867. dmas = <&dma 20 1>, <&dma 21 1>;
  868. dma-names = "rx","tx";
  869. #sound-dai-cells = <0>;
  870. status = "disabled";
  871. };
  872. spdif0: spdif0@100a0000 {
  873. compatible = "starfive,sf-spdif";
  874. reg = <0x0 0x100a0000 0x0 0x1000>;
  875. clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
  876. <&clkgen JH7110_SPDIF_CLK_CORE>,
  877. <&clkgen JH7110_MCLK>;
  878. clock-names = "spdif-apb", "spdif-core", "audioclk";
  879. resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
  880. reset-names = "rst_apb";
  881. interrupts = <84>;
  882. interrupt-names = "tx";
  883. #sound-dai-cells = <0>;
  884. status = "disabled";
  885. };
  886. pwmdac: pwmdac@100b0000 {
  887. compatible = "starfive,pwmdac";
  888. reg = <0x0 0x100b0000 0x0 0x1000>;
  889. clocks = <&clkgen JH7110_APB0>,
  890. <&clkgen JH7110_PWMDAC_CLK_APB>,
  891. <&clkgen JH7110_PWMDAC_CLK_CORE>;
  892. clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
  893. resets = <&rstgen RSTN_U0_PWMDAC_APB>;
  894. reset-names = "rst-apb";
  895. dmas = <&dma 22 1>;
  896. dma-names = "tx";
  897. #sound-dai-cells = <0>;
  898. status = "disabled";
  899. };
  900. i2stx: i2stx@100c0000 {
  901. compatible = "snps,designware-i2stx";
  902. reg = <0x0 0x100c0000 0x0 0x1000>;
  903. clocks = <&clkgen JH7110_APB0>;
  904. clock-names = "i2sclk";
  905. interrupt-names = "tx";
  906. #sound-dai-cells = <0>;
  907. dmas = <&dma 28 1>;
  908. dma-names = "rx";
  909. status = "disabled";
  910. };
  911. pdm: pdm@100d0000 {
  912. compatible = "starfive,sf-pdm";
  913. reg = <0x0 0x100d0000 0x0 0x1000>;
  914. reg-names = "pdm";
  915. clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
  916. <&clkgen JH7110_APB0>,
  917. <&clkgen JH7110_PDM_CLK_APB>,
  918. <&clkgen JH7110_PDM_CLK_DMIC0_BCLK_SLV>,
  919. <&clkgen JH7110_PDM_CLK_DMIC0_LRCK_SLV>,
  920. <&clkgen JH7110_PDM_CLK_DMIC1_BCLK_SLV>,
  921. <&clkgen JH7110_PDM_CLK_DMIC1_LRCK_SLV>,
  922. <&clkgen JH7110_I2SRX0_3CH_BCLK>;
  923. clock-names = "pdm_dmic", "clk_apb0", "pdm_apb",
  924. "pdm_dmic0_bclk", "pdm_dmic0_lrck",
  925. "pdm_dmic1_bclk", "pdm_dmic1_lrck",
  926. "u0_i2srx_3ch_bclk";
  927. resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
  928. <&rstgen RSTN_U0_PDM_4MIC_APB>;
  929. reset-names = "pdm_dmic", "pdm_apb";
  930. #sound-dai-cells = <0>;
  931. };
  932. i2srx_3ch: i2srx_3ch@100e0000 {
  933. compatible = "snps,designware-i2srx";
  934. reg = <0x0 0x100e0000 0x0 0x1000>;
  935. clocks = <&clkgen JH7110_APB0>,
  936. <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
  937. <&clkgen JH7110_I2SRX_3CH_BCLK_MST>;
  938. clock-names = "apb0", "3ch-apb",
  939. "3ch-bclk";
  940. resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
  941. <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
  942. reset-names = "rst_apb_rx", "rst_bclk_rx";
  943. interrupts = <42>;
  944. interrupt-names = "rx";
  945. dmas = <&dma 24 1>;
  946. dma-names = "rx";
  947. #sound-dai-cells = <0>;
  948. status = "disabled";
  949. };
  950. i2stx_4ch0: i2stx_4ch0@120b0000 {
  951. compatible = "snps,designware-i2stx-4ch0";
  952. reg = <0x0 0x120b0000 0x0 0x1000>;
  953. clocks = <&clkgen JH7110_MCLK_INNER>,
  954. <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
  955. <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
  956. <&clkgen JH7110_MCLK>,
  957. <&clkgen JH7110_I2STX0_4CHBCLK>,
  958. <&clkgen JH7110_I2STX0_4CHLRCK>;
  959. clock-names = "inner", "bclk-mst",
  960. "lrck-mst", "mclk",
  961. "bclk0", "lrck0";
  962. resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
  963. <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
  964. reset-names = "rst_apb0", "rst_bclk0";
  965. interrupts = <58>;
  966. interrupt-names = "tx";
  967. dmas = <&dma 47 1>;
  968. dma-names = "tx";
  969. #sound-dai-cells = <0>;
  970. status = "disabled";
  971. };
  972. i2stx_4ch1: i2stx_4ch1@120c0000 {
  973. compatible = "snps,designware-i2stx-4ch1";
  974. reg = <0x0 0x120c0000 0x0 0x1000>;
  975. clocks = <&clkgen JH7110_MCLK_INNER>,
  976. <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
  977. <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
  978. <&clkgen JH7110_MCLK>,
  979. <&clkgen JH7110_I2STX1_4CHBCLK>,
  980. <&clkgen JH7110_I2STX1_4CHLRCK>;
  981. clock-names = "inner", "bclk-mst1",
  982. "lrck-mst1", "mclk",
  983. "bclk1", "lrck1";
  984. resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
  985. <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
  986. reset-names = "rst_apb1", "rst_bclk1";
  987. interrupts = <59>;
  988. interrupt-names = "tx";
  989. dmas = <&dma 48 1>;
  990. dma-names = "tx";
  991. #sound-dai-cells = <0>;
  992. status = "disabled";
  993. };
  994. ptc: pwm@120d0000 {
  995. compatible = "starfive,pwm0";
  996. reg = <0x0 0x120d0000 0x0 0x10000>;
  997. reg-names = "control";
  998. clocks = <&clkgen JH7110_PWM_CLK_APB>;
  999. resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
  1000. starfive,approx-period = <2000000>;
  1001. #pwm-cells=<3>;
  1002. starfive,npwm = <8>;
  1003. status = "disabled";
  1004. };
  1005. spdif_transmitter: spdif_transmitter {
  1006. compatible = "linux,spdif-dit";
  1007. #sound-dai-cells = <0>;
  1008. status = "disabled";
  1009. };
  1010. spdif_receiver: spdif_receiver {
  1011. compatible = "linux,spdif-dir";
  1012. #sound-dai-cells = <0>;
  1013. status = "disabled";
  1014. };
  1015. pwmdac_codec: pwmdac-transmitter {
  1016. compatible = "linux,pwmdac-dit";
  1017. #sound-dai-cells = <0>;
  1018. status = "disabled";
  1019. };
  1020. dmic_codec: dmic_codec {
  1021. compatible = "dmic-codec";
  1022. #sound-dai-cells = <0>;
  1023. status = "disabled";
  1024. };
  1025. spi0: spi@10060000 {
  1026. compatible = "arm,pl022", "arm,primecell";
  1027. reg = <0x0 0x10060000 0x0 0x10000>;
  1028. clocks = <&clkgen JH7110_SPI0_CLK_APB>;
  1029. clock-names = "apb_pclk";
  1030. resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
  1031. reset-names = "rst_apb";
  1032. interrupts = <38>;
  1033. dmas = <&dma 14 1>, <&dma 15 1>;
  1034. dma-names = "rx","tx";
  1035. arm,primecell-periphid = <0x00041022>;
  1036. num-cs = <1>;
  1037. #address-cells = <1>;
  1038. #size-cells = <0>;
  1039. status = "disabled";
  1040. };
  1041. pcie0: pcie@2B000000 {
  1042. compatible = "plda,pci-xpressrich3-axi";
  1043. #address-cells = <3>;
  1044. #size-cells = <2>;
  1045. #interrupt-cells = <1>;
  1046. reg = <0x0 0x2B000000 0x0 0x1000000
  1047. 0x9 0x40000000 0x0 0x10000000>;
  1048. reg-names = "reg", "config";
  1049. device_type = "pci";
  1050. starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
  1051. bus-range = <0x0 0xff>;
  1052. ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x06000000>;
  1053. msi-parent = <&plic>;
  1054. interrupts = <56>;
  1055. interrupt-controller;
  1056. interrupt-names = "msi";
  1057. interrupt-parent = <&plic>;
  1058. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  1059. interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
  1060. <0x0 0x0 0x0 0x2 &plic 0x2>,
  1061. <0x0 0x0 0x0 0x3 &plic 0x3>,
  1062. <0x0 0x0 0x0 0x4 &plic 0x4>;
  1063. resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
  1064. <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
  1065. <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
  1066. <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
  1067. <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
  1068. <&rstgen RSTN_U0_PLDA_PCIE_APB>;
  1069. reset-names = "rst_mst0", "rst_slv0", "rst_slv",
  1070. "rst_brg", "rst_core", "rst_apb";
  1071. clocks = <&clkgen JH7110_PCIE0_CLK_TL>,
  1072. <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
  1073. <&clkgen JH7110_PCIE0_CLK_APB>;
  1074. clock-names = "tl", "axi_mst0", "apb";
  1075. status = "disabled";
  1076. };
  1077. pcie1: pcie@2C000000 {
  1078. compatible = "plda,pci-xpressrich3-axi";
  1079. #address-cells = <3>;
  1080. #size-cells = <2>;
  1081. #interrupt-cells = <1>;
  1082. reg = <0x0 0x2C000000 0x0 0x1000000
  1083. 0x9 0xc0000000 0x0 0x10000000>;
  1084. reg-names = "reg", "config";
  1085. device_type = "pci";
  1086. starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
  1087. bus-range = <0x0 0xff>;
  1088. ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x06000000>;
  1089. msi-parent = <&plic>;
  1090. interrupts = <57>;
  1091. interrupt-controller;
  1092. interrupt-names = "msi";
  1093. interrupt-parent = <&plic>;
  1094. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  1095. interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
  1096. <0x0 0x0 0x0 0x2 &plic 0x2>,
  1097. <0x0 0x0 0x0 0x3 &plic 0x3>,
  1098. <0x0 0x0 0x0 0x4 &plic 0x4>;
  1099. resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
  1100. <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
  1101. <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
  1102. <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
  1103. <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
  1104. <&rstgen RSTN_U1_PLDA_PCIE_APB>;
  1105. reset-names = "rst_mst0", "rst_slv0", "rst_slv",
  1106. "rst_brg", "rst_core", "rst_apb";
  1107. clocks = <&clkgen JH7110_PCIE1_CLK_TL>,
  1108. <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
  1109. <&clkgen JH7110_PCIE1_CLK_APB>;
  1110. clock-names = "tl", "axi_mst0", "apb";
  1111. status = "disabled";
  1112. };
  1113. mailbox_contrl0: mailbox@0 {
  1114. compatible = "starfive,mail_box";
  1115. reg = <0x0 0x13060000 0x0 0x0001000>;
  1116. clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
  1117. clock-names = "clk_apb";
  1118. resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
  1119. reset-names = "mbx_rre";
  1120. interrupts = <26 27>;
  1121. #mbox-cells = <2>;
  1122. status = "disabled";
  1123. };
  1124. mailbox_client0: mailbox_client@0 {
  1125. compatible = "starfive,mailbox-test";
  1126. mbox-names = "rx", "tx";
  1127. mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
  1128. status = "disabled";
  1129. };
  1130. dssctrl: dssctrl@295B0000 {
  1131. compatible = "verisilicon,dss-ctrl", "syscon";
  1132. reg = <0 0x295B0000 0 0x90>;
  1133. };
  1134. hdmi_output: hdmi-output {
  1135. compatible = "verisilicon,hdmi-encoder";
  1136. verisilicon,dss-syscon = <&dssctrl>;
  1137. verisilicon,mux-mask = <0x70 0x380>;
  1138. verisilicon,mux-val = <0x40 0x280>;
  1139. status = "disabled";
  1140. };
  1141. dc8200: dc8200@29400000 {
  1142. compatible = "verisilicon,dc8200";
  1143. reg = <0x0 0x29400000 0x0 0x100>,
  1144. <0x0 0x29400800 0x0 0x2000>,
  1145. <0x0 0x17030000 0x0 0x1000>;
  1146. interrupts = <95>;
  1147. status = "disabled";
  1148. clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
  1149. <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
  1150. <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
  1151. <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
  1152. <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
  1153. <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
  1154. <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
  1155. <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
  1156. <&clkgen JH7110_VOUT_SRC>,
  1157. <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
  1158. <&clkgen JH7110_AHB1>,
  1159. <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
  1160. <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
  1161. <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
  1162. <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
  1163. <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
  1164. <&clkvout JH7110_U0_DC8200_CLK_AXI>,
  1165. <&clkvout JH7110_U0_DC8200_CLK_CORE>,
  1166. <&clkvout JH7110_U0_DC8200_CLK_AHB>;
  1167. clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
  1168. "noc_disp","noc_isp","noc_stg","vout_src",
  1169. "top_vout_axi","ahb1","top_vout_ahb",
  1170. "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
  1171. "axi_clk","core_clk","vout_ahb";
  1172. resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
  1173. <&rstgen RSTN_U0_DC8200_AXI>,
  1174. <&rstgen RSTN_U0_DC8200_AHB>,
  1175. <&rstgen RSTN_U0_DC8200_CORE>,
  1176. <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
  1177. <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
  1178. <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
  1179. <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
  1180. <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
  1181. <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
  1182. <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
  1183. <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
  1184. <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
  1185. <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
  1186. reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
  1187. "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
  1188. "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
  1189. "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
  1190. };
  1191. mipi_dphy: mipi-dphy@295e0000{
  1192. compatible = "starfive,jh7100-mipi-dphy-tx";
  1193. reg = <0x0 0x295e0000 0x0 0x10000>;
  1194. clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
  1195. clock-names = "dphy_txesc";
  1196. resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
  1197. <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
  1198. reset-names = "dphy_sys", "dphy_txbytehs";
  1199. #phy-cells = <0>;
  1200. status = "disabled";
  1201. };
  1202. mipi_dsi: mipi@295d0000 {
  1203. compatible = "cdns,dsi";
  1204. reg = <0x0 0x295d0000 0x0 0x10000>;
  1205. reg-names = "dsi";
  1206. clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
  1207. <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
  1208. <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
  1209. <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
  1210. clock-names = "sys", "apb", "txesc", "dpi";
  1211. resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
  1212. <&rstgen RSTN_U0_CDNS_DSITX_APB>,
  1213. <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
  1214. <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
  1215. <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
  1216. <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
  1217. reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
  1218. "dsi_sys", "dsi_txbytehs", "dsi_txesc";
  1219. phys = <&mipi_dphy>;
  1220. phy-names = "dphy";
  1221. status = "disabled";
  1222. port {
  1223. dsi_out_port: endpoint {
  1224. /*remote-endpoint = <&panel_dsi_port>;*/
  1225. };
  1226. };
  1227. mipi_panel: panel@0 {
  1228. /*compatible = "";*/
  1229. status = "disabled";
  1230. };
  1231. };
  1232. hdmi: hdmi@29590000 {
  1233. compatible = "rockchip,rk3036-inno-hdmi";
  1234. reg = <0x0 0x29590000 0x0 0x4000>;
  1235. /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
  1236. /*clocks = <&cru PCLK_HDMI>;*/
  1237. /*clock-names = "pclk";*/
  1238. /*pinctrl-names = "default";*/
  1239. /*pinctrl-0 = <&hdmi_ctl>;*/
  1240. status = "disabled";
  1241. clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
  1242. <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
  1243. <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>;
  1244. clock-names = "sysclk", "mclk", "bclk";
  1245. resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
  1246. reset-names = "hdmi_tx";
  1247. };
  1248. sound: snd-card {
  1249. compatible = "simple-audio-card";
  1250. simple-audio-card,name = "Starfive-Multi-Sound-Card";
  1251. #address-cells = <1>;
  1252. #size-cells = <0>;
  1253. simple-audio-card,dai-link@0 {
  1254. reg = <0>;
  1255. format = "left_j";
  1256. bitclock-master = <&sndcpu0>;
  1257. frame-master = <&sndcpu0>;
  1258. status = "okay";
  1259. sndcpu0: cpu {
  1260. sound-dai = <&pwmdac>;
  1261. };
  1262. codec {
  1263. sound-dai = <&pwmdac_codec>;
  1264. };
  1265. };
  1266. };
  1267. co_process: e24@0 {
  1268. compatible = "starfive,e24";
  1269. reg = <0x0 0xc0110000 0x0 0x00001000>,
  1270. <0x0 0xc0111000 0x0 0x0001f000>;
  1271. reg-names = "ecmd", "espace";
  1272. clocks = <&clkgen JH7110_E2_RTC_CLK>,
  1273. <&clkgen JH7110_E2_CLK_CORE>,
  1274. <&clkgen JH7110_E2_CLK_DBG>;
  1275. clock-names = "clk_rtc", "clk_core", "clk_dbg";
  1276. resets = <&rstgen RSTN_U0_E24_CORE>;
  1277. reset-names = "e24_core";
  1278. starfive,stg-syscon = <&stg_syscon>;
  1279. interrupt-parent = <&plic>;
  1280. firmware-name = "e24_elf";
  1281. irq-mode = <1>;
  1282. mbox-names = "tx", "rx";
  1283. mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
  1284. #address-cells = <1>;
  1285. #size-cells = <1>;
  1286. ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
  1287. status = "disabled";
  1288. dsp@0 {};
  1289. };
  1290. };
  1291. };