dw_mipi_dsi.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
  4. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  5. * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  6. * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  7. *
  8. * This generic Synopsys DesignWare MIPI DSI host driver is inspired from
  9. * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <dsi_host.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <panel.h>
  17. #include <video.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/gpio.h>
  20. #include <dm/device-internal.h>
  21. #include <dm/device_compat.h>
  22. #include <linux/bitops.h>
  23. #include <linux/delay.h>
  24. #include <linux/iopoll.h>
  25. #include <video_bridge.h>
  26. #define HWVER_131 0x31333100 /* IP version 1.31 */
  27. #define DSI_VERSION 0x00
  28. #define VERSION GENMASK(31, 8)
  29. #define DSI_PWR_UP 0x04
  30. #define RESET 0
  31. #define POWERUP BIT(0)
  32. #define DSI_CLKMGR_CFG 0x08
  33. #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
  34. #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
  35. #define DSI_DPI_VCID 0x0c
  36. #define DPI_VCID(vcid) ((vcid) & 0x3)
  37. #define DSI_DPI_COLOR_CODING 0x10
  38. #define LOOSELY18_EN BIT(8)
  39. #define DPI_COLOR_CODING_16BIT_1 0x0
  40. #define DPI_COLOR_CODING_16BIT_2 0x1
  41. #define DPI_COLOR_CODING_16BIT_3 0x2
  42. #define DPI_COLOR_CODING_18BIT_1 0x3
  43. #define DPI_COLOR_CODING_18BIT_2 0x4
  44. #define DPI_COLOR_CODING_24BIT 0x5
  45. #define DSI_DPI_CFG_POL 0x14
  46. #define COLORM_ACTIVE_LOW BIT(4)
  47. #define SHUTD_ACTIVE_LOW BIT(3)
  48. #define HSYNC_ACTIVE_LOW BIT(2)
  49. #define VSYNC_ACTIVE_LOW BIT(1)
  50. #define DATAEN_ACTIVE_LOW BIT(0)
  51. #define DSI_DPI_LP_CMD_TIM 0x18
  52. #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
  53. #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
  54. #define DSI_DBI_VCID 0x1c
  55. #define DSI_DBI_CFG 0x20
  56. #define DSI_DBI_PARTITIONING_EN 0x24
  57. #define DSI_DBI_CMDSIZE 0x28
  58. #define DSI_PCKHDL_CFG 0x2c
  59. #define CRC_RX_EN BIT(4)
  60. #define ECC_RX_EN BIT(3)
  61. #define BTA_EN BIT(2)
  62. #define EOTP_RX_EN BIT(1)
  63. #define EOTP_TX_EN BIT(0)
  64. #define DSI_GEN_VCID 0x30
  65. #define DSI_MODE_CFG 0x34
  66. #define ENABLE_VIDEO_MODE 0
  67. #define ENABLE_CMD_MODE BIT(0)
  68. #define DSI_VID_MODE_CFG 0x38
  69. #define ENABLE_LOW_POWER (0x3f << 8)
  70. #define ENABLE_LOW_POWER_MASK (0x3f << 8)
  71. #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
  72. #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
  73. #define VID_MODE_TYPE_BURST 0x2
  74. #define VID_MODE_TYPE_MASK 0x3
  75. #define DSI_VID_PKT_SIZE 0x3c
  76. #define VID_PKT_SIZE(p) ((p) & 0x3fff)
  77. #define DSI_VID_NUM_CHUNKS 0x40
  78. #define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
  79. #define DSI_VID_NULL_SIZE 0x44
  80. #define VID_NULL_SIZE(b) ((b) & 0x1fff)
  81. #define DSI_VID_HSA_TIME 0x48
  82. #define DSI_VID_HBP_TIME 0x4c
  83. #define DSI_VID_HLINE_TIME 0x50
  84. #define DSI_VID_VSA_LINES 0x54
  85. #define DSI_VID_VBP_LINES 0x58
  86. #define DSI_VID_VFP_LINES 0x5c
  87. #define DSI_VID_VACTIVE_LINES 0x60
  88. #define DSI_EDPI_CMD_SIZE 0x64
  89. #define DSI_CMD_MODE_CFG 0x68
  90. #define MAX_RD_PKT_SIZE_LP BIT(24)
  91. #define DCS_LW_TX_LP BIT(19)
  92. #define DCS_SR_0P_TX_LP BIT(18)
  93. #define DCS_SW_1P_TX_LP BIT(17)
  94. #define DCS_SW_0P_TX_LP BIT(16)
  95. #define GEN_LW_TX_LP BIT(14)
  96. #define GEN_SR_2P_TX_LP BIT(13)
  97. #define GEN_SR_1P_TX_LP BIT(12)
  98. #define GEN_SR_0P_TX_LP BIT(11)
  99. #define GEN_SW_2P_TX_LP BIT(10)
  100. #define GEN_SW_1P_TX_LP BIT(9)
  101. #define GEN_SW_0P_TX_LP BIT(8)
  102. #define ACK_RQST_EN BIT(1)
  103. #define TEAR_FX_EN BIT(0)
  104. #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
  105. DCS_LW_TX_LP | \
  106. DCS_SR_0P_TX_LP | \
  107. DCS_SW_1P_TX_LP | \
  108. DCS_SW_0P_TX_LP | \
  109. GEN_LW_TX_LP | \
  110. GEN_SR_2P_TX_LP | \
  111. GEN_SR_1P_TX_LP | \
  112. GEN_SR_0P_TX_LP | \
  113. GEN_SW_2P_TX_LP | \
  114. GEN_SW_1P_TX_LP | \
  115. GEN_SW_0P_TX_LP)
  116. #define DSI_GEN_HDR 0x6c
  117. #define DSI_GEN_PLD_DATA 0x70
  118. #define DSI_CMD_PKT_STATUS 0x74
  119. #define GEN_RD_CMD_BUSY BIT(6)
  120. #define GEN_PLD_R_FULL BIT(5)
  121. #define GEN_PLD_R_EMPTY BIT(4)
  122. #define GEN_PLD_W_FULL BIT(3)
  123. #define GEN_PLD_W_EMPTY BIT(2)
  124. #define GEN_CMD_FULL BIT(1)
  125. #define GEN_CMD_EMPTY BIT(0)
  126. #define DSI_TO_CNT_CFG 0x78
  127. #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
  128. #define LPRX_TO_CNT(p) ((p) & 0xffff)
  129. #define DSI_HS_RD_TO_CNT 0x7c
  130. #define DSI_LP_RD_TO_CNT 0x80
  131. #define DSI_HS_WR_TO_CNT 0x84
  132. #define DSI_LP_WR_TO_CNT 0x88
  133. #define DSI_BTA_TO_CNT 0x8c
  134. #define DSI_LPCLK_CTRL 0x94
  135. #define AUTO_CLKLANE_CTRL BIT(1)
  136. #define PHY_TXREQUESTCLKHS BIT(0)
  137. #define DSI_PHY_TMR_LPCLK_CFG 0x98
  138. #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
  139. #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
  140. #define DSI_PHY_TMR_CFG 0x9c
  141. #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
  142. #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
  143. #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
  144. #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
  145. #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
  146. #define DSI_PHY_RSTZ 0xa0
  147. #define PHY_DISFORCEPLL 0
  148. #define PHY_ENFORCEPLL BIT(3)
  149. #define PHY_DISABLECLK 0
  150. #define PHY_ENABLECLK BIT(2)
  151. #define PHY_RSTZ 0
  152. #define PHY_UNRSTZ BIT(1)
  153. #define PHY_SHUTDOWNZ 0
  154. #define PHY_UNSHUTDOWNZ BIT(0)
  155. #define DSI_PHY_IF_CFG 0xa4
  156. #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
  157. #define N_LANES(n) (((n) - 1) & 0x3)
  158. #define DSI_PHY_ULPS_CTRL 0xa8
  159. #define DSI_PHY_TX_TRIGGERS 0xac
  160. #define DSI_PHY_STATUS 0xb0
  161. #define PHY_STOP_STATE_CLK_LANE BIT(2)
  162. #define PHY_LOCK BIT(0)
  163. #define DSI_PHY_TST_CTRL0 0xb4
  164. #define PHY_TESTCLK BIT(1)
  165. #define PHY_UNTESTCLK 0
  166. #define PHY_TESTCLR BIT(0)
  167. #define PHY_UNTESTCLR 0
  168. #define DSI_PHY_TST_CTRL1 0xb8
  169. #define PHY_TESTEN BIT(16)
  170. #define PHY_UNTESTEN 0
  171. #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
  172. #define PHY_TESTDIN(n) ((n) & 0xff)
  173. #define DSI_INT_ST0 0xbc
  174. #define DSI_INT_ST1 0xc0
  175. #define DSI_INT_MSK0 0xc4
  176. #define DSI_INT_MSK1 0xc8
  177. #define DSI_PHY_TMR_RD_CFG 0xf4
  178. #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
  179. #define PHY_STATUS_TIMEOUT_US 10000
  180. #define CMD_PKT_STATUS_TIMEOUT_US 20000
  181. #define MSEC_PER_SEC 1000
  182. struct dw_mipi_dsi {
  183. struct mipi_dsi_host dsi_host;
  184. struct mipi_dsi_device *device;
  185. void __iomem *base;
  186. unsigned int lane_mbps; /* per lane */
  187. u32 channel;
  188. unsigned int max_data_lanes;
  189. const struct mipi_dsi_phy_ops *phy_ops;
  190. };
  191. static int dsi_mode_vrefresh(struct display_timing *timings)
  192. {
  193. int refresh = 0;
  194. unsigned int calc_val;
  195. u32 htotal = timings->hactive.typ + timings->hfront_porch.typ +
  196. timings->hback_porch.typ + timings->hsync_len.typ;
  197. u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ +
  198. timings->vback_porch.typ + timings->vsync_len.typ;
  199. if (htotal > 0 && vtotal > 0) {
  200. calc_val = timings->pixelclock.typ;
  201. calc_val /= htotal;
  202. refresh = (calc_val + vtotal / 2) / vtotal;
  203. }
  204. return refresh;
  205. }
  206. /*
  207. * The controller should generate 2 frames before
  208. * preparing the peripheral.
  209. */
  210. static void dw_mipi_dsi_wait_for_two_frames(struct display_timing *timings)
  211. {
  212. int refresh, two_frames;
  213. refresh = dsi_mode_vrefresh(timings);
  214. two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
  215. mdelay(two_frames);
  216. }
  217. static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
  218. {
  219. return container_of(host, struct dw_mipi_dsi, dsi_host);
  220. }
  221. static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
  222. {
  223. writel(val, dsi->base + reg);
  224. }
  225. static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
  226. {
  227. return readl(dsi->base + reg);
  228. }
  229. static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
  230. struct mipi_dsi_device *device)
  231. {
  232. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  233. if (device->lanes > dsi->max_data_lanes) {
  234. dev_err(device->dev,
  235. "the number of data lanes(%u) is too many\n",
  236. device->lanes);
  237. return -EINVAL;
  238. }
  239. dsi->channel = device->channel;
  240. return 0;
  241. }
  242. static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
  243. const struct mipi_dsi_msg *msg)
  244. {
  245. bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
  246. u32 val = 0;
  247. if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
  248. val |= ACK_RQST_EN;
  249. if (lpm)
  250. val |= CMD_MODE_ALL_LP;
  251. dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
  252. dsi_write(dsi, DSI_CMD_MODE_CFG, val);
  253. }
  254. static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
  255. {
  256. int ret;
  257. u32 val, mask;
  258. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  259. val, !(val & GEN_CMD_FULL),
  260. CMD_PKT_STATUS_TIMEOUT_US);
  261. if (ret) {
  262. dev_err(dsi->dev, "failed to get available command FIFO\n");
  263. return ret;
  264. }
  265. dsi_write(dsi, DSI_GEN_HDR, hdr_val);
  266. mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
  267. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  268. val, (val & mask) == mask,
  269. CMD_PKT_STATUS_TIMEOUT_US);
  270. if (ret) {
  271. dev_err(dsi->dev, "failed to write command FIFO\n");
  272. return ret;
  273. }
  274. return 0;
  275. }
  276. static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
  277. const struct mipi_dsi_packet *packet)
  278. {
  279. const u8 *tx_buf = packet->payload;
  280. int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
  281. __le32 word;
  282. u32 val;
  283. while (len) {
  284. if (len < pld_data_bytes) {
  285. word = 0;
  286. memcpy(&word, tx_buf, len);
  287. dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
  288. len = 0;
  289. } else {
  290. memcpy(&word, tx_buf, pld_data_bytes);
  291. dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
  292. tx_buf += pld_data_bytes;
  293. len -= pld_data_bytes;
  294. }
  295. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  296. val, !(val & GEN_PLD_W_FULL),
  297. CMD_PKT_STATUS_TIMEOUT_US);
  298. if (ret) {
  299. dev_err(dsi->dev,
  300. "failed to get available write payload FIFO\n");
  301. return ret;
  302. }
  303. }
  304. word = 0;
  305. memcpy(&word, packet->header, sizeof(packet->header));
  306. return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
  307. }
  308. static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
  309. const struct mipi_dsi_msg *msg)
  310. {
  311. int i, j, ret, len = msg->rx_len;
  312. u8 *buf = msg->rx_buf;
  313. u32 val;
  314. /* Wait end of the read operation */
  315. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  316. val, !(val & GEN_RD_CMD_BUSY),
  317. CMD_PKT_STATUS_TIMEOUT_US);
  318. if (ret) {
  319. dev_err(dsi->dev, "Timeout during read operation\n");
  320. return ret;
  321. }
  322. for (i = 0; i < len; i += 4) {
  323. /* Read fifo must not be empty before all bytes are read */
  324. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  325. val, !(val & GEN_PLD_R_EMPTY),
  326. CMD_PKT_STATUS_TIMEOUT_US);
  327. if (ret) {
  328. dev_err(dsi->dev, "Read payload FIFO is empty\n");
  329. return ret;
  330. }
  331. val = dsi_read(dsi, DSI_GEN_PLD_DATA);
  332. for (j = 0; j < 4 && j + i < len; j++)
  333. buf[i + j] = val >> (8 * j);
  334. }
  335. return ret;
  336. }
  337. static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
  338. const struct mipi_dsi_msg *msg)
  339. {
  340. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  341. struct mipi_dsi_packet packet;
  342. int ret, nb_bytes;
  343. ret = mipi_dsi_create_packet(&packet, msg);
  344. if (ret) {
  345. dev_err(dsi->dev, "failed to create packet: %d\n", ret);
  346. return ret;
  347. }
  348. dw_mipi_message_config(dsi, msg);
  349. ret = dw_mipi_dsi_write(dsi, &packet);
  350. if (ret)
  351. return ret;
  352. if (msg->rx_buf && msg->rx_len) {
  353. ret = dw_mipi_dsi_read(dsi, msg);
  354. if (ret)
  355. return ret;
  356. nb_bytes = msg->rx_len;
  357. } else {
  358. nb_bytes = packet.size;
  359. }
  360. return nb_bytes;
  361. }
  362. static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
  363. .attach = dw_mipi_dsi_host_attach,
  364. .transfer = dw_mipi_dsi_host_transfer,
  365. };
  366. static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
  367. {
  368. struct mipi_dsi_device *device = dsi->device;
  369. u32 val;
  370. /*
  371. * TODO dw drv improvements
  372. * enabling low power is panel-dependent, we should use the
  373. * panel configuration here...
  374. */
  375. val = ENABLE_LOW_POWER;
  376. if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  377. val |= VID_MODE_TYPE_BURST;
  378. else if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  379. val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
  380. else
  381. val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
  382. dsi_write(dsi, DSI_VID_MODE_CFG, val);
  383. }
  384. static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
  385. unsigned long mode_flags)
  386. {
  387. const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
  388. dsi_write(dsi, DSI_PWR_UP, RESET);
  389. if (mode_flags & MIPI_DSI_MODE_VIDEO) {
  390. dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
  391. dw_mipi_dsi_video_mode_config(dsi);
  392. dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
  393. } else {
  394. dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
  395. }
  396. if (phy_ops->post_set_mode)
  397. phy_ops->post_set_mode(dsi->device, mode_flags);
  398. dsi_write(dsi, DSI_PWR_UP, POWERUP);
  399. }
  400. static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
  401. {
  402. /*
  403. * The maximum permitted escape clock is 20MHz and it is derived from
  404. * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
  405. *
  406. * (lane_mbps >> 3) / esc_clk_division < 20
  407. * which is:
  408. * (lane_mbps >> 3) / 20 > esc_clk_division
  409. */
  410. u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
  411. dsi_write(dsi, DSI_PWR_UP, RESET);
  412. /*
  413. * TODO dw drv improvements
  414. * timeout clock division should be computed with the
  415. * high speed transmission counter timeout and byte lane...
  416. */
  417. dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
  418. TX_ESC_CLK_DIVISION(esc_clk_division));
  419. }
  420. static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
  421. struct display_timing *timings)
  422. {
  423. struct mipi_dsi_device *device = dsi->device;
  424. u32 val = 0, color = 0;
  425. switch (device->format) {
  426. case MIPI_DSI_FMT_RGB888:
  427. color = DPI_COLOR_CODING_24BIT;
  428. break;
  429. case MIPI_DSI_FMT_RGB666:
  430. color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
  431. break;
  432. case MIPI_DSI_FMT_RGB666_PACKED:
  433. color = DPI_COLOR_CODING_18BIT_1;
  434. break;
  435. case MIPI_DSI_FMT_RGB565:
  436. color = DPI_COLOR_CODING_16BIT_1;
  437. break;
  438. }
  439. if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
  440. val |= VSYNC_ACTIVE_LOW;
  441. if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
  442. val |= HSYNC_ACTIVE_LOW;
  443. dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
  444. dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
  445. dsi_write(dsi, DSI_DPI_CFG_POL, val);
  446. /*
  447. * TODO dw drv improvements
  448. * largest packet sizes during hfp or during vsa/vpb/vfp
  449. * should be computed according to byte lane, lane number and only
  450. * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
  451. */
  452. dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
  453. | INVACT_LPCMD_TIME(4));
  454. }
  455. static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
  456. {
  457. dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
  458. }
  459. static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
  460. struct display_timing *timings)
  461. {
  462. /*
  463. * TODO dw drv improvements
  464. * only burst mode is supported here. For non-burst video modes,
  465. * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
  466. * DSI_VNPCR.NPSIZE... especially because this driver supports
  467. * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
  468. */
  469. dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
  470. }
  471. static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
  472. {
  473. const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
  474. /*
  475. * TODO dw drv improvements
  476. * compute high speed transmission counter timeout according
  477. * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
  478. */
  479. dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
  480. /*
  481. * TODO dw drv improvements
  482. * the Bus-Turn-Around Timeout Counter should be computed
  483. * according to byte lane...
  484. */
  485. dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
  486. dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
  487. if (phy_ops->post_set_mode)
  488. phy_ops->post_set_mode(dsi->device, 0);
  489. }
  490. /* Get lane byte clock cycles. */
  491. static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
  492. struct display_timing *timings,
  493. u32 hcomponent)
  494. {
  495. u32 frac, lbcc;
  496. lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
  497. frac = lbcc % (timings->pixelclock.typ / 1000);
  498. lbcc = lbcc / (timings->pixelclock.typ / 1000);
  499. if (frac)
  500. lbcc++;
  501. return lbcc;
  502. }
  503. static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
  504. struct display_timing *timings)
  505. {
  506. u32 htotal, hsa, hbp, lbcc;
  507. htotal = timings->hactive.typ + timings->hfront_porch.typ +
  508. timings->hback_porch.typ + timings->hsync_len.typ;
  509. hsa = timings->hback_porch.typ;
  510. hbp = timings->hsync_len.typ;
  511. /*
  512. * TODO dw drv improvements
  513. * computations below may be improved...
  514. */
  515. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
  516. dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
  517. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
  518. dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
  519. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
  520. dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
  521. }
  522. static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
  523. struct display_timing *timings)
  524. {
  525. u32 vactive, vsa, vfp, vbp;
  526. vactive = timings->vactive.typ;
  527. vsa = timings->vback_porch.typ;
  528. vfp = timings->vfront_porch.typ;
  529. vbp = timings->vsync_len.typ;
  530. dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
  531. dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
  532. dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
  533. dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
  534. }
  535. static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
  536. {
  537. u32 hw_version;
  538. /*
  539. * TODO dw drv improvements
  540. * data & clock lane timers should be computed according to panel
  541. * blankings and to the automatic clock lane control mode...
  542. * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
  543. * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
  544. */
  545. hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
  546. if (hw_version >= HWVER_131) {
  547. dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
  548. PHY_LP2HS_TIME_V131(0x40));
  549. dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
  550. } else {
  551. dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
  552. PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
  553. }
  554. dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
  555. | PHY_CLKLP2HS_TIME(0x40));
  556. }
  557. static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
  558. {
  559. struct mipi_dsi_device *device = dsi->device;
  560. /*
  561. * TODO dw drv improvements
  562. * stop wait time should be the maximum between host dsi
  563. * and panel stop wait times
  564. */
  565. dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
  566. N_LANES(device->lanes));
  567. }
  568. static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
  569. {
  570. /* Clear PHY state */
  571. dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
  572. | PHY_RSTZ | PHY_SHUTDOWNZ);
  573. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
  574. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
  575. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
  576. }
  577. static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
  578. {
  579. u32 val;
  580. int ret;
  581. dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
  582. PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
  583. ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
  584. val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
  585. if (ret)
  586. dev_warn(dsi->dev, "failed to wait phy lock state\n");
  587. ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
  588. val, val & PHY_STOP_STATE_CLK_LANE,
  589. PHY_STATUS_TIMEOUT_US);
  590. if (ret)
  591. dev_warn(dsi->dev, "failed to wait phy clk lane stop state\n");
  592. }
  593. static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
  594. {
  595. dsi_read(dsi, DSI_INT_ST0);
  596. dsi_read(dsi, DSI_INT_ST1);
  597. dsi_write(dsi, DSI_INT_MSK0, 0);
  598. dsi_write(dsi, DSI_INT_MSK1, 0);
  599. }
  600. static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
  601. struct display_timing *timings)
  602. {
  603. const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
  604. struct mipi_dsi_device *device = dsi->device;
  605. int ret;
  606. ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
  607. device->format, &dsi->lane_mbps);
  608. if (ret)
  609. dev_warn(dsi->dev, "Phy get_lane_mbps() failed\n");
  610. dw_mipi_dsi_init_pll(dsi);
  611. dw_mipi_dsi_dpi_config(dsi, timings);
  612. dw_mipi_dsi_packet_handler_config(dsi);
  613. dw_mipi_dsi_video_mode_config(dsi);
  614. dw_mipi_dsi_video_packet_config(dsi, timings);
  615. dw_mipi_dsi_command_mode_config(dsi);
  616. dw_mipi_dsi_line_timer_config(dsi, timings);
  617. dw_mipi_dsi_vertical_timing_config(dsi, timings);
  618. dw_mipi_dsi_dphy_init(dsi);
  619. dw_mipi_dsi_dphy_timing_config(dsi);
  620. dw_mipi_dsi_dphy_interface_config(dsi);
  621. dw_mipi_dsi_clear_err(dsi);
  622. ret = phy_ops->init(dsi->device);
  623. if (ret)
  624. dev_warn(dsi->dev, "Phy init() failed\n");
  625. dw_mipi_dsi_dphy_enable(dsi);
  626. dw_mipi_dsi_wait_for_two_frames(timings);
  627. /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
  628. dw_mipi_dsi_set_mode(dsi, 0);
  629. }
  630. static int dw_mipi_dsi_init(struct udevice *dev,
  631. struct mipi_dsi_device *device,
  632. struct display_timing *timings,
  633. unsigned int max_data_lanes,
  634. const struct mipi_dsi_phy_ops *phy_ops)
  635. {
  636. struct dw_mipi_dsi *dsi = dev_get_priv(dev);
  637. struct clk clk;
  638. int ret;
  639. if (!phy_ops->init || !phy_ops->get_lane_mbps) {
  640. dev_err(device->dev, "Phy not properly configured\n");
  641. return -ENODEV;
  642. }
  643. dsi->phy_ops = phy_ops;
  644. dsi->max_data_lanes = max_data_lanes;
  645. dsi->device = device;
  646. dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
  647. device->host = &dsi->dsi_host;
  648. dsi->base = (void *)dev_read_addr(device->dev);
  649. if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
  650. dev_err(device->dev, "dsi dt register address error\n");
  651. return -EINVAL;
  652. }
  653. ret = clk_get_by_name(device->dev, "px_clk", &clk);
  654. if (ret) {
  655. dev_err(device->dev, "peripheral clock get error %d\n", ret);
  656. return ret;
  657. }
  658. /* get the pixel clock set by the clock framework */
  659. timings->pixelclock.typ = clk_get_rate(&clk);
  660. dw_mipi_dsi_bridge_set(dsi, timings);
  661. return 0;
  662. }
  663. static int dw_mipi_dsi_enable(struct udevice *dev)
  664. {
  665. struct dw_mipi_dsi *dsi = dev_get_priv(dev);
  666. /* Switch to video mode for panel-bridge enable & panel enable */
  667. dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
  668. return 0;
  669. }
  670. struct dsi_host_ops dw_mipi_dsi_ops = {
  671. .init = dw_mipi_dsi_init,
  672. .enable = dw_mipi_dsi_enable,
  673. };
  674. static int dw_mipi_dsi_probe(struct udevice *dev)
  675. {
  676. return 0;
  677. }
  678. U_BOOT_DRIVER(dw_mipi_dsi) = {
  679. .name = "dw_mipi_dsi",
  680. .id = UCLASS_DSI_HOST,
  681. .probe = dw_mipi_dsi_probe,
  682. .ops = &dw_mipi_dsi_ops,
  683. .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi),
  684. };
  685. MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
  686. MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
  687. MODULE_AUTHOR("Yannick Fertré <yannick.fertre@st.com>");
  688. MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
  689. MODULE_LICENSE("GPL");
  690. MODULE_ALIAS("platform:dw-mipi-dsi");