da8xx-fb.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Porting to u-boot:
  4. *
  5. * (C) Copyright 2011
  6. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  7. *
  8. * Copyright (C) 2008-2009 MontaVista Software Inc.
  9. * Copyright (C) 2008-2009 Texas Instruments Inc
  10. *
  11. * Based on the LCD driver for TI Avalanche processors written by
  12. * Ajay Singh and Shalom Hai.
  13. */
  14. #include <common.h>
  15. #include <log.h>
  16. #include <malloc.h>
  17. #include <memalign.h>
  18. #include <video_fb.h>
  19. #include <linux/delay.h>
  20. #include <linux/list.h>
  21. #include <linux/fb.h>
  22. #include <linux/errno.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/hardware.h>
  25. #include "videomodes.h"
  26. #include "da8xx-fb.h"
  27. #if !defined(DA8XX_LCD_CNTL_BASE)
  28. #define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
  29. #endif
  30. #define DRIVER_NAME "da8xx_lcdc"
  31. #define LCD_VERSION_1 1
  32. #define LCD_VERSION_2 2
  33. /* LCD Status Register */
  34. #define LCD_END_OF_FRAME1 (1 << 9)
  35. #define LCD_END_OF_FRAME0 (1 << 8)
  36. #define LCD_PL_LOAD_DONE (1 << 6)
  37. #define LCD_FIFO_UNDERFLOW (1 << 5)
  38. #define LCD_SYNC_LOST (1 << 2)
  39. /* LCD DMA Control Register */
  40. #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
  41. #define LCD_DMA_BURST_1 0x0
  42. #define LCD_DMA_BURST_2 0x1
  43. #define LCD_DMA_BURST_4 0x2
  44. #define LCD_DMA_BURST_8 0x3
  45. #define LCD_DMA_BURST_16 0x4
  46. #define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
  47. #define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
  48. #define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
  49. #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
  50. #define LCD_V2_TFT_24BPP_MODE (1 << 25)
  51. #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
  52. /* LCD Control Register */
  53. #define LCD_CLK_DIVISOR(x) ((x) << 8)
  54. #define LCD_RASTER_MODE 0x01
  55. /* LCD Raster Control Register */
  56. #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
  57. #define PALETTE_AND_DATA 0x00
  58. #define PALETTE_ONLY 0x01
  59. #define DATA_ONLY 0x02
  60. #define LCD_MONO_8BIT_MODE (1 << 9)
  61. #define LCD_RASTER_ORDER (1 << 8)
  62. #define LCD_TFT_MODE (1 << 7)
  63. #define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
  64. #define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
  65. #define LCD_V1_PL_INT_ENA (1 << 4)
  66. #define LCD_V2_PL_INT_ENA (1 << 6)
  67. #define LCD_MONOCHROME_MODE (1 << 1)
  68. #define LCD_RASTER_ENABLE (1 << 0)
  69. #define LCD_TFT_ALT_ENABLE (1 << 23)
  70. #define LCD_STN_565_ENABLE (1 << 24)
  71. #define LCD_V2_DMA_CLK_EN (1 << 2)
  72. #define LCD_V2_LIDD_CLK_EN (1 << 1)
  73. #define LCD_V2_CORE_CLK_EN (1 << 0)
  74. #define LCD_V2_LPP_B10 26
  75. #define LCD_V2_TFT_24BPP_MODE (1 << 25)
  76. #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
  77. /* LCD Raster Timing 2 Register */
  78. #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
  79. #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
  80. #define LCD_SYNC_CTRL (1 << 25)
  81. #define LCD_SYNC_EDGE (1 << 24)
  82. #define LCD_INVERT_PIXEL_CLOCK (1 << 22)
  83. #define LCD_INVERT_LINE_CLOCK (1 << 21)
  84. #define LCD_INVERT_FRAME_CLOCK (1 << 20)
  85. /* Clock registers available only on Version 2 */
  86. #define LCD_CLK_MAIN_RESET (1 << 3)
  87. /* LCD Block */
  88. struct da8xx_lcd_regs {
  89. u32 revid;
  90. u32 ctrl;
  91. u32 stat;
  92. u32 lidd_ctrl;
  93. u32 lidd_cs0_conf;
  94. u32 lidd_cs0_addr;
  95. u32 lidd_cs0_data;
  96. u32 lidd_cs1_conf;
  97. u32 lidd_cs1_addr;
  98. u32 lidd_cs1_data;
  99. u32 raster_ctrl;
  100. u32 raster_timing_0;
  101. u32 raster_timing_1;
  102. u32 raster_timing_2;
  103. u32 raster_subpanel;
  104. u32 reserved;
  105. u32 dma_ctrl;
  106. u32 dma_frm_buf_base_addr_0;
  107. u32 dma_frm_buf_ceiling_addr_0;
  108. u32 dma_frm_buf_base_addr_1;
  109. u32 dma_frm_buf_ceiling_addr_1;
  110. u32 resv1;
  111. u32 raw_stat;
  112. u32 masked_stat;
  113. u32 int_ena_set;
  114. u32 int_ena_clr;
  115. u32 end_of_int_ind;
  116. /* Clock registers available only on Version 2 */
  117. u32 clk_ena;
  118. u32 clk_reset;
  119. };
  120. #define LCD_NUM_BUFFERS 1
  121. #define WSI_TIMEOUT 50
  122. #define PALETTE_SIZE 256
  123. #define LEFT_MARGIN 64
  124. #define RIGHT_MARGIN 64
  125. #define UPPER_MARGIN 32
  126. #define LOWER_MARGIN 32
  127. #define WAIT_FOR_FRAME_DONE true
  128. #define NO_WAIT_FOR_FRAME_DONE false
  129. #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
  130. static struct da8xx_lcd_regs *da8xx_fb_reg_base;
  131. DECLARE_GLOBAL_DATA_PTR;
  132. /* graphics setup */
  133. static GraphicDevice gpanel;
  134. static const struct da8xx_panel *lcd_panel;
  135. static struct fb_info *da8xx_fb_info;
  136. static int bits_x_pixel;
  137. static unsigned int lcd_revision;
  138. const struct lcd_ctrl_config *da8xx_lcd_cfg;
  139. static inline unsigned int lcdc_read(u32 *addr)
  140. {
  141. return (unsigned int)readl(addr);
  142. }
  143. static inline void lcdc_write(unsigned int val, u32 *addr)
  144. {
  145. writel(val, addr);
  146. }
  147. struct da8xx_fb_par {
  148. u32 p_palette_base;
  149. unsigned char *v_palette_base;
  150. dma_addr_t vram_phys;
  151. unsigned long vram_size;
  152. void *vram_virt;
  153. unsigned int dma_start;
  154. unsigned int dma_end;
  155. struct clk *lcdc_clk;
  156. int irq;
  157. unsigned short pseudo_palette[16];
  158. unsigned int palette_sz;
  159. unsigned int pxl_clk;
  160. int blank;
  161. int vsync_flag;
  162. int vsync_timeout;
  163. };
  164. /* Variable Screen Information */
  165. static struct fb_var_screeninfo da8xx_fb_var = {
  166. .xoffset = 0,
  167. .yoffset = 0,
  168. .transp = {0, 0, 0},
  169. .nonstd = 0,
  170. .activate = 0,
  171. .height = -1,
  172. .width = -1,
  173. .pixclock = 46666, /* 46us - AUO display */
  174. .accel_flags = 0,
  175. .left_margin = LEFT_MARGIN,
  176. .right_margin = RIGHT_MARGIN,
  177. .upper_margin = UPPER_MARGIN,
  178. .lower_margin = LOWER_MARGIN,
  179. .sync = 0,
  180. .vmode = FB_VMODE_NONINTERLACED
  181. };
  182. static struct fb_fix_screeninfo da8xx_fb_fix = {
  183. .id = "DA8xx FB Drv",
  184. .type = FB_TYPE_PACKED_PIXELS,
  185. .type_aux = 0,
  186. .visual = FB_VISUAL_PSEUDOCOLOR,
  187. .xpanstep = 0,
  188. .ypanstep = 1,
  189. .ywrapstep = 0,
  190. .accel = FB_ACCEL_NONE
  191. };
  192. /* Enable the Raster Engine of the LCD Controller */
  193. static inline void lcd_enable_raster(void)
  194. {
  195. u32 reg;
  196. /* Put LCDC in reset for several cycles */
  197. if (lcd_revision == LCD_VERSION_2)
  198. lcdc_write(LCD_CLK_MAIN_RESET,
  199. &da8xx_fb_reg_base->clk_reset);
  200. udelay(1000);
  201. /* Bring LCDC out of reset */
  202. if (lcd_revision == LCD_VERSION_2)
  203. lcdc_write(0,
  204. &da8xx_fb_reg_base->clk_reset);
  205. udelay(1000);
  206. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  207. if (!(reg & LCD_RASTER_ENABLE))
  208. lcdc_write(reg | LCD_RASTER_ENABLE,
  209. &da8xx_fb_reg_base->raster_ctrl);
  210. }
  211. /* Disable the Raster Engine of the LCD Controller */
  212. static inline void lcd_disable_raster(bool wait_for_frame_done)
  213. {
  214. u32 reg;
  215. u32 loop_cnt = 0;
  216. u32 stat;
  217. u32 i = 0;
  218. if (wait_for_frame_done)
  219. loop_cnt = 5000;
  220. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  221. if (reg & LCD_RASTER_ENABLE)
  222. lcdc_write(reg & ~LCD_RASTER_ENABLE,
  223. &da8xx_fb_reg_base->raster_ctrl);
  224. /* Wait for the current frame to complete */
  225. do {
  226. if (lcd_revision == LCD_VERSION_1)
  227. stat = lcdc_read(&da8xx_fb_reg_base->stat);
  228. else
  229. stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
  230. mdelay(1);
  231. } while (!(stat & 0x01) && (i++ < loop_cnt));
  232. if (lcd_revision == LCD_VERSION_1)
  233. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  234. else
  235. lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
  236. if ((loop_cnt != 0) && (i >= loop_cnt)) {
  237. printf("LCD Controller timed out\n");
  238. return;
  239. }
  240. }
  241. static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
  242. {
  243. u32 start;
  244. u32 end;
  245. u32 reg_ras;
  246. u32 reg_dma;
  247. u32 reg_int;
  248. /* init reg to clear PLM (loading mode) fields */
  249. reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  250. reg_ras &= ~(3 << 20);
  251. reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
  252. if (load_mode == LOAD_DATA) {
  253. start = par->dma_start;
  254. end = par->dma_end;
  255. reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
  256. if (lcd_revision == LCD_VERSION_1) {
  257. reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
  258. } else {
  259. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  260. LCD_V2_END_OF_FRAME0_INT_ENA |
  261. LCD_V2_END_OF_FRAME1_INT_ENA |
  262. LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
  263. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  264. }
  265. #if (LCD_NUM_BUFFERS == 2)
  266. reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
  267. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  268. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  269. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  270. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  271. #else
  272. reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
  273. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  274. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  275. lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  276. lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  277. #endif
  278. } else if (load_mode == LOAD_PALETTE) {
  279. start = par->p_palette_base;
  280. end = start + par->palette_sz - 1;
  281. reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
  282. if (lcd_revision == LCD_VERSION_1) {
  283. reg_ras |= LCD_V1_PL_INT_ENA;
  284. } else {
  285. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  286. LCD_V2_PL_INT_ENA;
  287. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  288. }
  289. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  290. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  291. }
  292. lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
  293. lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
  294. /*
  295. * The Raster enable bit must be set after all other control fields are
  296. * set.
  297. */
  298. lcd_enable_raster();
  299. }
  300. /* Configure the Burst Size of DMA */
  301. static int lcd_cfg_dma(int burst_size)
  302. {
  303. u32 reg;
  304. reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
  305. switch (burst_size) {
  306. case 1:
  307. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
  308. break;
  309. case 2:
  310. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
  311. break;
  312. case 4:
  313. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
  314. break;
  315. case 8:
  316. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
  317. break;
  318. case 16:
  319. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
  320. break;
  321. default:
  322. return -EINVAL;
  323. }
  324. lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
  325. return 0;
  326. }
  327. static void lcd_cfg_ac_bias(int period, int transitions_per_int)
  328. {
  329. u32 reg;
  330. /* Set the AC Bias Period and Number of Transitions per Interrupt */
  331. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
  332. reg |= LCD_AC_BIAS_FREQUENCY(period) |
  333. LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
  334. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  335. }
  336. static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
  337. int front_porch)
  338. {
  339. u32 reg;
  340. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
  341. reg |= ((back_porch & 0xff) << 24)
  342. | ((front_porch & 0xff) << 16)
  343. | ((pulse_width & 0x3f) << 10);
  344. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
  345. }
  346. static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
  347. int front_porch)
  348. {
  349. u32 reg;
  350. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
  351. reg |= ((back_porch & 0xff) << 24)
  352. | ((front_porch & 0xff) << 16)
  353. | ((pulse_width & 0x3f) << 10);
  354. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
  355. }
  356. static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
  357. {
  358. u32 reg;
  359. u32 reg_int;
  360. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
  361. LCD_MONO_8BIT_MODE |
  362. LCD_MONOCHROME_MODE);
  363. switch (cfg->p_disp_panel->panel_shade) {
  364. case MONOCHROME:
  365. reg |= LCD_MONOCHROME_MODE;
  366. if (cfg->mono_8bit_mode)
  367. reg |= LCD_MONO_8BIT_MODE;
  368. break;
  369. case COLOR_ACTIVE:
  370. reg |= LCD_TFT_MODE;
  371. if (cfg->tft_alt_mode)
  372. reg |= LCD_TFT_ALT_ENABLE;
  373. break;
  374. case COLOR_PASSIVE:
  375. if (cfg->stn_565_mode)
  376. reg |= LCD_STN_565_ENABLE;
  377. break;
  378. default:
  379. return -EINVAL;
  380. }
  381. /* enable additional interrupts here */
  382. if (lcd_revision == LCD_VERSION_1) {
  383. reg |= LCD_V1_UNDERFLOW_INT_ENA;
  384. } else {
  385. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  386. LCD_V2_UNDERFLOW_INT_ENA;
  387. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  388. }
  389. lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
  390. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
  391. if (cfg->sync_ctrl)
  392. reg |= LCD_SYNC_CTRL;
  393. else
  394. reg &= ~LCD_SYNC_CTRL;
  395. if (cfg->sync_edge)
  396. reg |= LCD_SYNC_EDGE;
  397. else
  398. reg &= ~LCD_SYNC_EDGE;
  399. if (cfg->invert_line_clock)
  400. reg |= LCD_INVERT_LINE_CLOCK;
  401. else
  402. reg &= ~LCD_INVERT_LINE_CLOCK;
  403. if (cfg->invert_frm_clock)
  404. reg |= LCD_INVERT_FRAME_CLOCK;
  405. else
  406. reg &= ~LCD_INVERT_FRAME_CLOCK;
  407. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  408. return 0;
  409. }
  410. static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
  411. u32 bpp, u32 raster_order)
  412. {
  413. u32 reg;
  414. /* Set the Panel Width */
  415. /* Pixels per line = (PPL + 1)*16 */
  416. if (lcd_revision == LCD_VERSION_1) {
  417. /*
  418. * 0x3F in bits 4..9 gives max horizontal resolution = 1024
  419. * pixels
  420. */
  421. width &= 0x3f0;
  422. } else {
  423. /*
  424. * 0x7F in bits 4..10 gives max horizontal resolution = 2048
  425. * pixels.
  426. */
  427. width &= 0x7f0;
  428. }
  429. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
  430. reg &= 0xfffffc00;
  431. if (lcd_revision == LCD_VERSION_1) {
  432. reg |= ((width >> 4) - 1) << 4;
  433. } else {
  434. width = (width >> 4) - 1;
  435. reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
  436. }
  437. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
  438. /* Set the Panel Height */
  439. /* Set bits 9:0 of Lines Per Pixel */
  440. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
  441. reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
  442. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
  443. /* Set bit 10 of Lines Per Pixel */
  444. if (lcd_revision == LCD_VERSION_2) {
  445. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
  446. reg |= ((height - 1) & 0x400) << 16;
  447. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  448. }
  449. /* Set the Raster Order of the Frame Buffer */
  450. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
  451. if (raster_order)
  452. reg |= LCD_RASTER_ORDER;
  453. if (bpp == 24)
  454. reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
  455. else if (bpp == 32)
  456. reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
  457. | LCD_V2_TFT_24BPP_UNPACK);
  458. lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
  459. switch (bpp) {
  460. case 1:
  461. case 2:
  462. case 4:
  463. case 16:
  464. case 24:
  465. case 32:
  466. par->palette_sz = 16 * 2;
  467. break;
  468. case 8:
  469. par->palette_sz = 256 * 2;
  470. break;
  471. default:
  472. return -EINVAL;
  473. }
  474. return 0;
  475. }
  476. static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
  477. unsigned blue, unsigned transp,
  478. struct fb_info *info)
  479. {
  480. struct da8xx_fb_par *par = info->par;
  481. unsigned short *palette = (unsigned short *) par->v_palette_base;
  482. u_short pal;
  483. int update_hw = 0;
  484. if (regno > 255)
  485. return 1;
  486. if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
  487. return 1;
  488. if (info->var.bits_per_pixel == 8) {
  489. red >>= 4;
  490. green >>= 8;
  491. blue >>= 12;
  492. pal = (red & 0x0f00);
  493. pal |= (green & 0x00f0);
  494. pal |= (blue & 0x000f);
  495. if (palette[regno] != pal) {
  496. update_hw = 1;
  497. palette[regno] = pal;
  498. }
  499. } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
  500. red >>= (16 - info->var.red.length);
  501. red <<= info->var.red.offset;
  502. green >>= (16 - info->var.green.length);
  503. green <<= info->var.green.offset;
  504. blue >>= (16 - info->var.blue.length);
  505. blue <<= info->var.blue.offset;
  506. par->pseudo_palette[regno] = red | green | blue;
  507. if (palette[0] != 0x4000) {
  508. update_hw = 1;
  509. palette[0] = 0x4000;
  510. }
  511. } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
  512. ((info->var.bits_per_pixel == 24) && regno < 24)) {
  513. red >>= (24 - info->var.red.length);
  514. red <<= info->var.red.offset;
  515. green >>= (24 - info->var.green.length);
  516. green <<= info->var.green.offset;
  517. blue >>= (24 - info->var.blue.length);
  518. blue <<= info->var.blue.offset;
  519. par->pseudo_palette[regno] = red | green | blue;
  520. if (palette[0] != 0x4000) {
  521. update_hw = 1;
  522. palette[0] = 0x4000;
  523. }
  524. }
  525. /* Update the palette in the h/w as needed. */
  526. if (update_hw)
  527. lcd_blit(LOAD_PALETTE, par);
  528. return 0;
  529. }
  530. static void lcd_reset(struct da8xx_fb_par *par)
  531. {
  532. /* Disable the Raster if previously Enabled */
  533. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  534. /* DMA has to be disabled */
  535. lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
  536. lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
  537. if (lcd_revision == LCD_VERSION_2) {
  538. lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
  539. /* Write 1 to reset */
  540. lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
  541. lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
  542. }
  543. }
  544. static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
  545. {
  546. unsigned int lcd_clk, div;
  547. /* Get clock from sysclk2 */
  548. lcd_clk = clk_get(2);
  549. div = lcd_clk / par->pxl_clk;
  550. debug("LCD Clock: %d Divider: %d PixClk: %d\n",
  551. lcd_clk, div, par->pxl_clk);
  552. /* Configure the LCD clock divisor. */
  553. lcdc_write(LCD_CLK_DIVISOR(div) |
  554. (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
  555. if (lcd_revision == LCD_VERSION_2)
  556. lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
  557. LCD_V2_CORE_CLK_EN,
  558. &da8xx_fb_reg_base->clk_ena);
  559. }
  560. static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
  561. const struct da8xx_panel *panel)
  562. {
  563. u32 bpp;
  564. int ret = 0;
  565. lcd_reset(par);
  566. /* Calculate the divider */
  567. lcd_calc_clk_divider(par);
  568. if (panel->invert_pxl_clk)
  569. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
  570. LCD_INVERT_PIXEL_CLOCK),
  571. &da8xx_fb_reg_base->raster_timing_2);
  572. else
  573. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
  574. ~LCD_INVERT_PIXEL_CLOCK),
  575. &da8xx_fb_reg_base->raster_timing_2);
  576. /* Configure the DMA burst size. */
  577. ret = lcd_cfg_dma(cfg->dma_burst_sz);
  578. if (ret < 0)
  579. return ret;
  580. /* Configure the AC bias properties. */
  581. lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
  582. /* Configure the vertical and horizontal sync properties. */
  583. lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
  584. lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
  585. /* Configure for display */
  586. ret = lcd_cfg_display(cfg);
  587. if (ret < 0)
  588. return ret;
  589. if ((QVGA != cfg->p_disp_panel->panel_type) &&
  590. (WVGA != cfg->p_disp_panel->panel_type))
  591. return -EINVAL;
  592. if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
  593. cfg->bpp >= cfg->p_disp_panel->min_bpp)
  594. bpp = cfg->bpp;
  595. else
  596. bpp = cfg->p_disp_panel->max_bpp;
  597. if (bpp == 12)
  598. bpp = 16;
  599. ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
  600. (unsigned int)panel->height, bpp,
  601. cfg->raster_order);
  602. if (ret < 0)
  603. return ret;
  604. /* Configure FDD */
  605. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
  606. (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
  607. return 0;
  608. }
  609. static void lcdc_dma_start(void)
  610. {
  611. struct da8xx_fb_par *par = da8xx_fb_info->par;
  612. lcdc_write(par->dma_start,
  613. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  614. lcdc_write(par->dma_end,
  615. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  616. lcdc_write(0,
  617. &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  618. lcdc_write(0,
  619. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  620. }
  621. static u32 lcdc_irq_handler_rev01(void)
  622. {
  623. struct da8xx_fb_par *par = da8xx_fb_info->par;
  624. u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
  625. u32 reg_ras;
  626. if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  627. debug("LCD_SYNC_LOST\n");
  628. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  629. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  630. lcd_enable_raster();
  631. return LCD_SYNC_LOST;
  632. } else if (stat & LCD_PL_LOAD_DONE) {
  633. debug("LCD_PL_LOAD_DONE\n");
  634. /*
  635. * Must disable raster before changing state of any control bit.
  636. * And also must be disabled before clearing the PL loading
  637. * interrupt via the following write to the status register. If
  638. * this is done after then one gets multiple PL done interrupts.
  639. */
  640. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  641. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  642. /* Disable PL completion interrupt */
  643. reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  644. reg_ras &= ~LCD_V1_PL_INT_ENA;
  645. lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
  646. /* Setup and start data loading mode */
  647. lcd_blit(LOAD_DATA, par);
  648. return LCD_PL_LOAD_DONE;
  649. } else {
  650. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  651. if (stat & LCD_END_OF_FRAME0)
  652. debug("LCD_END_OF_FRAME0\n");
  653. lcdc_write(par->dma_start,
  654. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  655. lcdc_write(par->dma_end,
  656. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  657. par->vsync_flag = 1;
  658. return LCD_END_OF_FRAME0;
  659. }
  660. return stat;
  661. }
  662. static u32 lcdc_irq_handler_rev02(void)
  663. {
  664. struct da8xx_fb_par *par = da8xx_fb_info->par;
  665. u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
  666. u32 reg_int;
  667. if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  668. debug("LCD_SYNC_LOST\n");
  669. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  670. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  671. lcd_enable_raster();
  672. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  673. return LCD_SYNC_LOST;
  674. } else if (stat & LCD_PL_LOAD_DONE) {
  675. debug("LCD_PL_LOAD_DONE\n");
  676. /*
  677. * Must disable raster before changing state of any control bit.
  678. * And also must be disabled before clearing the PL loading
  679. * interrupt via the following write to the status register. If
  680. * this is done after then one gets multiple PL done interrupts.
  681. */
  682. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  683. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  684. /* Disable PL completion interrupt */
  685. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
  686. (LCD_V2_PL_INT_ENA);
  687. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
  688. /* Setup and start data loading mode */
  689. lcd_blit(LOAD_DATA, par);
  690. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  691. return LCD_PL_LOAD_DONE;
  692. } else {
  693. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  694. if (stat & LCD_END_OF_FRAME0)
  695. debug("LCD_END_OF_FRAME0\n");
  696. lcdc_write(par->dma_start,
  697. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  698. lcdc_write(par->dma_end,
  699. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  700. par->vsync_flag = 1;
  701. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  702. return LCD_END_OF_FRAME0;
  703. }
  704. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  705. return stat;
  706. }
  707. static u32 lcdc_irq_handler(void)
  708. {
  709. if (lcd_revision == LCD_VERSION_1)
  710. return lcdc_irq_handler_rev01();
  711. else
  712. return lcdc_irq_handler_rev02();
  713. }
  714. static u32 wait_for_event(u32 event)
  715. {
  716. u32 timeout = 50000;
  717. u32 ret;
  718. do {
  719. ret = lcdc_irq_handler();
  720. udelay(1000);
  721. --timeout;
  722. } while (!(ret & event) && timeout);
  723. if (!(ret & event)) {
  724. printf("%s: event %d not hit\n", __func__, event);
  725. return -1;
  726. }
  727. return 0;
  728. }
  729. void *video_hw_init(void)
  730. {
  731. struct da8xx_fb_par *par;
  732. u32 size;
  733. u32 rev;
  734. char *p;
  735. if (!lcd_panel) {
  736. printf("Display not initialized\n");
  737. return NULL;
  738. }
  739. gpanel.winSizeX = lcd_panel->width;
  740. gpanel.winSizeY = lcd_panel->height;
  741. gpanel.plnSizeX = lcd_panel->width;
  742. gpanel.plnSizeY = lcd_panel->height;
  743. switch (bits_x_pixel) {
  744. case 32:
  745. gpanel.gdfBytesPP = 4;
  746. gpanel.gdfIndex = GDF_32BIT_X888RGB;
  747. break;
  748. case 24:
  749. gpanel.gdfBytesPP = 4;
  750. gpanel.gdfIndex = GDF_32BIT_X888RGB;
  751. break;
  752. case 16:
  753. gpanel.gdfBytesPP = 2;
  754. gpanel.gdfIndex = GDF_16BIT_565RGB;
  755. break;
  756. default:
  757. gpanel.gdfBytesPP = 1;
  758. gpanel.gdfIndex = GDF__8BIT_INDEX;
  759. break;
  760. }
  761. da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
  762. /* Determine LCD IP Version */
  763. rev = lcdc_read(&da8xx_fb_reg_base->revid);
  764. switch (rev) {
  765. case 0x4C100102:
  766. lcd_revision = LCD_VERSION_1;
  767. break;
  768. case 0x4F200800:
  769. case 0x4F201000:
  770. lcd_revision = LCD_VERSION_2;
  771. break;
  772. default:
  773. printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
  774. rev);
  775. lcd_revision = LCD_VERSION_1;
  776. break;
  777. }
  778. debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
  779. gpanel.winSizeX,
  780. gpanel.winSizeY,
  781. da8xx_lcd_cfg->bpp);
  782. size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
  783. da8xx_fb_info = malloc_cache_aligned(size);
  784. debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
  785. if (!da8xx_fb_info) {
  786. printf("Memory allocation failed for fb_info\n");
  787. return NULL;
  788. }
  789. memset(da8xx_fb_info, 0, size);
  790. p = (char *)da8xx_fb_info;
  791. da8xx_fb_info->par = p + sizeof(struct fb_info);
  792. debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
  793. par = da8xx_fb_info->par;
  794. par->pxl_clk = lcd_panel->pxl_clk;
  795. if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
  796. printf("lcd_init failed\n");
  797. goto err_release_fb;
  798. }
  799. /* allocate frame buffer */
  800. par->vram_size = lcd_panel->width * lcd_panel->height *
  801. da8xx_lcd_cfg->bpp;
  802. par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
  803. par->vram_virt = malloc_cache_aligned(par->vram_size);
  804. par->vram_phys = (dma_addr_t) par->vram_virt;
  805. debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
  806. (unsigned int)par->vram_size,
  807. (unsigned int)par->vram_virt);
  808. if (!par->vram_virt) {
  809. printf("GLCD: malloc for frame buffer failed\n");
  810. goto err_release_fb;
  811. }
  812. gd->fb_base = (int)par->vram_virt;
  813. gpanel.frameAdrs = (unsigned int)par->vram_virt;
  814. da8xx_fb_info->screen_base = (char *) par->vram_virt;
  815. da8xx_fb_fix.smem_start = gpanel.frameAdrs;
  816. da8xx_fb_fix.smem_len = par->vram_size;
  817. da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
  818. par->dma_start = par->vram_phys;
  819. par->dma_end = par->dma_start + lcd_panel->height *
  820. da8xx_fb_fix.line_length - 1;
  821. /* allocate palette buffer */
  822. par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE);
  823. if (!par->v_palette_base) {
  824. printf("GLCD: malloc for palette buffer failed\n");
  825. goto err_release_fb_mem;
  826. }
  827. memset(par->v_palette_base, 0, PALETTE_SIZE);
  828. par->p_palette_base = (unsigned int)par->v_palette_base;
  829. /* Initialize par */
  830. da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
  831. da8xx_fb_var.xres = lcd_panel->width;
  832. da8xx_fb_var.xres_virtual = lcd_panel->width;
  833. da8xx_fb_var.yres = lcd_panel->height;
  834. da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
  835. da8xx_fb_var.grayscale =
  836. da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
  837. da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
  838. da8xx_fb_var.hsync_len = lcd_panel->hsw;
  839. da8xx_fb_var.vsync_len = lcd_panel->vsw;
  840. /* Initialize fbinfo */
  841. da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
  842. da8xx_fb_info->fix = da8xx_fb_fix;
  843. da8xx_fb_info->var = da8xx_fb_var;
  844. da8xx_fb_info->pseudo_palette = par->pseudo_palette;
  845. da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
  846. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  847. /* Clear interrupt */
  848. memset((void *)par->vram_virt, 0, par->vram_size);
  849. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  850. if (lcd_revision == LCD_VERSION_1)
  851. lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
  852. else
  853. lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
  854. debug("Palette at 0x%x size %d\n", par->p_palette_base,
  855. par->palette_sz);
  856. lcdc_dma_start();
  857. /* Load a default palette */
  858. fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
  859. /* Check that the palette is loaded */
  860. wait_for_event(LCD_PL_LOAD_DONE);
  861. /* Wait until DMA is working */
  862. wait_for_event(LCD_END_OF_FRAME0);
  863. return (void *)&gpanel;
  864. err_release_fb_mem:
  865. free(par->vram_virt);
  866. err_release_fb:
  867. free(da8xx_fb_info);
  868. return NULL;
  869. }
  870. void da8xx_video_init(const struct da8xx_panel *panel,
  871. const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
  872. {
  873. lcd_panel = panel;
  874. da8xx_lcd_cfg = lcd_cfg;
  875. bits_x_pixel = bits_pixel;
  876. }