spi-sifive.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 SiFive, Inc.
  4. * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
  5. *
  6. * SiFive SPI controller driver (master mode only)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <dm/device_compat.h>
  11. #include <malloc.h>
  12. #include <spi-mem.h>
  13. #include <wait_bit.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #include <linux/log2.h>
  17. #include <clk.h>
  18. #define SIFIVE_SPI_MAX_CS 32
  19. #define SIFIVE_SPI_DEFAULT_DEPTH 8
  20. #define SIFIVE_SPI_DEFAULT_BITS 8
  21. /* register offsets */
  22. #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
  23. #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
  24. #define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
  25. #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
  26. #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
  27. #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
  28. #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
  29. #define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
  30. #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
  31. #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
  32. #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
  33. #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
  34. #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
  35. #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
  36. #define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
  37. #define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
  38. /* sckdiv bits */
  39. #define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
  40. /* sckmode bits */
  41. #define SIFIVE_SPI_SCKMODE_PHA BIT(0)
  42. #define SIFIVE_SPI_SCKMODE_POL BIT(1)
  43. #define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
  44. SIFIVE_SPI_SCKMODE_POL)
  45. /* csmode bits */
  46. #define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
  47. #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
  48. #define SIFIVE_SPI_CSMODE_MODE_OFF 3U
  49. /* delay0 bits */
  50. #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
  51. #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
  52. #define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
  53. #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
  54. /* delay1 bits */
  55. #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
  56. #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
  57. #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
  58. #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
  59. /* fmt bits */
  60. #define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
  61. #define SIFIVE_SPI_FMT_PROTO_DUAL 1U
  62. #define SIFIVE_SPI_FMT_PROTO_QUAD 2U
  63. #define SIFIVE_SPI_FMT_PROTO_MASK 3U
  64. #define SIFIVE_SPI_FMT_ENDIAN BIT(2)
  65. #define SIFIVE_SPI_FMT_DIR BIT(3)
  66. #define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
  67. #define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
  68. /* txdata bits */
  69. #define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
  70. #define SIFIVE_SPI_TXDATA_FULL BIT(31)
  71. /* rxdata bits */
  72. #define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
  73. #define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
  74. /* ie and ip bits */
  75. #define SIFIVE_SPI_IP_TXWM BIT(0)
  76. #define SIFIVE_SPI_IP_RXWM BIT(1)
  77. /* format protocol */
  78. #define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */
  79. #define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */
  80. #define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */
  81. struct sifive_spi {
  82. void *regs; /* base address of the registers */
  83. u32 fifo_depth;
  84. u32 bits_per_word;
  85. u32 cs_inactive; /* Level of the CS pins when inactive*/
  86. u32 freq;
  87. u32 num_cs;
  88. u8 fmt_proto;
  89. };
  90. static void sifive_spi_prep_device(struct sifive_spi *spi,
  91. struct dm_spi_slave_platdata *slave_plat)
  92. {
  93. /* Update the chip select polarity */
  94. if (slave_plat->mode & SPI_CS_HIGH)
  95. spi->cs_inactive &= ~BIT(slave_plat->cs);
  96. else
  97. spi->cs_inactive |= BIT(slave_plat->cs);
  98. writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
  99. /* Select the correct device */
  100. writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID);
  101. }
  102. static int sifive_spi_set_cs(struct sifive_spi *spi,
  103. struct dm_spi_slave_platdata *slave_plat)
  104. {
  105. u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
  106. if (slave_plat->mode & SPI_CS_HIGH)
  107. cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
  108. writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
  109. return 0;
  110. }
  111. static void sifive_spi_clear_cs(struct sifive_spi *spi)
  112. {
  113. writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
  114. }
  115. static void sifive_spi_prep_transfer(struct sifive_spi *spi,
  116. struct dm_spi_slave_platdata *slave_plat,
  117. u8 *rx_ptr)
  118. {
  119. u32 cr;
  120. /* Modify the SPI protocol mode */
  121. cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
  122. /* Bits per word ? */
  123. cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
  124. cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
  125. /* LSB first? */
  126. cr &= ~SIFIVE_SPI_FMT_ENDIAN;
  127. if (slave_plat->mode & SPI_LSB_FIRST)
  128. cr |= SIFIVE_SPI_FMT_ENDIAN;
  129. /* Number of wires ? */
  130. cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
  131. switch (spi->fmt_proto) {
  132. case SIFIVE_SPI_PROTO_QUAD:
  133. cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
  134. break;
  135. case SIFIVE_SPI_PROTO_DUAL:
  136. cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
  137. break;
  138. default:
  139. cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
  140. break;
  141. }
  142. /* SPI direction in/out ? */
  143. cr &= ~SIFIVE_SPI_FMT_DIR;
  144. if (!rx_ptr)
  145. cr |= SIFIVE_SPI_FMT_DIR;
  146. writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
  147. }
  148. static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
  149. {
  150. u32 data;
  151. do {
  152. data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
  153. } while (data & SIFIVE_SPI_RXDATA_EMPTY);
  154. if (rx_ptr)
  155. *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
  156. }
  157. static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
  158. {
  159. u32 data;
  160. u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
  161. SIFIVE_SPI_TXDATA_DATA_MASK;
  162. do {
  163. data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
  164. } while (data & SIFIVE_SPI_TXDATA_FULL);
  165. writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
  166. }
  167. static int sifive_spi_wait(struct sifive_spi *spi, u32 bit)
  168. {
  169. return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP,
  170. bit, true, 100, false);
  171. }
  172. static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
  173. const void *dout, void *din, unsigned long flags)
  174. {
  175. struct udevice *bus = dev->parent;
  176. struct sifive_spi *spi = dev_get_priv(bus);
  177. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  178. const u8 *tx_ptr = dout;
  179. u8 *rx_ptr = din;
  180. u32 remaining_len;
  181. int ret;
  182. if (flags & SPI_XFER_BEGIN) {
  183. sifive_spi_prep_device(spi, slave_plat);
  184. ret = sifive_spi_set_cs(spi, slave_plat);
  185. if (ret)
  186. return ret;
  187. }
  188. sifive_spi_prep_transfer(spi, slave_plat, rx_ptr);
  189. remaining_len = bitlen / 8;
  190. while (remaining_len) {
  191. unsigned int n_words = min(remaining_len, spi->fifo_depth);
  192. unsigned int tx_words, rx_words;
  193. /* Enqueue n_words for transmission */
  194. for (tx_words = 0; tx_words < n_words; tx_words++) {
  195. if (!tx_ptr)
  196. sifive_spi_tx(spi, NULL);
  197. else
  198. sifive_spi_tx(spi, tx_ptr++);
  199. }
  200. if (rx_ptr) {
  201. /* Wait for transmission + reception to complete */
  202. writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK);
  203. ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM);
  204. if (ret)
  205. return ret;
  206. /* Read out all the data from the RX FIFO */
  207. for (rx_words = 0; rx_words < n_words; rx_words++)
  208. sifive_spi_rx(spi, rx_ptr++);
  209. } else {
  210. /* Wait for transmission to complete */
  211. ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM);
  212. if (ret)
  213. return ret;
  214. }
  215. remaining_len -= n_words;
  216. }
  217. if (flags & SPI_XFER_END)
  218. sifive_spi_clear_cs(spi);
  219. return 0;
  220. }
  221. static int sifive_spi_exec_op(struct spi_slave *slave,
  222. const struct spi_mem_op *op)
  223. {
  224. struct udevice *dev = slave->dev;
  225. struct sifive_spi *spi = dev_get_priv(dev->parent);
  226. unsigned long flags = SPI_XFER_BEGIN;
  227. u8 opcode = op->cmd.opcode;
  228. unsigned int pos = 0;
  229. const void *tx_buf = NULL;
  230. void *rx_buf = NULL;
  231. int op_len, i;
  232. int ret;
  233. if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes)
  234. flags |= SPI_XFER_END;
  235. spi->fmt_proto = op->cmd.buswidth;
  236. /* send the opcode */
  237. ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
  238. if (ret < 0) {
  239. dev_err(dev, "failed to xfer opcode\n");
  240. return ret;
  241. }
  242. op_len = op->addr.nbytes + op->dummy.nbytes;
  243. u8 op_buf[op_len];
  244. /* send the addr + dummy */
  245. if (op->addr.nbytes) {
  246. /* fill address */
  247. for (i = 0; i < op->addr.nbytes; i++)
  248. op_buf[pos + i] = op->addr.val >>
  249. (8 * (op->addr.nbytes - i - 1));
  250. pos += op->addr.nbytes;
  251. /* fill dummy */
  252. if (op->dummy.nbytes)
  253. memset(op_buf + pos, 0xff, op->dummy.nbytes);
  254. /* make sure to set end flag, if no data bytes */
  255. if (!op->data.nbytes)
  256. flags |= SPI_XFER_END;
  257. spi->fmt_proto = op->addr.buswidth;
  258. ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags);
  259. if (ret < 0) {
  260. dev_err(dev, "failed to xfer addr + dummy\n");
  261. return ret;
  262. }
  263. }
  264. /* send/received the data */
  265. if (op->data.nbytes) {
  266. if (op->data.dir == SPI_MEM_DATA_IN)
  267. rx_buf = op->data.buf.in;
  268. else
  269. tx_buf = op->data.buf.out;
  270. spi->fmt_proto = op->data.buswidth;
  271. ret = sifive_spi_xfer(dev, op->data.nbytes * 8,
  272. tx_buf, rx_buf, SPI_XFER_END);
  273. if (ret) {
  274. dev_err(dev, "failed to xfer data\n");
  275. return ret;
  276. }
  277. }
  278. return 0;
  279. }
  280. static int sifive_spi_set_speed(struct udevice *bus, uint speed)
  281. {
  282. struct sifive_spi *spi = dev_get_priv(bus);
  283. u32 scale;
  284. if (speed > spi->freq)
  285. speed = spi->freq;
  286. /* Cofigure max speed */
  287. scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
  288. & SIFIVE_SPI_SCKDIV_DIV_MASK;
  289. writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
  290. return 0;
  291. }
  292. static int sifive_spi_set_mode(struct udevice *bus, uint mode)
  293. {
  294. struct sifive_spi *spi = dev_get_priv(bus);
  295. u32 cr;
  296. /* Switch clock mode bits */
  297. cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
  298. ~SIFIVE_SPI_SCKMODE_MODE_MASK;
  299. if (mode & SPI_CPHA)
  300. cr |= SIFIVE_SPI_SCKMODE_PHA;
  301. if (mode & SPI_CPOL)
  302. cr |= SIFIVE_SPI_SCKMODE_POL;
  303. writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
  304. return 0;
  305. }
  306. static int sifive_spi_cs_info(struct udevice *bus, uint cs,
  307. struct spi_cs_info *info)
  308. {
  309. struct sifive_spi *spi = dev_get_priv(bus);
  310. if (cs >= spi->num_cs)
  311. return -EINVAL;
  312. return 0;
  313. }
  314. static void sifive_spi_init_hw(struct sifive_spi *spi)
  315. {
  316. u32 cs_bits;
  317. /* probe the number of CS lines */
  318. spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
  319. writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
  320. cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
  321. writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
  322. if (!cs_bits) {
  323. printf("Could not auto probe CS lines\n");
  324. return;
  325. }
  326. spi->num_cs = ilog2(cs_bits) + 1;
  327. if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
  328. printf("Invalid number of spi slaves\n");
  329. return;
  330. }
  331. /* Watermark interrupts are disabled by default */
  332. writel(0, spi->regs + SIFIVE_SPI_REG_IE);
  333. /* Default watermark FIFO threshold values */
  334. writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK);
  335. writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK);
  336. /* Set CS/SCK Delays and Inactive Time to defaults */
  337. writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
  338. spi->regs + SIFIVE_SPI_REG_DELAY0);
  339. writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
  340. spi->regs + SIFIVE_SPI_REG_DELAY1);
  341. /* Exit specialized memory-mapped SPI flash mode */
  342. writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
  343. }
  344. static int sifive_spi_probe(struct udevice *bus)
  345. {
  346. struct sifive_spi *spi = dev_get_priv(bus);
  347. struct clk clkdev;
  348. int ret;
  349. spi->regs = (void *)(ulong)dev_remap_addr(bus);
  350. if (!spi->regs)
  351. return -ENODEV;
  352. spi->fifo_depth = dev_read_u32_default(bus,
  353. "sifive,fifo-depth",
  354. SIFIVE_SPI_DEFAULT_DEPTH);
  355. spi->bits_per_word = dev_read_u32_default(bus,
  356. "sifive,max-bits-per-word",
  357. SIFIVE_SPI_DEFAULT_BITS);
  358. ret = clk_get_by_index(bus, 0, &clkdev);
  359. if (ret)
  360. return ret;
  361. spi->freq = clk_get_rate(&clkdev);
  362. /* init the sifive spi hw */
  363. sifive_spi_init_hw(spi);
  364. return 0;
  365. }
  366. static const struct spi_controller_mem_ops sifive_spi_mem_ops = {
  367. .exec_op = sifive_spi_exec_op,
  368. };
  369. static const struct dm_spi_ops sifive_spi_ops = {
  370. .xfer = sifive_spi_xfer,
  371. .set_speed = sifive_spi_set_speed,
  372. .set_mode = sifive_spi_set_mode,
  373. .cs_info = sifive_spi_cs_info,
  374. .mem_ops = &sifive_spi_mem_ops,
  375. };
  376. static const struct udevice_id sifive_spi_ids[] = {
  377. { .compatible = "sifive,spi0" },
  378. { }
  379. };
  380. U_BOOT_DRIVER(sifive_spi) = {
  381. .name = "sifive_spi",
  382. .id = UCLASS_SPI,
  383. .of_match = sifive_spi_ids,
  384. .ops = &sifive_spi_ops,
  385. .priv_auto_alloc_size = sizeof(struct sifive_spi),
  386. .probe = sifive_spi_probe,
  387. };