nxp_fspi.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NXP FlexSPI(FSPI) controller driver.
  4. *
  5. * Copyright (c) 2019 Michael Walle <michael@walle.cc>
  6. * Copyright (c) 2019 NXP
  7. *
  8. * This driver was originally ported from the linux kernel v5.4-rc3, which had
  9. * the following notes:
  10. *
  11. * FlexSPI is a flexsible SPI host controller which supports two SPI
  12. * channels and up to 4 external devices. Each channel supports
  13. * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
  14. * data lines).
  15. *
  16. * FlexSPI controller is driven by the LUT(Look-up Table) registers
  17. * LUT registers are a look-up-table for sequences of instructions.
  18. * A valid sequence consists of four LUT registers.
  19. * Maximum 32 LUT sequences can be programmed simultaneously.
  20. *
  21. * LUTs are being created at run-time based on the commands passed
  22. * from the spi-mem framework, thus using single LUT index.
  23. *
  24. * Software triggered Flash read/write access by IP Bus.
  25. *
  26. * Memory mapped read access by AHB Bus.
  27. *
  28. * Based on SPI MEM interface and spi-fsl-qspi.c driver.
  29. *
  30. * Author:
  31. * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
  32. * Boris Brezillon <bbrezillon@kernel.org>
  33. * Frieder Schrempf <frieder.schrempf@kontron.de>
  34. */
  35. #include <common.h>
  36. #include <asm/io.h>
  37. #include <malloc.h>
  38. #include <spi.h>
  39. #include <spi-mem.h>
  40. #include <dm.h>
  41. #include <clk.h>
  42. #include <linux/bitops.h>
  43. #include <linux/kernel.h>
  44. #include <linux/sizes.h>
  45. #include <linux/iopoll.h>
  46. #include <linux/bug.h>
  47. #include <linux/err.h>
  48. /*
  49. * The driver only uses one single LUT entry, that is updated on
  50. * each call of exec_op(). Index 0 is preset at boot with a basic
  51. * read operation, so let's use the last entry (31).
  52. */
  53. #define SEQID_LUT 31
  54. /* Registers used by the driver */
  55. #define FSPI_MCR0 0x00
  56. #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
  57. #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
  58. #define FSPI_MCR0_LEARN_EN BIT(15)
  59. #define FSPI_MCR0_SCRFRUN_EN BIT(14)
  60. #define FSPI_MCR0_OCTCOMB_EN BIT(13)
  61. #define FSPI_MCR0_DOZE_EN BIT(12)
  62. #define FSPI_MCR0_HSEN BIT(11)
  63. #define FSPI_MCR0_SERCLKDIV BIT(8)
  64. #define FSPI_MCR0_ATDF_EN BIT(7)
  65. #define FSPI_MCR0_ARDF_EN BIT(6)
  66. #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
  67. #define FSPI_MCR0_END_CFG(x) ((x) << 2)
  68. #define FSPI_MCR0_MDIS BIT(1)
  69. #define FSPI_MCR0_SWRST BIT(0)
  70. #define FSPI_MCR1 0x04
  71. #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
  72. #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
  73. #define FSPI_MCR2 0x08
  74. #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
  75. #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
  76. #define FSPI_MCR2_CLRLRPHS BIT(14)
  77. #define FSPI_MCR2_ABRDATSZ BIT(8)
  78. #define FSPI_MCR2_ABRLEARN BIT(7)
  79. #define FSPI_MCR2_ABR_READ BIT(6)
  80. #define FSPI_MCR2_ABRWRITE BIT(5)
  81. #define FSPI_MCR2_ABRDUMMY BIT(4)
  82. #define FSPI_MCR2_ABR_MODE BIT(3)
  83. #define FSPI_MCR2_ABRCADDR BIT(2)
  84. #define FSPI_MCR2_ABRRADDR BIT(1)
  85. #define FSPI_MCR2_ABR_CMD BIT(0)
  86. #define FSPI_AHBCR 0x0c
  87. #define FSPI_AHBCR_RDADDROPT BIT(6)
  88. #define FSPI_AHBCR_PREF_EN BIT(5)
  89. #define FSPI_AHBCR_BUFF_EN BIT(4)
  90. #define FSPI_AHBCR_CACH_EN BIT(3)
  91. #define FSPI_AHBCR_CLRTXBUF BIT(2)
  92. #define FSPI_AHBCR_CLRRXBUF BIT(1)
  93. #define FSPI_AHBCR_PAR_EN BIT(0)
  94. #define FSPI_INTEN 0x10
  95. #define FSPI_INTEN_SCLKSBWR BIT(9)
  96. #define FSPI_INTEN_SCLKSBRD BIT(8)
  97. #define FSPI_INTEN_DATALRNFL BIT(7)
  98. #define FSPI_INTEN_IPTXWE BIT(6)
  99. #define FSPI_INTEN_IPRXWA BIT(5)
  100. #define FSPI_INTEN_AHBCMDERR BIT(4)
  101. #define FSPI_INTEN_IPCMDERR BIT(3)
  102. #define FSPI_INTEN_AHBCMDGE BIT(2)
  103. #define FSPI_INTEN_IPCMDGE BIT(1)
  104. #define FSPI_INTEN_IPCMDDONE BIT(0)
  105. #define FSPI_INTR 0x14
  106. #define FSPI_INTR_SCLKSBWR BIT(9)
  107. #define FSPI_INTR_SCLKSBRD BIT(8)
  108. #define FSPI_INTR_DATALRNFL BIT(7)
  109. #define FSPI_INTR_IPTXWE BIT(6)
  110. #define FSPI_INTR_IPRXWA BIT(5)
  111. #define FSPI_INTR_AHBCMDERR BIT(4)
  112. #define FSPI_INTR_IPCMDERR BIT(3)
  113. #define FSPI_INTR_AHBCMDGE BIT(2)
  114. #define FSPI_INTR_IPCMDGE BIT(1)
  115. #define FSPI_INTR_IPCMDDONE BIT(0)
  116. #define FSPI_LUTKEY 0x18
  117. #define FSPI_LUTKEY_VALUE 0x5AF05AF0
  118. #define FSPI_LCKCR 0x1C
  119. #define FSPI_LCKER_LOCK 0x1
  120. #define FSPI_LCKER_UNLOCK 0x2
  121. #define FSPI_BUFXCR_INVALID_MSTRID 0xE
  122. #define FSPI_AHBRX_BUF0CR0 0x20
  123. #define FSPI_AHBRX_BUF1CR0 0x24
  124. #define FSPI_AHBRX_BUF2CR0 0x28
  125. #define FSPI_AHBRX_BUF3CR0 0x2C
  126. #define FSPI_AHBRX_BUF4CR0 0x30
  127. #define FSPI_AHBRX_BUF5CR0 0x34
  128. #define FSPI_AHBRX_BUF6CR0 0x38
  129. #define FSPI_AHBRX_BUF7CR0 0x3C
  130. #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
  131. #define FSPI_AHBRX_BUF0CR1 0x40
  132. #define FSPI_AHBRX_BUF1CR1 0x44
  133. #define FSPI_AHBRX_BUF2CR1 0x48
  134. #define FSPI_AHBRX_BUF3CR1 0x4C
  135. #define FSPI_AHBRX_BUF4CR1 0x50
  136. #define FSPI_AHBRX_BUF5CR1 0x54
  137. #define FSPI_AHBRX_BUF6CR1 0x58
  138. #define FSPI_AHBRX_BUF7CR1 0x5C
  139. #define FSPI_FLSHA1CR0 0x60
  140. #define FSPI_FLSHA2CR0 0x64
  141. #define FSPI_FLSHB1CR0 0x68
  142. #define FSPI_FLSHB2CR0 0x6C
  143. #define FSPI_FLSHXCR0_SZ_KB 10
  144. #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
  145. #define FSPI_FLSHA1CR1 0x70
  146. #define FSPI_FLSHA2CR1 0x74
  147. #define FSPI_FLSHB1CR1 0x78
  148. #define FSPI_FLSHB2CR1 0x7C
  149. #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
  150. #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
  151. #define FSPI_FLSHXCR1_WA BIT(10)
  152. #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
  153. #define FSPI_FLSHXCR1_TCSS(x) (x)
  154. #define FSPI_FLSHA1CR2 0x80
  155. #define FSPI_FLSHA2CR2 0x84
  156. #define FSPI_FLSHB1CR2 0x88
  157. #define FSPI_FLSHB2CR2 0x8C
  158. #define FSPI_FLSHXCR2_CLRINSP BIT(24)
  159. #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
  160. #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
  161. #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
  162. #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
  163. #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
  164. #define FSPI_IPCR0 0xA0
  165. #define FSPI_IPCR1 0xA4
  166. #define FSPI_IPCR1_IPAREN BIT(31)
  167. #define FSPI_IPCR1_SEQNUM_SHIFT 24
  168. #define FSPI_IPCR1_SEQID_SHIFT 16
  169. #define FSPI_IPCR1_IDATSZ(x) (x)
  170. #define FSPI_IPCMD 0xB0
  171. #define FSPI_IPCMD_TRG BIT(0)
  172. #define FSPI_DLPR 0xB4
  173. #define FSPI_IPRXFCR 0xB8
  174. #define FSPI_IPRXFCR_CLR BIT(0)
  175. #define FSPI_IPRXFCR_DMA_EN BIT(1)
  176. #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
  177. #define FSPI_IPTXFCR 0xBC
  178. #define FSPI_IPTXFCR_CLR BIT(0)
  179. #define FSPI_IPTXFCR_DMA_EN BIT(1)
  180. #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
  181. #define FSPI_DLLACR 0xC0
  182. #define FSPI_DLLACR_OVRDEN BIT(8)
  183. #define FSPI_DLLBCR 0xC4
  184. #define FSPI_DLLBCR_OVRDEN BIT(8)
  185. #define FSPI_STS0 0xE0
  186. #define FSPI_STS0_DLPHB(x) ((x) << 8)
  187. #define FSPI_STS0_DLPHA(x) ((x) << 4)
  188. #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
  189. #define FSPI_STS0_ARB_IDLE BIT(1)
  190. #define FSPI_STS0_SEQ_IDLE BIT(0)
  191. #define FSPI_STS1 0xE4
  192. #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
  193. #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
  194. #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
  195. #define FSPI_STS1_AHB_ERRID(x) (x)
  196. #define FSPI_AHBSPNST 0xEC
  197. #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
  198. #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
  199. #define FSPI_AHBSPNST_ACTIVE BIT(0)
  200. #define FSPI_IPRXFSTS 0xF0
  201. #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
  202. #define FSPI_IPRXFSTS_FILL(x) (x)
  203. #define FSPI_IPTXFSTS 0xF4
  204. #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
  205. #define FSPI_IPTXFSTS_FILL(x) (x)
  206. #define FSPI_RFDR 0x100
  207. #define FSPI_TFDR 0x180
  208. #define FSPI_LUT_BASE 0x200
  209. #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  210. #define FSPI_LUT_REG(idx) \
  211. (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
  212. /* register map end */
  213. /* Instruction set for the LUT register. */
  214. #define LUT_STOP 0x00
  215. #define LUT_CMD 0x01
  216. #define LUT_ADDR 0x02
  217. #define LUT_CADDR_SDR 0x03
  218. #define LUT_MODE 0x04
  219. #define LUT_MODE2 0x05
  220. #define LUT_MODE4 0x06
  221. #define LUT_MODE8 0x07
  222. #define LUT_NXP_WRITE 0x08
  223. #define LUT_NXP_READ 0x09
  224. #define LUT_LEARN_SDR 0x0A
  225. #define LUT_DATSZ_SDR 0x0B
  226. #define LUT_DUMMY 0x0C
  227. #define LUT_DUMMY_RWDS_SDR 0x0D
  228. #define LUT_JMP_ON_CS 0x1F
  229. #define LUT_CMD_DDR 0x21
  230. #define LUT_ADDR_DDR 0x22
  231. #define LUT_CADDR_DDR 0x23
  232. #define LUT_MODE_DDR 0x24
  233. #define LUT_MODE2_DDR 0x25
  234. #define LUT_MODE4_DDR 0x26
  235. #define LUT_MODE8_DDR 0x27
  236. #define LUT_WRITE_DDR 0x28
  237. #define LUT_READ_DDR 0x29
  238. #define LUT_LEARN_DDR 0x2A
  239. #define LUT_DATSZ_DDR 0x2B
  240. #define LUT_DUMMY_DDR 0x2C
  241. #define LUT_DUMMY_RWDS_DDR 0x2D
  242. /*
  243. * Calculate number of required PAD bits for LUT register.
  244. *
  245. * The pad stands for the number of IO lines [0:7].
  246. * For example, the octal read needs eight IO lines,
  247. * so you should use LUT_PAD(8). This macro
  248. * returns 3 i.e. use eight (2^3) IP lines for read.
  249. */
  250. #define LUT_PAD(x) (fls(x) - 1)
  251. /*
  252. * Macro for constructing the LUT entries with the following
  253. * register layout:
  254. *
  255. * ---------------------------------------------------
  256. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  257. * ---------------------------------------------------
  258. */
  259. #define PAD_SHIFT 8
  260. #define INSTR_SHIFT 10
  261. #define OPRND_SHIFT 16
  262. /* Macros for constructing the LUT register. */
  263. #define LUT_DEF(idx, ins, pad, opr) \
  264. ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
  265. (opr)) << (((idx) % 2) * OPRND_SHIFT))
  266. #define POLL_TOUT 5000
  267. #define NXP_FSPI_MAX_CHIPSELECT 4
  268. struct nxp_fspi_devtype_data {
  269. unsigned int rxfifo;
  270. unsigned int txfifo;
  271. unsigned int ahb_buf_size;
  272. unsigned int quirks;
  273. bool little_endian;
  274. };
  275. static const struct nxp_fspi_devtype_data lx2160a_data = {
  276. .rxfifo = SZ_512, /* (64 * 64 bits) */
  277. .txfifo = SZ_1K, /* (128 * 64 bits) */
  278. .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
  279. .quirks = 0,
  280. .little_endian = true, /* little-endian */
  281. };
  282. struct nxp_fspi {
  283. struct udevice *dev;
  284. void __iomem *iobase;
  285. void __iomem *ahb_addr;
  286. u32 memmap_phy;
  287. u32 memmap_phy_size;
  288. struct clk clk, clk_en;
  289. const struct nxp_fspi_devtype_data *devtype_data;
  290. };
  291. /*
  292. * R/W functions for big- or little-endian registers:
  293. * The FSPI controller's endianness is independent of
  294. * the CPU core's endianness. So far, although the CPU
  295. * core is little-endian the FSPI controller can use
  296. * big-endian or little-endian.
  297. */
  298. static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
  299. {
  300. if (f->devtype_data->little_endian)
  301. out_le32(addr, val);
  302. else
  303. out_be32(addr, val);
  304. }
  305. static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
  306. {
  307. if (f->devtype_data->little_endian)
  308. return in_le32(addr);
  309. else
  310. return in_be32(addr);
  311. }
  312. static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
  313. {
  314. switch (width) {
  315. case 1:
  316. case 2:
  317. case 4:
  318. case 8:
  319. return 0;
  320. }
  321. return -ENOTSUPP;
  322. }
  323. static bool nxp_fspi_supports_op(struct spi_slave *slave,
  324. const struct spi_mem_op *op)
  325. {
  326. struct nxp_fspi *f;
  327. struct udevice *bus;
  328. int ret;
  329. bus = slave->dev->parent;
  330. f = dev_get_priv(bus);
  331. ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
  332. if (op->addr.nbytes)
  333. ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
  334. if (op->dummy.nbytes)
  335. ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
  336. if (op->data.nbytes)
  337. ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
  338. if (ret)
  339. return false;
  340. /*
  341. * The number of address bytes should be equal to or less than 4 bytes.
  342. */
  343. if (op->addr.nbytes > 4)
  344. return false;
  345. /*
  346. * If requested address value is greater than controller assigned
  347. * memory mapped space, return error as it didn't fit in the range
  348. * of assigned address space.
  349. */
  350. if (op->addr.val >= f->memmap_phy_size)
  351. return false;
  352. /* Max 64 dummy clock cycles supported */
  353. if (op->dummy.buswidth &&
  354. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  355. return false;
  356. /* Max data length, check controller limits and alignment */
  357. if (op->data.dir == SPI_MEM_DATA_IN &&
  358. (op->data.nbytes > f->devtype_data->ahb_buf_size ||
  359. (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
  360. !IS_ALIGNED(op->data.nbytes, 8))))
  361. return false;
  362. if (op->data.dir == SPI_MEM_DATA_OUT &&
  363. op->data.nbytes > f->devtype_data->txfifo)
  364. return false;
  365. return true;
  366. }
  367. /* Instead of busy looping invoke readl_poll_sleep_timeout functionality. */
  368. static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
  369. u32 mask, u32 delay_us,
  370. u32 timeout_us, bool c)
  371. {
  372. u32 reg;
  373. if (!f->devtype_data->little_endian)
  374. mask = (u32)cpu_to_be32(mask);
  375. if (c)
  376. return readl_poll_sleep_timeout(base, reg, (reg & mask),
  377. delay_us, timeout_us);
  378. else
  379. return readl_poll_sleep_timeout(base, reg, !(reg & mask),
  380. delay_us, timeout_us);
  381. }
  382. /*
  383. * If the slave device content being changed by Write/Erase, need to
  384. * invalidate the AHB buffer. This can be achieved by doing the reset
  385. * of controller after setting MCR0[SWRESET] bit.
  386. */
  387. static inline void nxp_fspi_invalid(struct nxp_fspi *f)
  388. {
  389. u32 reg;
  390. int ret;
  391. reg = fspi_readl(f, f->iobase + FSPI_MCR0);
  392. fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
  393. /* w1c register, wait unit clear */
  394. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
  395. FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
  396. WARN_ON(ret);
  397. }
  398. static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
  399. const struct spi_mem_op *op)
  400. {
  401. void __iomem *base = f->iobase;
  402. u32 lutval[4] = {};
  403. int lutidx = 1, i;
  404. /* cmd */
  405. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  406. op->cmd.opcode);
  407. /* addr bytes */
  408. if (op->addr.nbytes) {
  409. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
  410. LUT_PAD(op->addr.buswidth),
  411. op->addr.nbytes * 8);
  412. lutidx++;
  413. }
  414. /* dummy bytes, if needed */
  415. if (op->dummy.nbytes) {
  416. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  417. /*
  418. * Due to FlexSPI controller limitation number of PAD for dummy
  419. * buswidth needs to be programmed as equal to data buswidth.
  420. */
  421. LUT_PAD(op->data.buswidth),
  422. op->dummy.nbytes * 8 /
  423. op->dummy.buswidth);
  424. lutidx++;
  425. }
  426. /* read/write data bytes */
  427. if (op->data.nbytes) {
  428. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  429. op->data.dir == SPI_MEM_DATA_IN ?
  430. LUT_NXP_READ : LUT_NXP_WRITE,
  431. LUT_PAD(op->data.buswidth),
  432. 0);
  433. lutidx++;
  434. }
  435. /* stop condition. */
  436. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  437. /* unlock LUT */
  438. fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
  439. fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
  440. /* fill LUT */
  441. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  442. fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
  443. dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  444. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  445. /* lock LUT */
  446. fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
  447. fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
  448. }
  449. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  450. static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
  451. {
  452. int ret;
  453. ret = clk_enable(&f->clk_en);
  454. if (ret)
  455. return ret;
  456. ret = clk_enable(&f->clk);
  457. if (ret) {
  458. clk_disable(&f->clk_en);
  459. return ret;
  460. }
  461. return 0;
  462. }
  463. static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
  464. {
  465. clk_disable(&f->clk);
  466. clk_disable(&f->clk_en);
  467. }
  468. #endif
  469. /*
  470. * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
  471. * register and start base address of the slave device.
  472. *
  473. * (Higher address)
  474. * -------- <-- FLSHB2CR0
  475. * | B2 |
  476. * | |
  477. * B2 start address --> -------- <-- FLSHB1CR0
  478. * | B1 |
  479. * | |
  480. * B1 start address --> -------- <-- FLSHA2CR0
  481. * | A2 |
  482. * | |
  483. * A2 start address --> -------- <-- FLSHA1CR0
  484. * | A1 |
  485. * | |
  486. * A1 start address --> -------- (Lower address)
  487. *
  488. *
  489. * Start base address defines the starting address range for given CS and
  490. * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
  491. *
  492. * But, different targets are having different combinations of number of CS,
  493. * some targets only have single CS or two CS covering controller's full
  494. * memory mapped space area.
  495. * Thus, implementation is being done as independent of the size and number
  496. * of the connected slave device.
  497. * Assign controller memory mapped space size as the size to the connected
  498. * slave device.
  499. * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
  500. * chip-select Flash configuration register.
  501. *
  502. * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
  503. * memory mapped size of the controller.
  504. * Value for rest of the CS FLSHxxCR0 register would be zero.
  505. *
  506. */
  507. static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
  508. {
  509. u64 size_kb;
  510. /* Reset FLSHxxCR0 registers */
  511. fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
  512. fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
  513. fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
  514. fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
  515. /* Assign controller memory mapped space as size, KBytes, of flash. */
  516. size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
  517. fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
  518. 4 * chip_select);
  519. dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
  520. }
  521. static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
  522. {
  523. u32 len = op->data.nbytes;
  524. /* Read out the data directly from the AHB buffer. */
  525. memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
  526. }
  527. static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
  528. const struct spi_mem_op *op)
  529. {
  530. void __iomem *base = f->iobase;
  531. int i, ret;
  532. u8 *buf = (u8 *)op->data.buf.out;
  533. /* clear the TX FIFO. */
  534. fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
  535. /*
  536. * Default value of water mark level is 8 bytes, hence in single
  537. * write request controller can write max 8 bytes of data.
  538. */
  539. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
  540. /* Wait for TXFIFO empty */
  541. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  542. FSPI_INTR_IPTXWE, 0,
  543. POLL_TOUT, true);
  544. WARN_ON(ret);
  545. fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
  546. fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
  547. fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
  548. }
  549. if (i < op->data.nbytes) {
  550. u32 data = 0;
  551. int j;
  552. /* Wait for TXFIFO empty */
  553. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  554. FSPI_INTR_IPTXWE, 0,
  555. POLL_TOUT, true);
  556. WARN_ON(ret);
  557. for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
  558. memcpy(&data, buf + i + j, 4);
  559. fspi_writel(f, data, base + FSPI_TFDR + j);
  560. }
  561. fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
  562. }
  563. }
  564. static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
  565. const struct spi_mem_op *op)
  566. {
  567. void __iomem *base = f->iobase;
  568. int i, ret;
  569. int len = op->data.nbytes;
  570. u8 *buf = (u8 *)op->data.buf.in;
  571. /*
  572. * Default value of water mark level is 8 bytes, hence in single
  573. * read request controller can read max 8 bytes of data.
  574. */
  575. for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
  576. /* Wait for RXFIFO available */
  577. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  578. FSPI_INTR_IPRXWA, 0,
  579. POLL_TOUT, true);
  580. WARN_ON(ret);
  581. *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
  582. *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
  583. /* move the FIFO pointer */
  584. fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
  585. }
  586. if (i < len) {
  587. u32 tmp;
  588. int size, j;
  589. buf = op->data.buf.in + i;
  590. /* Wait for RXFIFO available */
  591. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  592. FSPI_INTR_IPRXWA, 0,
  593. POLL_TOUT, true);
  594. WARN_ON(ret);
  595. len = op->data.nbytes - i;
  596. for (j = 0; j < op->data.nbytes - i; j += 4) {
  597. tmp = fspi_readl(f, base + FSPI_RFDR + j);
  598. size = min(len, 4);
  599. memcpy(buf + j, &tmp, size);
  600. len -= size;
  601. }
  602. }
  603. /* invalid the RXFIFO */
  604. fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
  605. /* move the FIFO pointer */
  606. fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
  607. }
  608. static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
  609. {
  610. void __iomem *base = f->iobase;
  611. int seqnum = 0;
  612. int err = 0;
  613. u32 reg;
  614. reg = fspi_readl(f, base + FSPI_IPRXFCR);
  615. /* invalid RXFIFO first */
  616. reg &= ~FSPI_IPRXFCR_DMA_EN;
  617. reg = reg | FSPI_IPRXFCR_CLR;
  618. fspi_writel(f, reg, base + FSPI_IPRXFCR);
  619. fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
  620. /*
  621. * Always start the sequence at the same index since we update
  622. * the LUT at each exec_op() call. And also specify the DATA
  623. * length, since it's has not been specified in the LUT.
  624. */
  625. fspi_writel(f, op->data.nbytes |
  626. (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
  627. (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
  628. base + FSPI_IPCR1);
  629. /* Trigger the LUT now. */
  630. fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
  631. /* Wait for the completion. */
  632. err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
  633. FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
  634. /* Invoke IP data read, if request is of data read. */
  635. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  636. nxp_fspi_read_rxfifo(f, op);
  637. return err;
  638. }
  639. static int nxp_fspi_exec_op(struct spi_slave *slave,
  640. const struct spi_mem_op *op)
  641. {
  642. struct nxp_fspi *f;
  643. struct udevice *bus;
  644. int err = 0;
  645. bus = slave->dev->parent;
  646. f = dev_get_priv(bus);
  647. /* Wait for controller being ready. */
  648. err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
  649. FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
  650. WARN_ON(err);
  651. nxp_fspi_prepare_lut(f, op);
  652. /*
  653. * If we have large chunks of data, we read them through the AHB bus
  654. * by accessing the mapped memory. In all other cases we use
  655. * IP commands to access the flash.
  656. */
  657. if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
  658. op->data.dir == SPI_MEM_DATA_IN) {
  659. nxp_fspi_read_ahb(f, op);
  660. } else {
  661. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  662. nxp_fspi_fill_txfifo(f, op);
  663. err = nxp_fspi_do_op(f, op);
  664. }
  665. /* Invalidate the data in the AHB buffer. */
  666. nxp_fspi_invalid(f);
  667. return err;
  668. }
  669. static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
  670. struct spi_mem_op *op)
  671. {
  672. struct nxp_fspi *f;
  673. struct udevice *bus;
  674. bus = slave->dev->parent;
  675. f = dev_get_priv(bus);
  676. if (op->data.dir == SPI_MEM_DATA_OUT) {
  677. if (op->data.nbytes > f->devtype_data->txfifo)
  678. op->data.nbytes = f->devtype_data->txfifo;
  679. } else {
  680. if (op->data.nbytes > f->devtype_data->ahb_buf_size)
  681. op->data.nbytes = f->devtype_data->ahb_buf_size;
  682. else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
  683. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  684. }
  685. return 0;
  686. }
  687. static int nxp_fspi_default_setup(struct nxp_fspi *f)
  688. {
  689. void __iomem *base = f->iobase;
  690. int ret, i;
  691. u32 reg;
  692. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  693. /* disable and unprepare clock to avoid glitch pass to controller */
  694. nxp_fspi_clk_disable_unprep(f);
  695. /* the default frequency, we will change it later if necessary. */
  696. ret = clk_set_rate(&f->clk, 20000000);
  697. if (ret)
  698. return ret;
  699. ret = nxp_fspi_clk_prep_enable(f);
  700. if (ret)
  701. return ret;
  702. #endif
  703. /* Reset the module */
  704. /* w1c register, wait unit clear */
  705. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
  706. FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
  707. WARN_ON(ret);
  708. /* Disable the module */
  709. fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
  710. /* Reset the DLL register to default value */
  711. fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
  712. fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
  713. /* enable module */
  714. fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
  715. base + FSPI_MCR0);
  716. /*
  717. * Disable same device enable bit and configure all slave devices
  718. * independently.
  719. */
  720. reg = fspi_readl(f, f->iobase + FSPI_MCR2);
  721. reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
  722. fspi_writel(f, reg, base + FSPI_MCR2);
  723. /* AHB configuration for access buffer 0~7. */
  724. for (i = 0; i < 7; i++)
  725. fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
  726. /*
  727. * Set ADATSZ with the maximum AHB buffer size to improve the read
  728. * performance.
  729. */
  730. fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
  731. FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
  732. /* prefetch and no start address alignment limitation */
  733. fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
  734. base + FSPI_AHBCR);
  735. /* AHB Read - Set lut sequence ID for all CS. */
  736. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
  737. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
  738. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
  739. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
  740. return 0;
  741. }
  742. static int nxp_fspi_probe(struct udevice *bus)
  743. {
  744. struct nxp_fspi *f = dev_get_priv(bus);
  745. f->devtype_data =
  746. (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
  747. nxp_fspi_default_setup(f);
  748. return 0;
  749. }
  750. static int nxp_fspi_claim_bus(struct udevice *dev)
  751. {
  752. struct nxp_fspi *f;
  753. struct udevice *bus;
  754. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  755. bus = dev->parent;
  756. f = dev_get_priv(bus);
  757. nxp_fspi_select_mem(f, slave_plat->cs);
  758. return 0;
  759. }
  760. static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
  761. {
  762. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  763. struct nxp_fspi *f = dev_get_priv(bus);
  764. int ret;
  765. nxp_fspi_clk_disable_unprep(f);
  766. ret = clk_set_rate(&f->clk, speed);
  767. if (ret)
  768. return ret;
  769. ret = nxp_fspi_clk_prep_enable(f);
  770. if (ret)
  771. return ret;
  772. #endif
  773. return 0;
  774. }
  775. static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
  776. {
  777. /* Nothing to do */
  778. return 0;
  779. }
  780. static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
  781. {
  782. struct nxp_fspi *f = dev_get_priv(bus);
  783. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  784. int ret;
  785. #endif
  786. fdt_addr_t iobase;
  787. fdt_addr_t iobase_size;
  788. fdt_addr_t ahb_addr;
  789. fdt_addr_t ahb_size;
  790. f->dev = bus;
  791. iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
  792. if (iobase == FDT_ADDR_T_NONE) {
  793. dev_err(bus, "fspi_base regs missing\n");
  794. return -ENODEV;
  795. }
  796. f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
  797. ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
  798. if (ahb_addr == FDT_ADDR_T_NONE) {
  799. dev_err(bus, "fspi_mmap regs missing\n");
  800. return -ENODEV;
  801. }
  802. f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
  803. f->memmap_phy_size = ahb_size;
  804. #if CONFIG_IS_ENABLED(CONFIG_CLK)
  805. ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
  806. if (ret) {
  807. dev_err(bus, "failed to get fspi_en clock\n");
  808. return ret;
  809. }
  810. ret = clk_get_by_name(bus, "fspi", &f->clk);
  811. if (ret) {
  812. dev_err(bus, "failed to get fspi clock\n");
  813. return ret;
  814. }
  815. #endif
  816. dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
  817. return 0;
  818. }
  819. static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
  820. .adjust_op_size = nxp_fspi_adjust_op_size,
  821. .supports_op = nxp_fspi_supports_op,
  822. .exec_op = nxp_fspi_exec_op,
  823. };
  824. static const struct dm_spi_ops nxp_fspi_ops = {
  825. .claim_bus = nxp_fspi_claim_bus,
  826. .set_speed = nxp_fspi_set_speed,
  827. .set_mode = nxp_fspi_set_mode,
  828. .mem_ops = &nxp_fspi_mem_ops,
  829. };
  830. static const struct udevice_id nxp_fspi_ids[] = {
  831. { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
  832. { }
  833. };
  834. U_BOOT_DRIVER(nxp_fspi) = {
  835. .name = "nxp_fspi",
  836. .id = UCLASS_SPI,
  837. .of_match = nxp_fspi_ids,
  838. .ops = &nxp_fspi_ops,
  839. .ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
  840. .priv_auto_alloc_size = sizeof(struct nxp_fspi),
  841. .probe = nxp_fspi_probe,
  842. };