mxs_spi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 SPI driver
  4. *
  5. * Copyright (C) 2019 DENX Software Engineering
  6. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  7. *
  8. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  9. * on behalf of DENX Software Engineering GmbH
  10. *
  11. * NOTE: This driver only supports the SPI-controller chipselects,
  12. * GPIO driven chipselects are not supported.
  13. */
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <dt-structs.h>
  17. #include <cpu_func.h>
  18. #include <errno.h>
  19. #include <log.h>
  20. #include <malloc.h>
  21. #include <memalign.h>
  22. #include <spi.h>
  23. #include <asm/cache.h>
  24. #include <linux/bitops.h>
  25. #include <linux/errno.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/arch/imx-regs.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/mach-imx/dma.h>
  31. #define MXS_SPI_MAX_TIMEOUT 1000000
  32. #define MXS_SPI_PORT_OFFSET 0x2000
  33. #define MXS_SSP_CHIPSELECT_MASK 0x00300000
  34. #define MXS_SSP_CHIPSELECT_SHIFT 20
  35. #define MXSSSP_SMALL_TRANSFER 512
  36. /* Base numbers of i.MX2[38] clk for ssp0 IP block */
  37. #define MXS_SSP_IMX23_CLKID_SSP0 33
  38. #define MXS_SSP_IMX28_CLKID_SSP0 46
  39. #ifdef CONFIG_MX28
  40. #define dtd_fsl_imx_spi dtd_fsl_imx28_spi
  41. #else /* CONFIG_MX23 */
  42. #define dtd_fsl_imx_spi dtd_fsl_imx23_spi
  43. #endif
  44. struct mxs_spi_platdata {
  45. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  46. struct dtd_fsl_imx_spi dtplat;
  47. #endif
  48. s32 frequency; /* Default clock frequency, -1 for none */
  49. fdt_addr_t base; /* SPI IP block base address */
  50. int num_cs; /* Number of CSes supported */
  51. int dma_id; /* ID of the DMA channel */
  52. int clk_id; /* ID of the SSP clock */
  53. };
  54. struct mxs_spi_priv {
  55. struct mxs_ssp_regs *regs;
  56. unsigned int dma_channel;
  57. unsigned int max_freq;
  58. unsigned int clk_id;
  59. unsigned int mode;
  60. };
  61. static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
  62. {
  63. writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
  64. writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
  65. }
  66. static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
  67. {
  68. writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
  69. writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
  70. }
  71. static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
  72. char *data, int length, int write,
  73. unsigned long flags)
  74. {
  75. struct mxs_ssp_regs *ssp_regs = priv->regs;
  76. if (flags & SPI_XFER_BEGIN)
  77. mxs_spi_start_xfer(ssp_regs);
  78. while (length--) {
  79. /* We transfer 1 byte */
  80. #if defined(CONFIG_MX23)
  81. writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
  82. writel(1, &ssp_regs->hw_ssp_ctrl0_set);
  83. #elif defined(CONFIG_MX28)
  84. writel(1, &ssp_regs->hw_ssp_xfer_size);
  85. #endif
  86. if ((flags & SPI_XFER_END) && !length)
  87. mxs_spi_end_xfer(ssp_regs);
  88. if (write)
  89. writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
  90. else
  91. writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
  92. writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
  93. if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
  94. SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
  95. printf("MXS SPI: Timeout waiting for start\n");
  96. return -ETIMEDOUT;
  97. }
  98. if (write)
  99. writel(*data++, &ssp_regs->hw_ssp_data);
  100. writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
  101. if (!write) {
  102. if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
  103. SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
  104. printf("MXS SPI: Timeout waiting for data\n");
  105. return -ETIMEDOUT;
  106. }
  107. *data = readl(&ssp_regs->hw_ssp_data);
  108. data++;
  109. }
  110. if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
  111. SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
  112. printf("MXS SPI: Timeout waiting for finish\n");
  113. return -ETIMEDOUT;
  114. }
  115. }
  116. return 0;
  117. }
  118. static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
  119. char *data, int length, int write,
  120. unsigned long flags)
  121. { struct mxs_ssp_regs *ssp_regs = priv->regs;
  122. const int xfer_max_sz = 0xff00;
  123. const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
  124. struct mxs_dma_desc *dp;
  125. uint32_t ctrl0;
  126. uint32_t cache_data_count;
  127. const uint32_t dstart = (uint32_t)data;
  128. int dmach;
  129. int tl;
  130. int ret = 0;
  131. #if defined(CONFIG_MX23)
  132. const int mxs_spi_pio_words = 1;
  133. #elif defined(CONFIG_MX28)
  134. const int mxs_spi_pio_words = 4;
  135. #endif
  136. ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
  137. memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
  138. ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
  139. ctrl0 |= SSP_CTRL0_DATA_XFER;
  140. if (flags & SPI_XFER_BEGIN)
  141. ctrl0 |= SSP_CTRL0_LOCK_CS;
  142. if (!write)
  143. ctrl0 |= SSP_CTRL0_READ;
  144. if (length % ARCH_DMA_MINALIGN)
  145. cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
  146. else
  147. cache_data_count = length;
  148. /* Flush data to DRAM so DMA can pick them up */
  149. if (write)
  150. flush_dcache_range(dstart, dstart + cache_data_count);
  151. /* Invalidate the area, so no writeback into the RAM races with DMA */
  152. invalidate_dcache_range(dstart, dstart + cache_data_count);
  153. dmach = priv->dma_channel;
  154. dp = desc;
  155. while (length) {
  156. dp->address = (dma_addr_t)dp;
  157. dp->cmd.address = (dma_addr_t)data;
  158. /*
  159. * This is correct, even though it does indeed look insane.
  160. * I hereby have to, wholeheartedly, thank Freescale Inc.,
  161. * for always inventing insane hardware and keeping me busy
  162. * and employed ;-)
  163. */
  164. if (write)
  165. dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
  166. else
  167. dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
  168. /*
  169. * The DMA controller can transfer large chunks (64kB) at
  170. * time by setting the transfer length to 0. Setting tl to
  171. * 0x10000 will overflow below and make .data contain 0.
  172. * Otherwise, 0xff00 is the transfer maximum.
  173. */
  174. if (length >= 0x10000)
  175. tl = 0x10000;
  176. else
  177. tl = min(length, xfer_max_sz);
  178. dp->cmd.data |=
  179. ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
  180. (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  181. MXS_DMA_DESC_HALT_ON_TERMINATE |
  182. MXS_DMA_DESC_TERMINATE_FLUSH;
  183. data += tl;
  184. length -= tl;
  185. if (!length) {
  186. dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
  187. if (flags & SPI_XFER_END) {
  188. ctrl0 &= ~SSP_CTRL0_LOCK_CS;
  189. ctrl0 |= SSP_CTRL0_IGNORE_CRC;
  190. }
  191. }
  192. /*
  193. * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
  194. * case of MX28, write only CTRL0 in case of MX23 due
  195. * to the difference in register layout. It is utterly
  196. * essential that the XFER_SIZE register is written on
  197. * a per-descriptor basis with the same size as is the
  198. * descriptor!
  199. */
  200. dp->cmd.pio_words[0] = ctrl0;
  201. #ifdef CONFIG_MX28
  202. dp->cmd.pio_words[1] = 0;
  203. dp->cmd.pio_words[2] = 0;
  204. dp->cmd.pio_words[3] = tl;
  205. #endif
  206. mxs_dma_desc_append(dmach, dp);
  207. dp++;
  208. }
  209. if (mxs_dma_go(dmach))
  210. ret = -EINVAL;
  211. /* The data arrived into DRAM, invalidate cache over them */
  212. if (!write)
  213. invalidate_dcache_range(dstart, dstart + cache_data_count);
  214. return ret;
  215. }
  216. int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
  217. const void *dout, void *din, unsigned long flags)
  218. {
  219. struct udevice *bus = dev_get_parent(dev);
  220. struct mxs_spi_priv *priv = dev_get_priv(bus);
  221. struct mxs_ssp_regs *ssp_regs = priv->regs;
  222. int len = bitlen / 8;
  223. char dummy;
  224. int write = 0;
  225. char *data = NULL;
  226. int dma = 1;
  227. if (bitlen == 0) {
  228. if (flags & SPI_XFER_END) {
  229. din = (void *)&dummy;
  230. len = 1;
  231. } else
  232. return 0;
  233. }
  234. /* Half-duplex only */
  235. if (din && dout)
  236. return -EINVAL;
  237. /* No data */
  238. if (!din && !dout)
  239. return 0;
  240. if (dout) {
  241. data = (char *)dout;
  242. write = 1;
  243. } else if (din) {
  244. data = (char *)din;
  245. write = 0;
  246. }
  247. /*
  248. * Check for alignment, if the buffer is aligned, do DMA transfer,
  249. * PIO otherwise. This is a temporary workaround until proper bounce
  250. * buffer is in place.
  251. */
  252. if (dma) {
  253. if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
  254. dma = 0;
  255. if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
  256. dma = 0;
  257. }
  258. if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
  259. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
  260. return mxs_spi_xfer_pio(priv, data, len, write, flags);
  261. } else {
  262. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
  263. return mxs_spi_xfer_dma(priv, data, len, write, flags);
  264. }
  265. }
  266. static int mxs_spi_probe(struct udevice *bus)
  267. {
  268. struct mxs_spi_platdata *plat = dev_get_platdata(bus);
  269. struct mxs_spi_priv *priv = dev_get_priv(bus);
  270. int ret;
  271. debug("%s: probe\n", __func__);
  272. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  273. struct dtd_fsl_imx_spi *dtplat = &plat->dtplat;
  274. struct phandle_1_arg *p1a = &dtplat->clocks[0];
  275. priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
  276. priv->dma_channel = dtplat->dmas[1];
  277. priv->clk_id = p1a->arg[0];
  278. priv->max_freq = dtplat->spi_max_frequency;
  279. plat->num_cs = dtplat->num_cs;
  280. debug("OF_PLATDATA: regs: 0x%x max freq: %d clkid: %d\n",
  281. (unsigned int)priv->regs, priv->max_freq, priv->clk_id);
  282. #else
  283. priv->regs = (struct mxs_ssp_regs *)plat->base;
  284. priv->max_freq = plat->frequency;
  285. priv->dma_channel = plat->dma_id;
  286. priv->clk_id = plat->clk_id;
  287. #endif
  288. mxs_reset_block(&priv->regs->hw_ssp_ctrl0_reg);
  289. ret = mxs_dma_init_channel(priv->dma_channel);
  290. if (ret) {
  291. printf("%s: DMA init channel error %d\n", __func__, ret);
  292. return ret;
  293. }
  294. return 0;
  295. }
  296. static int mxs_spi_claim_bus(struct udevice *dev)
  297. {
  298. struct udevice *bus = dev_get_parent(dev);
  299. struct mxs_spi_priv *priv = dev_get_priv(bus);
  300. struct mxs_ssp_regs *ssp_regs = priv->regs;
  301. int cs = spi_chip_select(dev);
  302. /*
  303. * i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
  304. * To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
  305. * where:
  306. *
  307. * WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
  308. * WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
  309. * HW_SSP_CTRL0
  310. * SSn0 b00
  311. * SSn1 b01
  312. * SSn2 b10 (which require setting WAIT_FOR_IRQ)
  313. *
  314. * However, for now i.MX28 SPI driver will support up till 2 CSes
  315. * (SSn0, and SSn1).
  316. */
  317. /* Ungate SSP clock and set active CS */
  318. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  319. BIT(MXS_SSP_CHIPSELECT_SHIFT) |
  320. SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
  321. return 0;
  322. }
  323. static int mxs_spi_release_bus(struct udevice *dev)
  324. {
  325. struct udevice *bus = dev_get_parent(dev);
  326. struct mxs_spi_priv *priv = dev_get_priv(bus);
  327. struct mxs_ssp_regs *ssp_regs = priv->regs;
  328. /* Gate SSP clock */
  329. setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
  330. return 0;
  331. }
  332. static int mxs_spi_set_speed(struct udevice *bus, uint speed)
  333. {
  334. struct mxs_spi_priv *priv = dev_get_priv(bus);
  335. #ifdef CONFIG_MX28
  336. int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
  337. #else /* CONFIG_MX23 */
  338. int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
  339. #endif
  340. if (speed > priv->max_freq)
  341. speed = priv->max_freq;
  342. debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
  343. mxs_set_ssp_busclock(clkid, speed / 1000);
  344. return 0;
  345. }
  346. static int mxs_spi_set_mode(struct udevice *bus, uint mode)
  347. {
  348. struct mxs_spi_priv *priv = dev_get_priv(bus);
  349. struct mxs_ssp_regs *ssp_regs = priv->regs;
  350. u32 reg;
  351. priv->mode = mode;
  352. debug("%s: mode 0x%x\n", __func__, mode);
  353. reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
  354. reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
  355. reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
  356. writel(reg, &ssp_regs->hw_ssp_ctrl1);
  357. /* Single bit SPI support */
  358. writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
  359. return 0;
  360. }
  361. static const struct dm_spi_ops mxs_spi_ops = {
  362. .claim_bus = mxs_spi_claim_bus,
  363. .release_bus = mxs_spi_release_bus,
  364. .xfer = mxs_spi_xfer,
  365. .set_speed = mxs_spi_set_speed,
  366. .set_mode = mxs_spi_set_mode,
  367. /*
  368. * cs_info is not needed, since we require all chip selects to be
  369. * in the device tree explicitly
  370. */
  371. };
  372. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  373. static int mxs_ofdata_to_platdata(struct udevice *bus)
  374. {
  375. struct mxs_spi_platdata *plat = bus->platdata;
  376. u32 prop[2];
  377. int ret;
  378. plat->base = dev_read_addr(bus);
  379. plat->frequency =
  380. dev_read_u32_default(bus, "spi-max-frequency", 40000000);
  381. plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
  382. ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
  383. if (ret) {
  384. printf("%s: Reading 'dmas' property failed!\n", __func__);
  385. return ret;
  386. }
  387. plat->dma_id = prop[1];
  388. ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
  389. if (ret) {
  390. printf("%s: Reading 'clocks' property failed!\n", __func__);
  391. return ret;
  392. }
  393. plat->clk_id = prop[1];
  394. debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
  395. __func__, (uint)plat->base, plat->frequency, plat->num_cs,
  396. plat->dma_id, plat->clk_id);
  397. return 0;
  398. }
  399. static const struct udevice_id mxs_spi_ids[] = {
  400. { .compatible = "fsl,imx23-spi" },
  401. { .compatible = "fsl,imx28-spi" },
  402. { }
  403. };
  404. #endif
  405. U_BOOT_DRIVER(fsl_imx23_spi) = {
  406. .name = "fsl_imx23_spi",
  407. .id = UCLASS_SPI,
  408. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  409. .of_match = mxs_spi_ids,
  410. .ofdata_to_platdata = mxs_ofdata_to_platdata,
  411. #endif
  412. .platdata_auto_alloc_size = sizeof(struct mxs_spi_platdata),
  413. .ops = &mxs_spi_ops,
  414. .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
  415. .probe = mxs_spi_probe,
  416. };
  417. U_BOOT_DRIVER_ALIAS(fsl_imx23_spi, fsl_imx28_spi)