mscc_bb_spi.c 5.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi SoCs spi driver
  4. *
  5. * Copyright (c) 2018 Microsemi Corporation
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <dm.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. struct mscc_bb_priv {
  19. void __iomem *regs;
  20. u32 deactivate_delay_us;
  21. bool cs_active; /* State flag as to whether CS is asserted */
  22. int cs_num;
  23. u32 svalue; /* Value to start transfer with */
  24. u32 clk1; /* Clock value start */
  25. u32 clk2; /* Clock value 2nd phase */
  26. };
  27. /* Delay 24 instructions for this particular application */
  28. #define hold_time_delay() mscc_vcoreiii_nop_delay(3)
  29. static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
  30. {
  31. if (!priv->cs_active) {
  32. int cpha = mode & SPI_CPHA;
  33. u32 cs_value;
  34. priv->cs_num = cs;
  35. if (cpha) {
  36. /* Initial clock starts SCK=1 */
  37. priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
  38. priv->clk2 = 0;
  39. } else {
  40. /* Initial clock starts SCK=0 */
  41. priv->clk1 = 0;
  42. priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
  43. }
  44. /* Enable bitbang, SCK_OE, SDO_OE */
  45. priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */
  46. ICPU_SW_MODE_SW_SPI_SCK_OE | /* SCK_OE */
  47. ICPU_SW_MODE_SW_SPI_SDO_OE); /* SDO OE */
  48. /* Add CS */
  49. if (cs >= 0) {
  50. cs_value =
  51. ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |
  52. ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
  53. } else {
  54. cs_value = 0;
  55. }
  56. priv->svalue |= cs_value;
  57. /* Enable the CS in HW, Initial clock value */
  58. writel(priv->svalue | priv->clk2, priv->regs);
  59. priv->cs_active = true;
  60. debug("Activated CS%d\n", priv->cs_num);
  61. }
  62. return 0;
  63. }
  64. static int mscc_bb_spi_cs_deactivate(struct mscc_bb_priv *priv, int deact_delay)
  65. {
  66. if (priv->cs_active) {
  67. /* Keep driving the CLK to its current value while
  68. * actively deselecting CS.
  69. */
  70. u32 value = readl(priv->regs);
  71. value &= ~ICPU_SW_MODE_SW_SPI_CS_M;
  72. writel(value, priv->regs);
  73. hold_time_delay();
  74. /* Stop driving the clock, but keep CS with nCS == 1 */
  75. value &= ~ICPU_SW_MODE_SW_SPI_SCK_OE;
  76. writel(value, priv->regs);
  77. /* Deselect hold time delay */
  78. if (deact_delay)
  79. udelay(deact_delay);
  80. /* Drop everything */
  81. writel(0, priv->regs);
  82. priv->cs_active = false;
  83. debug("Deactivated CS%d\n", priv->cs_num);
  84. }
  85. return 0;
  86. }
  87. int mscc_bb_spi_claim_bus(struct udevice *dev)
  88. {
  89. return 0;
  90. }
  91. int mscc_bb_spi_release_bus(struct udevice *dev)
  92. {
  93. return 0;
  94. }
  95. int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen,
  96. const void *dout, void *din, unsigned long flags)
  97. {
  98. struct udevice *bus = dev_get_parent(dev);
  99. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  100. struct mscc_bb_priv *priv = dev_get_priv(bus);
  101. u32 i, count;
  102. const u8 *txd = dout;
  103. u8 *rxd = din;
  104. debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",
  105. dev->parent->name, dev->name, plat->cs, plat->mode, dout,
  106. din, bitlen);
  107. if (flags & SPI_XFER_BEGIN)
  108. mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);
  109. count = bitlen / 8;
  110. for (i = 0; i < count; i++) {
  111. u32 rx = 0, mask = 0x80, value;
  112. while (mask) {
  113. /* Initial condition: CLK is low. */
  114. value = priv->svalue;
  115. if (txd && txd[i] & mask)
  116. value |= ICPU_SW_MODE_SW_SPI_SDO;
  117. /* Drive data while taking CLK low. The device
  118. * we're accessing will sample on the
  119. * following rising edge and will output data
  120. * on this edge for us to be sampled at the
  121. * end of this loop.
  122. */
  123. writel(value | priv->clk1, priv->regs);
  124. /* Wait for t_setup. All devices do have a
  125. * setup-time, so we always insert some delay
  126. * here. Some devices have a very long
  127. * setup-time, which can be adjusted by the
  128. * user through vcoreiii_device->delay.
  129. */
  130. hold_time_delay();
  131. /* Drive the clock high. */
  132. writel(value | priv->clk2, priv->regs);
  133. /* Wait for t_hold. See comment about t_setup
  134. * above.
  135. */
  136. hold_time_delay();
  137. /* We sample as close to the next falling edge
  138. * as possible.
  139. */
  140. value = readl(priv->regs);
  141. if (value & ICPU_SW_MODE_SW_SPI_SDI)
  142. rx |= mask;
  143. mask >>= 1;
  144. }
  145. if (rxd) {
  146. debug("Read 0x%02x\n", rx);
  147. rxd[i] = (u8)rx;
  148. }
  149. debug("spi_xfer: byte %d/%d\n", i + 1, count);
  150. }
  151. debug("spi_xfer: done\n");
  152. if (flags & SPI_XFER_END)
  153. mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);
  154. return 0;
  155. }
  156. int mscc_bb_spi_set_speed(struct udevice *dev, unsigned int speed)
  157. {
  158. /* Accept any speed */
  159. return 0;
  160. }
  161. int mscc_bb_spi_set_mode(struct udevice *dev, unsigned int mode)
  162. {
  163. return 0;
  164. }
  165. static const struct dm_spi_ops mscc_bb_ops = {
  166. .claim_bus = mscc_bb_spi_claim_bus,
  167. .release_bus = mscc_bb_spi_release_bus,
  168. .xfer = mscc_bb_spi_xfer,
  169. .set_speed = mscc_bb_spi_set_speed,
  170. .set_mode = mscc_bb_spi_set_mode,
  171. };
  172. static const struct udevice_id mscc_bb_ids[] = {
  173. { .compatible = "mscc,luton-bb-spi" },
  174. { }
  175. };
  176. static int mscc_bb_spi_probe(struct udevice *bus)
  177. {
  178. struct mscc_bb_priv *priv = dev_get_priv(bus);
  179. debug("%s: loaded, priv %p\n", __func__, priv);
  180. priv->regs = (void __iomem *)dev_read_addr(bus);
  181. priv->deactivate_delay_us =
  182. dev_read_u32_default(bus, "spi-deactivate-delay", 0);
  183. priv->cs_active = false;
  184. return 0;
  185. }
  186. U_BOOT_DRIVER(mscc_bb) = {
  187. .name = "mscc_bb",
  188. .id = UCLASS_SPI,
  189. .of_match = mscc_bb_ids,
  190. .ops = &mscc_bb_ops,
  191. .priv_auto_alloc_size = sizeof(struct mscc_bb_priv),
  192. .probe = mscc_bb_spi_probe,
  193. };