fsl_qspi.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale QuadSPI driver.
  4. *
  5. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. * Copyright (C) 2018 Bootlin
  7. * Copyright (C) 2018 exceet electronics GmbH
  8. * Copyright (C) 2018 Kontron Electronics GmbH
  9. * Copyright 2019-2020 NXP
  10. *
  11. * This driver is a ported version of Linux Freescale QSPI driver taken from
  12. * v5.5-rc1 tag having following information.
  13. *
  14. * Transition to SPI MEM interface:
  15. * Authors:
  16. * Boris Brezillon <bbrezillon@kernel.org>
  17. * Frieder Schrempf <frieder.schrempf@kontron.de>
  18. * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  19. * Suresh Gupta <suresh.gupta@nxp.com>
  20. *
  21. * Based on the original fsl-quadspi.c spi-nor driver.
  22. * Transition to spi-mem in spi-fsl-qspi.c
  23. */
  24. #include <common.h>
  25. #include <log.h>
  26. #include <asm/io.h>
  27. #include <linux/bitops.h>
  28. #include <linux/delay.h>
  29. #include <linux/libfdt.h>
  30. #include <linux/sizes.h>
  31. #include <linux/iopoll.h>
  32. #include <dm.h>
  33. #include <linux/iopoll.h>
  34. #include <linux/sizes.h>
  35. #include <linux/err.h>
  36. #include <spi.h>
  37. #include <spi-mem.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. /*
  40. * The driver only uses one single LUT entry, that is updated on
  41. * each call of exec_op(). Index 0 is preset at boot with a basic
  42. * read operation, so let's use the last entry (15).
  43. */
  44. #define SEQID_LUT 15
  45. /* Registers used by the driver */
  46. #define QUADSPI_MCR 0x00
  47. #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
  48. #define QUADSPI_MCR_MDIS_MASK BIT(14)
  49. #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
  50. #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
  51. #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
  52. #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
  53. #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
  54. #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
  55. #define QUADSPI_IPCR 0x08
  56. #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
  57. #define QUADSPI_FLSHCR 0x0c
  58. #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
  59. #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
  60. #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
  61. #define QUADSPI_BUF3CR 0x1c
  62. #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
  63. #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
  64. #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
  65. #define QUADSPI_BFGENCR 0x20
  66. #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
  67. #define QUADSPI_BUF0IND 0x30
  68. #define QUADSPI_BUF1IND 0x34
  69. #define QUADSPI_BUF2IND 0x38
  70. #define QUADSPI_SFAR 0x100
  71. #define QUADSPI_SMPR 0x108
  72. #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
  73. #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
  74. #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
  75. #define QUADSPI_SMPR_HSENA_MASK BIT(0)
  76. #define QUADSPI_RBCT 0x110
  77. #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
  78. #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
  79. #define QUADSPI_TBDR 0x154
  80. #define QUADSPI_SR 0x15c
  81. #define QUADSPI_SR_IP_ACC_MASK BIT(1)
  82. #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
  83. #define QUADSPI_FR 0x160
  84. #define QUADSPI_FR_TFF_MASK BIT(0)
  85. #define QUADSPI_RSER 0x164
  86. #define QUADSPI_RSER_TFIE BIT(0)
  87. #define QUADSPI_SPTRCLR 0x16c
  88. #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
  89. #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
  90. #define QUADSPI_SFA1AD 0x180
  91. #define QUADSPI_SFA2AD 0x184
  92. #define QUADSPI_SFB1AD 0x188
  93. #define QUADSPI_SFB2AD 0x18c
  94. #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
  95. #define QUADSPI_LUTKEY 0x300
  96. #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
  97. #define QUADSPI_LCKCR 0x304
  98. #define QUADSPI_LCKER_LOCK BIT(0)
  99. #define QUADSPI_LCKER_UNLOCK BIT(1)
  100. #define QUADSPI_LUT_BASE 0x310
  101. #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  102. #define QUADSPI_LUT_REG(idx) \
  103. (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
  104. /* Instruction set for the LUT register */
  105. #define LUT_STOP 0
  106. #define LUT_CMD 1
  107. #define LUT_ADDR 2
  108. #define LUT_DUMMY 3
  109. #define LUT_MODE 4
  110. #define LUT_MODE2 5
  111. #define LUT_MODE4 6
  112. #define LUT_FSL_READ 7
  113. #define LUT_FSL_WRITE 8
  114. #define LUT_JMP_ON_CS 9
  115. #define LUT_ADDR_DDR 10
  116. #define LUT_MODE_DDR 11
  117. #define LUT_MODE2_DDR 12
  118. #define LUT_MODE4_DDR 13
  119. #define LUT_FSL_READ_DDR 14
  120. #define LUT_FSL_WRITE_DDR 15
  121. #define LUT_DATA_LEARN 16
  122. /*
  123. * The PAD definitions for LUT register.
  124. *
  125. * The pad stands for the number of IO lines [0:3].
  126. * For example, the quad read needs four IO lines,
  127. * so you should use LUT_PAD(4).
  128. */
  129. #define LUT_PAD(x) (fls(x) - 1)
  130. /*
  131. * Macro for constructing the LUT entries with the following
  132. * register layout:
  133. *
  134. * ---------------------------------------------------
  135. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  136. * ---------------------------------------------------
  137. */
  138. #define LUT_DEF(idx, ins, pad, opr) \
  139. ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
  140. /* Controller needs driver to swap endianness */
  141. #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
  142. /* Controller needs 4x internal clock */
  143. #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
  144. /*
  145. * TKT253890, the controller needs the driver to fill the txfifo with
  146. * 16 bytes at least to trigger a data transfer, even though the extra
  147. * data won't be transferred.
  148. */
  149. #define QUADSPI_QUIRK_TKT253890 BIT(2)
  150. /* TKT245618, the controller cannot wake up from wait mode */
  151. #define QUADSPI_QUIRK_TKT245618 BIT(3)
  152. /*
  153. * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
  154. * internally. No need to add it when setting SFXXAD and SFAR registers
  155. */
  156. #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
  157. /*
  158. * Controller uses TDH bits in register QUADSPI_FLSHCR.
  159. * They need to be set in accordance with the DDR/SDR mode.
  160. */
  161. #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
  162. struct fsl_qspi_devtype_data {
  163. unsigned int rxfifo;
  164. unsigned int txfifo;
  165. unsigned int ahb_buf_size;
  166. unsigned int quirks;
  167. bool little_endian;
  168. };
  169. static const struct fsl_qspi_devtype_data vybrid_data = {
  170. .rxfifo = SZ_128,
  171. .txfifo = SZ_64,
  172. .ahb_buf_size = SZ_1K,
  173. .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
  174. .little_endian = true,
  175. };
  176. static const struct fsl_qspi_devtype_data imx6sx_data = {
  177. .rxfifo = SZ_128,
  178. .txfifo = SZ_512,
  179. .ahb_buf_size = SZ_1K,
  180. .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
  181. .little_endian = true,
  182. };
  183. static const struct fsl_qspi_devtype_data imx7d_data = {
  184. .rxfifo = SZ_128,
  185. .txfifo = SZ_512,
  186. .ahb_buf_size = SZ_1K,
  187. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  188. QUADSPI_QUIRK_USE_TDH_SETTING,
  189. .little_endian = true,
  190. };
  191. static const struct fsl_qspi_devtype_data imx6ul_data = {
  192. .rxfifo = SZ_128,
  193. .txfifo = SZ_512,
  194. .ahb_buf_size = SZ_1K,
  195. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  196. QUADSPI_QUIRK_USE_TDH_SETTING,
  197. .little_endian = true,
  198. };
  199. static const struct fsl_qspi_devtype_data ls1021a_data = {
  200. .rxfifo = SZ_128,
  201. .txfifo = SZ_64,
  202. .ahb_buf_size = SZ_1K,
  203. .quirks = 0,
  204. .little_endian = false,
  205. };
  206. static const struct fsl_qspi_devtype_data ls1088a_data = {
  207. .rxfifo = SZ_128,
  208. .txfifo = SZ_128,
  209. .ahb_buf_size = SZ_1K,
  210. .quirks = QUADSPI_QUIRK_TKT253890,
  211. .little_endian = true,
  212. };
  213. static const struct fsl_qspi_devtype_data ls2080a_data = {
  214. .rxfifo = SZ_128,
  215. .txfifo = SZ_64,
  216. .ahb_buf_size = SZ_1K,
  217. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
  218. .little_endian = true,
  219. };
  220. struct fsl_qspi {
  221. struct udevice *dev;
  222. void __iomem *iobase;
  223. void __iomem *ahb_addr;
  224. u32 memmap_phy;
  225. const struct fsl_qspi_devtype_data *devtype_data;
  226. int selected;
  227. };
  228. static inline int needs_swap_endian(struct fsl_qspi *q)
  229. {
  230. return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
  231. }
  232. static inline int needs_4x_clock(struct fsl_qspi *q)
  233. {
  234. return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
  235. }
  236. static inline int needs_fill_txfifo(struct fsl_qspi *q)
  237. {
  238. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
  239. }
  240. static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
  241. {
  242. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
  243. }
  244. static inline int needs_amba_base_offset(struct fsl_qspi *q)
  245. {
  246. return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
  247. }
  248. static inline int needs_tdh_setting(struct fsl_qspi *q)
  249. {
  250. return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
  251. }
  252. /*
  253. * An IC bug makes it necessary to rearrange the 32-bit data.
  254. * Later chips, such as IMX6SLX, have fixed this bug.
  255. */
  256. static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
  257. {
  258. return needs_swap_endian(q) ? __swab32(a) : a;
  259. }
  260. /*
  261. * R/W functions for big- or little-endian registers:
  262. * The QSPI controller's endianness is independent of
  263. * the CPU core's endianness. So far, although the CPU
  264. * core is little-endian the QSPI controller can use
  265. * big-endian or little-endian.
  266. */
  267. static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
  268. {
  269. if (q->devtype_data->little_endian)
  270. out_le32(addr, val);
  271. else
  272. out_be32(addr, val);
  273. }
  274. static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
  275. {
  276. if (q->devtype_data->little_endian)
  277. return in_le32(addr);
  278. return in_be32(addr);
  279. }
  280. static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
  281. {
  282. switch (width) {
  283. case 1:
  284. case 2:
  285. case 4:
  286. return 0;
  287. }
  288. return -ENOTSUPP;
  289. }
  290. static bool fsl_qspi_supports_op(struct spi_slave *slave,
  291. const struct spi_mem_op *op)
  292. {
  293. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  294. int ret;
  295. ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
  296. if (op->addr.nbytes)
  297. ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
  298. if (op->dummy.nbytes)
  299. ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
  300. if (op->data.nbytes)
  301. ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
  302. if (ret)
  303. return false;
  304. /*
  305. * The number of instructions needed for the op, needs
  306. * to fit into a single LUT entry.
  307. */
  308. if (op->addr.nbytes +
  309. (op->dummy.nbytes ? 1 : 0) +
  310. (op->data.nbytes ? 1 : 0) > 6)
  311. return false;
  312. /* Max 64 dummy clock cycles supported */
  313. if (op->dummy.nbytes &&
  314. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  315. return false;
  316. /* Max data length, check controller limits and alignment */
  317. if (op->data.dir == SPI_MEM_DATA_IN &&
  318. (op->data.nbytes > q->devtype_data->ahb_buf_size ||
  319. (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
  320. !IS_ALIGNED(op->data.nbytes, 8))))
  321. return false;
  322. if (op->data.dir == SPI_MEM_DATA_OUT &&
  323. op->data.nbytes > q->devtype_data->txfifo)
  324. return false;
  325. return true;
  326. }
  327. static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
  328. const struct spi_mem_op *op)
  329. {
  330. void __iomem *base = q->iobase;
  331. u32 lutval[4] = {};
  332. int lutidx = 1, i;
  333. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  334. op->cmd.opcode);
  335. /*
  336. * For some unknown reason, using LUT_ADDR doesn't work in some
  337. * cases (at least with only one byte long addresses), so
  338. * let's use LUT_MODE to write the address bytes one by one
  339. */
  340. for (i = 0; i < op->addr.nbytes; i++) {
  341. u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
  342. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
  343. LUT_PAD(op->addr.buswidth),
  344. addrbyte);
  345. lutidx++;
  346. }
  347. if (op->dummy.nbytes) {
  348. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  349. LUT_PAD(op->dummy.buswidth),
  350. op->dummy.nbytes * 8 /
  351. op->dummy.buswidth);
  352. lutidx++;
  353. }
  354. if (op->data.nbytes) {
  355. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  356. op->data.dir == SPI_MEM_DATA_IN ?
  357. LUT_FSL_READ : LUT_FSL_WRITE,
  358. LUT_PAD(op->data.buswidth),
  359. 0);
  360. lutidx++;
  361. }
  362. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  363. /* unlock LUT */
  364. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  365. qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
  366. dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  367. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  368. /* fill LUT */
  369. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  370. qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
  371. /* lock LUT */
  372. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  373. qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
  374. }
  375. /*
  376. * If we have changed the content of the flash by writing or erasing, or if we
  377. * read from flash with a different offset into the page buffer, we need to
  378. * invalidate the AHB buffer. If we do not do so, we may read out the wrong
  379. * data. The spec tells us reset the AHB domain and Serial Flash domain at
  380. * the same time.
  381. */
  382. static void fsl_qspi_invalidate(struct fsl_qspi *q)
  383. {
  384. u32 reg;
  385. reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
  386. reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
  387. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  388. /*
  389. * The minimum delay : 1 AHB + 2 SFCK clocks.
  390. * Delay 1 us is enough.
  391. */
  392. udelay(1);
  393. reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
  394. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  395. }
  396. static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
  397. {
  398. struct dm_spi_slave_platdata *plat =
  399. dev_get_parent_platdata(slave->dev);
  400. if (q->selected == plat->cs)
  401. return;
  402. q->selected = plat->cs;
  403. fsl_qspi_invalidate(q);
  404. }
  405. static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
  406. {
  407. memcpy_fromio(op->data.buf.in,
  408. q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
  409. op->data.nbytes);
  410. }
  411. static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
  412. const struct spi_mem_op *op)
  413. {
  414. void __iomem *base = q->iobase;
  415. int i;
  416. u32 val;
  417. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  418. memcpy(&val, op->data.buf.out + i, 4);
  419. val = fsl_qspi_endian_xchg(q, val);
  420. qspi_writel(q, val, base + QUADSPI_TBDR);
  421. }
  422. if (i < op->data.nbytes) {
  423. memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
  424. val = fsl_qspi_endian_xchg(q, val);
  425. qspi_writel(q, val, base + QUADSPI_TBDR);
  426. }
  427. if (needs_fill_txfifo(q)) {
  428. for (i = op->data.nbytes; i < 16; i += 4)
  429. qspi_writel(q, 0, base + QUADSPI_TBDR);
  430. }
  431. }
  432. static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
  433. const struct spi_mem_op *op)
  434. {
  435. void __iomem *base = q->iobase;
  436. int i;
  437. u8 *buf = op->data.buf.in;
  438. u32 val;
  439. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  440. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  441. val = fsl_qspi_endian_xchg(q, val);
  442. memcpy(buf + i, &val, 4);
  443. }
  444. if (i < op->data.nbytes) {
  445. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  446. val = fsl_qspi_endian_xchg(q, val);
  447. memcpy(buf + i, &val, op->data.nbytes - i);
  448. }
  449. }
  450. static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
  451. u32 mask, u32 delay_us, u32 timeout_us)
  452. {
  453. u32 reg;
  454. if (!q->devtype_data->little_endian)
  455. mask = (u32)cpu_to_be32(mask);
  456. return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
  457. }
  458. static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
  459. {
  460. void __iomem *base = q->iobase;
  461. int err = 0;
  462. /*
  463. * Always start the sequence at the same index since we update
  464. * the LUT at each exec_op() call. And also specify the DATA
  465. * length, since it's has not been specified in the LUT.
  466. */
  467. qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
  468. base + QUADSPI_IPCR);
  469. /* wait for the controller being ready */
  470. err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
  471. (QUADSPI_SR_IP_ACC_MASK |
  472. QUADSPI_SR_AHB_ACC_MASK),
  473. 10, 1000);
  474. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  475. fsl_qspi_read_rxfifo(q, op);
  476. return err;
  477. }
  478. static int fsl_qspi_exec_op(struct spi_slave *slave,
  479. const struct spi_mem_op *op)
  480. {
  481. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  482. void __iomem *base = q->iobase;
  483. u32 addr_offset = 0;
  484. int err = 0;
  485. /* wait for the controller being ready */
  486. fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
  487. QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
  488. fsl_qspi_select_mem(q, slave);
  489. if (needs_amba_base_offset(q))
  490. addr_offset = q->memmap_phy;
  491. qspi_writel(q,
  492. q->selected * q->devtype_data->ahb_buf_size + addr_offset,
  493. base + QUADSPI_SFAR);
  494. qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
  495. QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
  496. base + QUADSPI_MCR);
  497. qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
  498. base + QUADSPI_SPTRCLR);
  499. fsl_qspi_prepare_lut(q, op);
  500. /*
  501. * If we have large chunks of data, we read them through the AHB bus
  502. * by accessing the mapped memory. In all other cases we use
  503. * IP commands to access the flash.
  504. */
  505. if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
  506. op->data.dir == SPI_MEM_DATA_IN) {
  507. fsl_qspi_read_ahb(q, op);
  508. } else {
  509. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
  510. QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
  511. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  512. fsl_qspi_fill_txfifo(q, op);
  513. err = fsl_qspi_do_op(q, op);
  514. }
  515. /* Invalidate the data in the AHB buffer. */
  516. fsl_qspi_invalidate(q);
  517. return err;
  518. }
  519. static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
  520. struct spi_mem_op *op)
  521. {
  522. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  523. if (op->data.dir == SPI_MEM_DATA_OUT) {
  524. if (op->data.nbytes > q->devtype_data->txfifo)
  525. op->data.nbytes = q->devtype_data->txfifo;
  526. } else {
  527. if (op->data.nbytes > q->devtype_data->ahb_buf_size)
  528. op->data.nbytes = q->devtype_data->ahb_buf_size;
  529. else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
  530. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  531. }
  532. return 0;
  533. }
  534. static int fsl_qspi_default_setup(struct fsl_qspi *q)
  535. {
  536. void __iomem *base = q->iobase;
  537. u32 reg, addr_offset = 0;
  538. /* Reset the module */
  539. qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
  540. base + QUADSPI_MCR);
  541. udelay(1);
  542. /* Disable the module */
  543. qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
  544. base + QUADSPI_MCR);
  545. /*
  546. * Previous boot stages (BootROM, bootloader) might have used DDR
  547. * mode and did not clear the TDH bits. As we currently use SDR mode
  548. * only, clear the TDH bits if necessary.
  549. */
  550. if (needs_tdh_setting(q))
  551. qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
  552. ~QUADSPI_FLSHCR_TDH_MASK,
  553. base + QUADSPI_FLSHCR);
  554. reg = qspi_readl(q, base + QUADSPI_SMPR);
  555. qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
  556. | QUADSPI_SMPR_FSPHS_MASK
  557. | QUADSPI_SMPR_HSENA_MASK
  558. | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
  559. /* We only use the buffer3 for AHB read */
  560. qspi_writel(q, 0, base + QUADSPI_BUF0IND);
  561. qspi_writel(q, 0, base + QUADSPI_BUF1IND);
  562. qspi_writel(q, 0, base + QUADSPI_BUF2IND);
  563. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
  564. q->iobase + QUADSPI_BFGENCR);
  565. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
  566. qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
  567. QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
  568. base + QUADSPI_BUF3CR);
  569. if (needs_amba_base_offset(q))
  570. addr_offset = q->memmap_phy;
  571. /*
  572. * In HW there can be a maximum of four chips on two buses with
  573. * two chip selects on each bus. We use four chip selects in SW
  574. * to differentiate between the four chips.
  575. * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
  576. * SFB2AD accordingly.
  577. */
  578. qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
  579. base + QUADSPI_SFA1AD);
  580. qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
  581. base + QUADSPI_SFA2AD);
  582. qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
  583. base + QUADSPI_SFB1AD);
  584. qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
  585. base + QUADSPI_SFB2AD);
  586. q->selected = -1;
  587. /* Enable the module */
  588. qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
  589. base + QUADSPI_MCR);
  590. return 0;
  591. }
  592. static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
  593. .adjust_op_size = fsl_qspi_adjust_op_size,
  594. .supports_op = fsl_qspi_supports_op,
  595. .exec_op = fsl_qspi_exec_op,
  596. };
  597. static int fsl_qspi_probe(struct udevice *bus)
  598. {
  599. struct dm_spi_bus *dm_bus = bus->uclass_priv;
  600. struct fsl_qspi *q = dev_get_priv(bus);
  601. const void *blob = gd->fdt_blob;
  602. int node = dev_of_offset(bus);
  603. struct fdt_resource res;
  604. int ret;
  605. q->dev = bus;
  606. q->devtype_data = (struct fsl_qspi_devtype_data *)
  607. dev_get_driver_data(bus);
  608. /* find the resources */
  609. ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
  610. &res);
  611. if (ret) {
  612. dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
  613. return -ENOMEM;
  614. }
  615. q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  616. ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  617. "QuadSPI-memory", &res);
  618. if (ret) {
  619. dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
  620. return -ENOMEM;
  621. }
  622. q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  623. q->memmap_phy = res.start;
  624. dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  625. 66000000);
  626. fsl_qspi_default_setup(q);
  627. return 0;
  628. }
  629. static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  630. const void *dout, void *din, unsigned long flags)
  631. {
  632. return 0;
  633. }
  634. static int fsl_qspi_claim_bus(struct udevice *dev)
  635. {
  636. return 0;
  637. }
  638. static int fsl_qspi_release_bus(struct udevice *dev)
  639. {
  640. return 0;
  641. }
  642. static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
  643. {
  644. return 0;
  645. }
  646. static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
  647. {
  648. return 0;
  649. }
  650. static const struct dm_spi_ops fsl_qspi_ops = {
  651. .claim_bus = fsl_qspi_claim_bus,
  652. .release_bus = fsl_qspi_release_bus,
  653. .xfer = fsl_qspi_xfer,
  654. .set_speed = fsl_qspi_set_speed,
  655. .set_mode = fsl_qspi_set_mode,
  656. .mem_ops = &fsl_qspi_mem_ops,
  657. };
  658. static const struct udevice_id fsl_qspi_ids[] = {
  659. { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
  660. { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
  661. { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
  662. { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
  663. { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
  664. { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
  665. { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
  666. { }
  667. };
  668. U_BOOT_DRIVER(fsl_qspi) = {
  669. .name = "fsl_qspi",
  670. .id = UCLASS_SPI,
  671. .of_match = fsl_qspi_ids,
  672. .ops = &fsl_qspi_ops,
  673. .priv_auto_alloc_size = sizeof(struct fsl_qspi),
  674. .probe = fsl_qspi_probe,
  675. };