fsl_dspi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. * Chao Fu (B44548@freescale.com)
  9. * Haikun Wang (B53464@freescale.com)
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <common.h>
  15. #include <log.h>
  16. #include <spi.h>
  17. #include <malloc.h>
  18. #include <asm/io.h>
  19. #include <fdtdec.h>
  20. #ifndef CONFIG_M68K
  21. #include <asm/arch/clock.h>
  22. #endif
  23. #include <fsl_dspi.h>
  24. #include <linux/bitops.h>
  25. #include <linux/delay.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* fsl_dspi_platdata flags */
  28. #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
  29. /* idle data value */
  30. #define DSPI_IDLE_VAL 0x0
  31. /* max chipselect signals number */
  32. #define FSL_DSPI_MAX_CHIPSELECT 6
  33. /* default SCK frequency, unit: HZ */
  34. #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
  35. /* tx/rx data wait timeout value, unit: us */
  36. #define DSPI_TXRX_WAIT_TIMEOUT 1000000
  37. /* CTAR register pre-configure value */
  38. #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
  39. DSPI_CTAR_PCSSCK_1CLK | \
  40. DSPI_CTAR_PASC(0) | \
  41. DSPI_CTAR_PDT(0) | \
  42. DSPI_CTAR_CSSCK(0) | \
  43. DSPI_CTAR_ASC(0) | \
  44. DSPI_CTAR_DT(0))
  45. /* CTAR register pre-configure mask */
  46. #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
  47. DSPI_CTAR_PCSSCK(3) | \
  48. DSPI_CTAR_PASC(3) | \
  49. DSPI_CTAR_PDT(3) | \
  50. DSPI_CTAR_CSSCK(15) | \
  51. DSPI_CTAR_ASC(15) | \
  52. DSPI_CTAR_DT(15))
  53. /**
  54. * struct fsl_dspi_platdata - platform data for Freescale DSPI
  55. *
  56. * @flags: Flags for DSPI DSPI_FLAG_...
  57. * @speed_hz: Default SCK frequency
  58. * @num_chipselect: Number of DSPI chipselect signals
  59. * @regs_addr: Base address of DSPI registers
  60. */
  61. struct fsl_dspi_platdata {
  62. uint flags;
  63. uint speed_hz;
  64. uint num_chipselect;
  65. fdt_addr_t regs_addr;
  66. };
  67. /**
  68. * struct fsl_dspi_priv - private data for Freescale DSPI
  69. *
  70. * @flags: Flags for DSPI DSPI_FLAG_...
  71. * @mode: SPI mode to use for slave device (see SPI mode flags)
  72. * @mcr_val: MCR register configure value
  73. * @bus_clk: DSPI input clk frequency
  74. * @speed_hz: Default SCK frequency
  75. * @charbit: How many bits in every transfer
  76. * @num_chipselect: Number of DSPI chipselect signals
  77. * @ctar_val: CTAR register configure value of per chipselect slave device
  78. * @regs: Point to DSPI register structure for I/O access
  79. */
  80. struct fsl_dspi_priv {
  81. uint flags;
  82. uint mode;
  83. uint mcr_val;
  84. uint bus_clk;
  85. uint speed_hz;
  86. uint charbit;
  87. uint num_chipselect;
  88. uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
  89. struct dspi *regs;
  90. };
  91. __weak void cpu_dspi_port_conf(void)
  92. {
  93. }
  94. __weak int cpu_dspi_claim_bus(uint bus, uint cs)
  95. {
  96. return 0;
  97. }
  98. __weak void cpu_dspi_release_bus(uint bus, uint cs)
  99. {
  100. }
  101. static uint dspi_read32(uint flags, uint *addr)
  102. {
  103. return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
  104. in_be32(addr) : in_le32(addr);
  105. }
  106. static void dspi_write32(uint flags, uint *addr, uint val)
  107. {
  108. flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
  109. out_be32(addr, val) : out_le32(addr, val);
  110. }
  111. static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
  112. {
  113. uint mcr_val;
  114. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  115. if (halt)
  116. mcr_val |= DSPI_MCR_HALT;
  117. else
  118. mcr_val &= ~DSPI_MCR_HALT;
  119. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  120. }
  121. static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
  122. {
  123. /* halt DSPI module */
  124. dspi_halt(priv, 1);
  125. dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
  126. /* resume module */
  127. dspi_halt(priv, 0);
  128. priv->mcr_val = cfg_val;
  129. }
  130. static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
  131. uint cs, uint state)
  132. {
  133. uint mcr_val;
  134. dspi_halt(priv, 1);
  135. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  136. if (state & SPI_CS_HIGH)
  137. /* CSx inactive state is low */
  138. mcr_val &= ~DSPI_MCR_PCSIS(cs);
  139. else
  140. /* CSx inactive state is high */
  141. mcr_val |= DSPI_MCR_PCSIS(cs);
  142. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  143. dspi_halt(priv, 0);
  144. }
  145. static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
  146. uint cs, uint mode)
  147. {
  148. uint bus_setup;
  149. bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
  150. bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
  151. bus_setup |= priv->ctar_val[cs];
  152. bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
  153. if (mode & SPI_CPOL)
  154. bus_setup |= DSPI_CTAR_CPOL;
  155. if (mode & SPI_CPHA)
  156. bus_setup |= DSPI_CTAR_CPHA;
  157. if (mode & SPI_LSB_FIRST)
  158. bus_setup |= DSPI_CTAR_LSBFE;
  159. dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
  160. priv->charbit =
  161. ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
  162. DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
  163. return 0;
  164. }
  165. static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
  166. {
  167. uint mcr_val;
  168. dspi_halt(priv, 1);
  169. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  170. /* flush RX and TX FIFO */
  171. mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  172. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  173. dspi_halt(priv, 0);
  174. }
  175. static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
  176. {
  177. int timeout = DSPI_TXRX_WAIT_TIMEOUT;
  178. /* wait for empty entries in TXFIFO or timeout */
  179. while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
  180. timeout--)
  181. udelay(1);
  182. if (timeout >= 0)
  183. dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
  184. else
  185. debug("dspi_tx: waiting timeout!\n");
  186. }
  187. static u16 dspi_rx(struct fsl_dspi_priv *priv)
  188. {
  189. int timeout = DSPI_TXRX_WAIT_TIMEOUT;
  190. /* wait for valid entries in RXFIFO or timeout */
  191. while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
  192. timeout--)
  193. udelay(1);
  194. if (timeout >= 0)
  195. return (u16)DSPI_RFR_RXDATA(
  196. dspi_read32(priv->flags, &priv->regs->rfr));
  197. else {
  198. debug("dspi_rx: waiting timeout!\n");
  199. return (u16)(~0);
  200. }
  201. }
  202. static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
  203. const void *dout, void *din, unsigned long flags)
  204. {
  205. u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
  206. u8 *spi_rd = NULL, *spi_wr = NULL;
  207. static u32 ctrl;
  208. uint len = bitlen >> 3;
  209. if (priv->charbit == 16) {
  210. bitlen >>= 1;
  211. spi_wr16 = (u16 *)dout;
  212. spi_rd16 = (u16 *)din;
  213. } else {
  214. spi_wr = (u8 *)dout;
  215. spi_rd = (u8 *)din;
  216. }
  217. if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
  218. ctrl |= DSPI_TFR_CONT;
  219. ctrl = ctrl & DSPI_TFR_CONT;
  220. ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
  221. if (len > 1) {
  222. int tmp_len = len - 1;
  223. while (tmp_len--) {
  224. if ((dout != NULL) && (din != NULL)) {
  225. if (priv->charbit == 16) {
  226. dspi_tx(priv, ctrl, *spi_wr16++);
  227. *spi_rd16++ = dspi_rx(priv);
  228. }
  229. else {
  230. dspi_tx(priv, ctrl, *spi_wr++);
  231. *spi_rd++ = dspi_rx(priv);
  232. }
  233. }
  234. else if (dout != NULL) {
  235. if (priv->charbit == 16)
  236. dspi_tx(priv, ctrl, *spi_wr16++);
  237. else
  238. dspi_tx(priv, ctrl, *spi_wr++);
  239. dspi_rx(priv);
  240. }
  241. else if (din != NULL) {
  242. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  243. if (priv->charbit == 16)
  244. *spi_rd16++ = dspi_rx(priv);
  245. else
  246. *spi_rd++ = dspi_rx(priv);
  247. }
  248. }
  249. len = 1; /* remaining byte */
  250. }
  251. if ((flags & SPI_XFER_END) == SPI_XFER_END)
  252. ctrl &= ~DSPI_TFR_CONT;
  253. if (len) {
  254. if ((dout != NULL) && (din != NULL)) {
  255. if (priv->charbit == 16) {
  256. dspi_tx(priv, ctrl, *spi_wr16++);
  257. *spi_rd16++ = dspi_rx(priv);
  258. }
  259. else {
  260. dspi_tx(priv, ctrl, *spi_wr++);
  261. *spi_rd++ = dspi_rx(priv);
  262. }
  263. }
  264. else if (dout != NULL) {
  265. if (priv->charbit == 16)
  266. dspi_tx(priv, ctrl, *spi_wr16);
  267. else
  268. dspi_tx(priv, ctrl, *spi_wr);
  269. dspi_rx(priv);
  270. }
  271. else if (din != NULL) {
  272. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  273. if (priv->charbit == 16)
  274. *spi_rd16 = dspi_rx(priv);
  275. else
  276. *spi_rd = dspi_rx(priv);
  277. }
  278. } else {
  279. /* dummy read */
  280. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  281. dspi_rx(priv);
  282. }
  283. return 0;
  284. }
  285. /**
  286. * Calculate the divide value between input clk frequency and expected SCK frequency
  287. * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
  288. * Dbr: use default value 0
  289. *
  290. * @pbr: return Baud Rate Prescaler value
  291. * @br: return Baud Rate Scaler value
  292. * @speed_hz: expected SCK frequency
  293. * @clkrate: input clk frequency
  294. */
  295. static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
  296. int speed_hz, uint clkrate)
  297. {
  298. /* Valid baud rate pre-scaler values */
  299. int pbr_tbl[4] = {2, 3, 5, 7};
  300. int brs[16] = {2, 4, 6, 8,
  301. 16, 32, 64, 128,
  302. 256, 512, 1024, 2048,
  303. 4096, 8192, 16384, 32768};
  304. int temp, i = 0, j = 0;
  305. temp = clkrate / speed_hz;
  306. for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
  307. for (j = 0; j < ARRAY_SIZE(brs); j++) {
  308. if (pbr_tbl[i] * brs[j] >= temp) {
  309. *pbr = i;
  310. *br = j;
  311. return 0;
  312. }
  313. }
  314. debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
  315. debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
  316. *pbr = ARRAY_SIZE(pbr_tbl) - 1;
  317. *br = ARRAY_SIZE(brs) - 1;
  318. return -EINVAL;
  319. }
  320. static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
  321. {
  322. int ret;
  323. uint bus_setup;
  324. int best_i, best_j, bus_clk;
  325. bus_clk = priv->bus_clk;
  326. debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
  327. speed, bus_clk);
  328. bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
  329. bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
  330. ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
  331. if (ret) {
  332. speed = priv->speed_hz;
  333. debug("DSPI set_speed use default SCK rate %u.\n", speed);
  334. fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
  335. }
  336. bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
  337. dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
  338. priv->speed_hz = speed;
  339. return 0;
  340. }
  341. static int fsl_dspi_child_pre_probe(struct udevice *dev)
  342. {
  343. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  344. struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
  345. if (slave_plat->cs >= priv->num_chipselect) {
  346. debug("DSPI invalid chipselect number %d(max %d)!\n",
  347. slave_plat->cs, priv->num_chipselect - 1);
  348. return -EINVAL;
  349. }
  350. priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
  351. debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
  352. slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
  353. return 0;
  354. }
  355. static int fsl_dspi_probe(struct udevice *bus)
  356. {
  357. struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
  358. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  359. struct dm_spi_bus *dm_spi_bus;
  360. uint mcr_cfg_val;
  361. dm_spi_bus = bus->uclass_priv;
  362. /* cpu speical pin muxing configure */
  363. cpu_dspi_port_conf();
  364. /* get input clk frequency */
  365. priv->regs = (struct dspi *)plat->regs_addr;
  366. priv->flags = plat->flags;
  367. #ifdef CONFIG_M68K
  368. priv->bus_clk = gd->bus_clk;
  369. #else
  370. priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
  371. #endif
  372. priv->num_chipselect = plat->num_chipselect;
  373. priv->speed_hz = plat->speed_hz;
  374. /* frame data length in bits, default 8bits */
  375. priv->charbit = 8;
  376. dm_spi_bus->max_hz = plat->speed_hz;
  377. /* default: all CS signals inactive state is high */
  378. mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
  379. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  380. fsl_dspi_init_mcr(priv, mcr_cfg_val);
  381. debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
  382. return 0;
  383. }
  384. static int fsl_dspi_claim_bus(struct udevice *dev)
  385. {
  386. uint sr_val;
  387. struct fsl_dspi_priv *priv;
  388. struct udevice *bus = dev->parent;
  389. struct dm_spi_slave_platdata *slave_plat =
  390. dev_get_parent_platdata(dev);
  391. priv = dev_get_priv(bus);
  392. /* processor special preparation work */
  393. cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
  394. /* configure transfer mode */
  395. fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
  396. /* configure active state of CSX */
  397. fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
  398. priv->mode);
  399. fsl_dspi_clr_fifo(priv);
  400. /* check module TX and RX status */
  401. sr_val = dspi_read32(priv->flags, &priv->regs->sr);
  402. if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
  403. debug("DSPI RX/TX not ready!\n");
  404. return -EIO;
  405. }
  406. return 0;
  407. }
  408. static int fsl_dspi_release_bus(struct udevice *dev)
  409. {
  410. struct udevice *bus = dev->parent;
  411. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  412. struct dm_spi_slave_platdata *slave_plat =
  413. dev_get_parent_platdata(dev);
  414. /* halt module */
  415. dspi_halt(priv, 1);
  416. /* processor special release work */
  417. cpu_dspi_release_bus(bus->seq, slave_plat->cs);
  418. return 0;
  419. }
  420. /**
  421. * This function doesn't do anything except help with debugging
  422. */
  423. static int fsl_dspi_bind(struct udevice *bus)
  424. {
  425. debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq);
  426. return 0;
  427. }
  428. static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
  429. {
  430. fdt_addr_t addr;
  431. struct fsl_dspi_platdata *plat = bus->platdata;
  432. const void *blob = gd->fdt_blob;
  433. int node = dev_of_offset(bus);
  434. if (fdtdec_get_bool(blob, node, "big-endian"))
  435. plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
  436. plat->num_chipselect =
  437. fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
  438. addr = devfdt_get_addr(bus);
  439. if (addr == FDT_ADDR_T_NONE) {
  440. debug("DSPI: Can't get base address or size\n");
  441. return -ENOMEM;
  442. }
  443. plat->regs_addr = addr;
  444. plat->speed_hz = fdtdec_get_int(blob,
  445. node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
  446. debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
  447. &plat->regs_addr, plat->speed_hz,
  448. plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
  449. plat->num_chipselect);
  450. return 0;
  451. }
  452. static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
  453. const void *dout, void *din, unsigned long flags)
  454. {
  455. struct fsl_dspi_priv *priv;
  456. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  457. struct udevice *bus;
  458. bus = dev->parent;
  459. priv = dev_get_priv(bus);
  460. return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
  461. }
  462. static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
  463. {
  464. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  465. return fsl_dspi_cfg_speed(priv, speed);
  466. }
  467. static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
  468. {
  469. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  470. debug("DSPI set_mode: mode 0x%x.\n", mode);
  471. /*
  472. * We store some chipselect special configure value in priv->ctar_val,
  473. * and we can't get the correct chipselect number here,
  474. * so just store mode value.
  475. * Do really configuration when claim_bus.
  476. */
  477. priv->mode = mode;
  478. return 0;
  479. }
  480. static const struct dm_spi_ops fsl_dspi_ops = {
  481. .claim_bus = fsl_dspi_claim_bus,
  482. .release_bus = fsl_dspi_release_bus,
  483. .xfer = fsl_dspi_xfer,
  484. .set_speed = fsl_dspi_set_speed,
  485. .set_mode = fsl_dspi_set_mode,
  486. };
  487. static const struct udevice_id fsl_dspi_ids[] = {
  488. { .compatible = "fsl,vf610-dspi" },
  489. { }
  490. };
  491. U_BOOT_DRIVER(fsl_dspi) = {
  492. .name = "fsl_dspi",
  493. .id = UCLASS_SPI,
  494. .of_match = fsl_dspi_ids,
  495. .ops = &fsl_dspi_ops,
  496. .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
  497. .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
  498. .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
  499. .probe = fsl_dspi_probe,
  500. .child_pre_probe = fsl_dspi_child_pre_probe,
  501. .bind = fsl_dspi_bind,
  502. };