phy-mtk-tphy.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015 - 2019 MediaTek Inc.
  4. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  5. * Ryder Lee <ryder.lee@mediatek.com>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <generic-phy.h>
  11. #include <malloc.h>
  12. #include <mapmem.h>
  13. #include <asm/io.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/devres.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <dt-bindings/phy/phy.h>
  19. /* version V1 sub-banks offset base address */
  20. /* banks shared by multiple phys */
  21. #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
  22. #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
  23. #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
  24. /* u2 phy bank */
  25. #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
  26. /* u3/pcie/sata phy banks */
  27. #define SSUSB_SIFSLV_V1_U3PHYD 0x000
  28. #define SSUSB_SIFSLV_V1_U3PHYA 0x200
  29. /* version V2 sub-banks offset base address */
  30. /* u2 phy banks */
  31. #define SSUSB_SIFSLV_V2_MISC 0x000
  32. #define SSUSB_SIFSLV_V2_U2FREQ 0x100
  33. #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
  34. /* u3/pcie/sata phy banks */
  35. #define SSUSB_SIFSLV_V2_SPLLC 0x000
  36. #define SSUSB_SIFSLV_V2_CHIP 0x100
  37. #define SSUSB_SIFSLV_V2_U3PHYD 0x200
  38. #define SSUSB_SIFSLV_V2_U3PHYA 0x400
  39. #define U3P_USBPHYACR0 0x000
  40. #define PA0_RG_U2PLL_FORCE_ON BIT(15)
  41. #define PA0_RG_USB20_INTR_EN BIT(5)
  42. #define U3P_USBPHYACR5 0x014
  43. #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
  44. #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
  45. #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
  46. #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
  47. #define U3P_USBPHYACR6 0x018
  48. #define PA6_RG_U2_BC11_SW_EN BIT(23)
  49. #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
  50. #define PA6_RG_U2_SQTH GENMASK(3, 0)
  51. #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
  52. #define U3P_U2PHYACR4 0x020
  53. #define P2C_RG_USB20_GPIO_CTL BIT(9)
  54. #define P2C_USB20_GPIO_MODE BIT(8)
  55. #define P2C_U2_GPIO_CTR_MSK \
  56. (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  57. #define U3P_U2PHYDTM0 0x068
  58. #define P2C_FORCE_UART_EN BIT(26)
  59. #define P2C_FORCE_DATAIN BIT(23)
  60. #define P2C_FORCE_DM_PULLDOWN BIT(21)
  61. #define P2C_FORCE_DP_PULLDOWN BIT(20)
  62. #define P2C_FORCE_XCVRSEL BIT(19)
  63. #define P2C_FORCE_SUSPENDM BIT(18)
  64. #define P2C_FORCE_TERMSEL BIT(17)
  65. #define P2C_RG_DATAIN GENMASK(13, 10)
  66. #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
  67. #define P2C_RG_DMPULLDOWN BIT(7)
  68. #define P2C_RG_DPPULLDOWN BIT(6)
  69. #define P2C_RG_XCVRSEL GENMASK(5, 4)
  70. #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
  71. #define P2C_RG_SUSPENDM BIT(3)
  72. #define P2C_RG_TERMSEL BIT(2)
  73. #define P2C_DTM0_PART_MASK \
  74. (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
  75. P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
  76. P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
  77. P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
  78. #define U3P_U2PHYDTM1 0x06C
  79. #define P2C_RG_UART_EN BIT(16)
  80. #define P2C_FORCE_IDDIG BIT(9)
  81. #define P2C_RG_VBUSVALID BIT(5)
  82. #define P2C_RG_SESSEND BIT(4)
  83. #define P2C_RG_AVALID BIT(2)
  84. #define P2C_RG_IDDIG BIT(1)
  85. #define U3P_U3_CHIP_GPIO_CTLD 0x0c
  86. #define P3C_REG_IP_SW_RST BIT(31)
  87. #define P3C_MCU_BUS_CK_GATE_EN BIT(30)
  88. #define P3C_FORCE_IP_SW_RST BIT(29)
  89. #define U3P_U3_CHIP_GPIO_CTLE 0x10
  90. #define P3C_RG_SWRST_U3_PHYD BIT(25)
  91. #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
  92. #define U3P_U3_PHYA_REG0 0x000
  93. #define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
  94. #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
  95. #define U3P_U3_PHYA_REG1 0x004
  96. #define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
  97. #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
  98. #define U3P_U3_PHYA_REG6 0x018
  99. #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
  100. #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
  101. #define U3P_U3_PHYA_REG9 0x024
  102. #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
  103. #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
  104. #define U3P_U3_PHYA_DA_REG0 0x100
  105. #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
  106. #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
  107. #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
  108. #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
  109. #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
  110. #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
  111. #define U3P_U3_PHYA_DA_REG4 0x108
  112. #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
  113. #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
  114. #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
  115. #define U3P_U3_PHYA_DA_REG5 0x10c
  116. #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
  117. #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
  118. #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
  119. #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
  120. #define U3P_U3_PHYA_DA_REG6 0x110
  121. #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
  122. #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
  123. #define U3P_U3_PHYA_DA_REG7 0x114
  124. #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
  125. #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
  126. #define U3P_U3_PHYA_DA_REG20 0x13c
  127. #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
  128. #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
  129. #define U3P_U3_PHYA_DA_REG25 0x148
  130. #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
  131. #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
  132. #define U3P_U3_PHYD_LFPS1 0x00c
  133. #define P3D_RG_FWAKE_TH GENMASK(21, 16)
  134. #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
  135. #define U3P_U3_PHYD_CDR1 0x05c
  136. #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
  137. #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
  138. #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
  139. #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
  140. #define U3P_U3_PHYD_RXDET1 0x128
  141. #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
  142. #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
  143. #define U3P_U3_PHYD_RXDET2 0x12c
  144. #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
  145. #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
  146. #define U3P_SPLLC_XTALCTL3 0x018
  147. #define XC3_RG_U3_XTAL_RX_PWD BIT(9)
  148. #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
  149. enum mtk_phy_version {
  150. MTK_TPHY_V1 = 1,
  151. MTK_TPHY_V2,
  152. };
  153. struct u2phy_banks {
  154. void __iomem *misc;
  155. void __iomem *fmreg;
  156. void __iomem *com;
  157. };
  158. struct u3phy_banks {
  159. void __iomem *spllc;
  160. void __iomem *chip;
  161. void __iomem *phyd; /* include u3phyd_bank2 */
  162. void __iomem *phya; /* include u3phya_da */
  163. };
  164. struct mtk_phy_instance {
  165. void __iomem *port_base;
  166. const struct device_node *np;
  167. union {
  168. struct u2phy_banks u2_banks;
  169. struct u3phy_banks u3_banks;
  170. };
  171. struct clk ref_clk; /* reference clock of (digital) phy */
  172. struct clk da_ref_clk; /* reference clock of analog phy */
  173. u32 index;
  174. u32 type;
  175. };
  176. struct mtk_tphy {
  177. struct udevice *dev;
  178. void __iomem *sif_base;
  179. enum mtk_phy_version version;
  180. struct mtk_phy_instance **phys;
  181. int nphys;
  182. };
  183. static void u2_phy_instance_init(struct mtk_tphy *tphy,
  184. struct mtk_phy_instance *instance)
  185. {
  186. struct u2phy_banks *u2_banks = &instance->u2_banks;
  187. /* switch to USB function, and enable usb pll */
  188. clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
  189. P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
  190. P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
  191. clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
  192. setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
  193. /* disable switch 100uA current to SSUSB */
  194. clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
  195. clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
  196. /* DP/DM BC1.1 path Disable */
  197. clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
  198. PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
  199. PA6_RG_U2_SQTH_VAL(2));
  200. /* set HS slew rate */
  201. clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
  202. PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
  203. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  204. }
  205. static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
  206. struct mtk_phy_instance *instance)
  207. {
  208. struct u2phy_banks *u2_banks = &instance->u2_banks;
  209. clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
  210. P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
  211. /* OTG Enable */
  212. setbits_le32(u2_banks->com + U3P_USBPHYACR6,
  213. PA6_RG_U2_OTG_VBUSCMP_EN);
  214. clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
  215. P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
  216. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  217. }
  218. static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
  219. struct mtk_phy_instance *instance)
  220. {
  221. struct u2phy_banks *u2_banks = &instance->u2_banks;
  222. clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
  223. P2C_RG_XCVRSEL | P2C_RG_DATAIN);
  224. /* OTG Disable */
  225. clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
  226. PA6_RG_U2_OTG_VBUSCMP_EN);
  227. clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
  228. P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
  229. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  230. }
  231. static void u3_phy_instance_init(struct mtk_tphy *tphy,
  232. struct mtk_phy_instance *instance)
  233. {
  234. struct u3phy_banks *u3_banks = &instance->u3_banks;
  235. /* gating PCIe Analog XTAL clock */
  236. setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
  237. XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
  238. /* gating XSQ */
  239. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
  240. P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
  241. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
  242. P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
  243. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
  244. P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
  245. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
  246. P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
  247. P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
  248. P3D_RG_CDR_BIR_LTD1_VAL(0x3));
  249. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
  250. P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
  251. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
  252. P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
  253. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
  254. P3D_RG_RXDET_STB2_SET_P3,
  255. P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
  256. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  257. }
  258. static void pcie_phy_instance_init(struct mtk_tphy *tphy,
  259. struct mtk_phy_instance *instance)
  260. {
  261. struct u3phy_banks *u3_banks = &instance->u3_banks;
  262. if (tphy->version != MTK_TPHY_V1)
  263. return;
  264. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
  265. P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
  266. P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
  267. P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
  268. /* ref clk drive */
  269. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
  270. P3A_RG_CLKDRV_AMP_VAL(0x4));
  271. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
  272. P3A_RG_CLKDRV_OFF_VAL(0x1));
  273. /* SSC delta -5000ppm */
  274. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
  275. P3A_RG_PLL_DELTA1_PE2H,
  276. P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
  277. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
  278. P3A_RG_PLL_DELTA_PE2H,
  279. P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
  280. /* change pll BW 0.6M */
  281. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
  282. P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
  283. P3A_RG_PLL_BR_PE2H_VAL(0x1) |
  284. P3A_RG_PLL_IC_PE2H_VAL(0x1));
  285. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
  286. P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
  287. P3A_RG_PLL_BC_PE2H_VAL(0x3));
  288. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
  289. P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
  290. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
  291. P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
  292. /* Tx Detect Rx Timing: 10us -> 5us */
  293. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
  294. P3D_RG_RXDET_STB2_SET,
  295. P3D_RG_RXDET_STB2_SET_VAL(0x10));
  296. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
  297. P3D_RG_RXDET_STB2_SET_P3,
  298. P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
  299. /* wait for PCIe subsys register to active */
  300. udelay(3000);
  301. }
  302. static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
  303. struct mtk_phy_instance *instance)
  304. {
  305. struct u3phy_banks *bank = &instance->u3_banks;
  306. clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
  307. P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
  308. clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
  309. P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
  310. }
  311. static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
  312. struct mtk_phy_instance *instance)
  313. {
  314. struct u3phy_banks *bank = &instance->u3_banks;
  315. setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
  316. P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
  317. setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
  318. P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
  319. }
  320. static void phy_v1_banks_init(struct mtk_tphy *tphy,
  321. struct mtk_phy_instance *instance)
  322. {
  323. struct u2phy_banks *u2_banks = &instance->u2_banks;
  324. struct u3phy_banks *u3_banks = &instance->u3_banks;
  325. switch (instance->type) {
  326. case PHY_TYPE_USB2:
  327. u2_banks->misc = NULL;
  328. u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
  329. u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
  330. break;
  331. case PHY_TYPE_USB3:
  332. case PHY_TYPE_PCIE:
  333. u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
  334. u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
  335. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
  336. u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
  337. break;
  338. default:
  339. dev_err(tphy->dev, "incompatible PHY type\n");
  340. return;
  341. }
  342. }
  343. static void phy_v2_banks_init(struct mtk_tphy *tphy,
  344. struct mtk_phy_instance *instance)
  345. {
  346. struct u2phy_banks *u2_banks = &instance->u2_banks;
  347. struct u3phy_banks *u3_banks = &instance->u3_banks;
  348. switch (instance->type) {
  349. case PHY_TYPE_USB2:
  350. u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
  351. u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
  352. u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
  353. break;
  354. case PHY_TYPE_USB3:
  355. case PHY_TYPE_PCIE:
  356. u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
  357. u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
  358. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
  359. u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
  360. break;
  361. default:
  362. dev_err(tphy->dev, "incompatible PHY type\n");
  363. return;
  364. }
  365. }
  366. static int mtk_phy_init(struct phy *phy)
  367. {
  368. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  369. struct mtk_phy_instance *instance = tphy->phys[phy->id];
  370. int ret;
  371. ret = clk_enable(&instance->ref_clk);
  372. if (ret < 0) {
  373. dev_err(tphy->dev, "failed to enable ref_clk\n");
  374. return ret;
  375. }
  376. ret = clk_enable(&instance->da_ref_clk);
  377. if (ret < 0) {
  378. dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret);
  379. clk_disable(&instance->ref_clk);
  380. return ret;
  381. }
  382. switch (instance->type) {
  383. case PHY_TYPE_USB2:
  384. u2_phy_instance_init(tphy, instance);
  385. break;
  386. case PHY_TYPE_USB3:
  387. u3_phy_instance_init(tphy, instance);
  388. break;
  389. case PHY_TYPE_PCIE:
  390. pcie_phy_instance_init(tphy, instance);
  391. break;
  392. default:
  393. dev_err(tphy->dev, "incompatible PHY type\n");
  394. return -EINVAL;
  395. }
  396. return 0;
  397. }
  398. static int mtk_phy_power_on(struct phy *phy)
  399. {
  400. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  401. struct mtk_phy_instance *instance = tphy->phys[phy->id];
  402. if (instance->type == PHY_TYPE_USB2)
  403. u2_phy_instance_power_on(tphy, instance);
  404. else if (instance->type == PHY_TYPE_PCIE)
  405. pcie_phy_instance_power_on(tphy, instance);
  406. return 0;
  407. }
  408. static int mtk_phy_power_off(struct phy *phy)
  409. {
  410. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  411. struct mtk_phy_instance *instance = tphy->phys[phy->id];
  412. if (instance->type == PHY_TYPE_USB2)
  413. u2_phy_instance_power_off(tphy, instance);
  414. else if (instance->type == PHY_TYPE_PCIE)
  415. pcie_phy_instance_power_off(tphy, instance);
  416. return 0;
  417. }
  418. static int mtk_phy_exit(struct phy *phy)
  419. {
  420. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  421. struct mtk_phy_instance *instance = tphy->phys[phy->id];
  422. clk_disable(&instance->da_ref_clk);
  423. clk_disable(&instance->ref_clk);
  424. return 0;
  425. }
  426. static int mtk_phy_xlate(struct phy *phy,
  427. struct ofnode_phandle_args *args)
  428. {
  429. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  430. struct mtk_phy_instance *instance = NULL;
  431. const struct device_node *phy_np = ofnode_to_np(args->node);
  432. u32 index;
  433. if (!phy_np) {
  434. dev_err(phy->dev, "null pointer phy node\n");
  435. return -EINVAL;
  436. }
  437. if (args->args_count < 1) {
  438. dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
  439. return -EINVAL;
  440. }
  441. for (index = 0; index < tphy->nphys; index++)
  442. if (phy_np == tphy->phys[index]->np) {
  443. instance = tphy->phys[index];
  444. break;
  445. }
  446. if (!instance) {
  447. dev_err(phy->dev, "failed to find appropriate phy\n");
  448. return -EINVAL;
  449. }
  450. phy->id = index;
  451. instance->type = args->args[1];
  452. if (!(instance->type == PHY_TYPE_USB2 ||
  453. instance->type == PHY_TYPE_USB3 ||
  454. instance->type == PHY_TYPE_PCIE)) {
  455. dev_err(phy->dev, "unsupported device type\n");
  456. return -EINVAL;
  457. }
  458. if (tphy->version == MTK_TPHY_V1) {
  459. phy_v1_banks_init(tphy, instance);
  460. } else if (tphy->version == MTK_TPHY_V2) {
  461. phy_v2_banks_init(tphy, instance);
  462. } else {
  463. dev_err(phy->dev, "phy version is not supported\n");
  464. return -EINVAL;
  465. }
  466. return 0;
  467. }
  468. static const struct phy_ops mtk_tphy_ops = {
  469. .init = mtk_phy_init,
  470. .exit = mtk_phy_exit,
  471. .power_on = mtk_phy_power_on,
  472. .power_off = mtk_phy_power_off,
  473. .of_xlate = mtk_phy_xlate,
  474. };
  475. static int mtk_tphy_probe(struct udevice *dev)
  476. {
  477. struct mtk_tphy *tphy = dev_get_priv(dev);
  478. ofnode subnode;
  479. int index = 0;
  480. tphy->nphys = dev_get_child_count(dev);
  481. tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
  482. GFP_KERNEL);
  483. if (!tphy->phys)
  484. return -ENOMEM;
  485. tphy->dev = dev;
  486. tphy->version = dev_get_driver_data(dev);
  487. /* v1 has shared banks */
  488. if (tphy->version == MTK_TPHY_V1) {
  489. tphy->sif_base = dev_read_addr_ptr(dev);
  490. if (!tphy->sif_base)
  491. return -ENOENT;
  492. }
  493. dev_for_each_subnode(subnode, dev) {
  494. struct mtk_phy_instance *instance;
  495. fdt_addr_t addr;
  496. int err;
  497. instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
  498. if (!instance)
  499. return -ENOMEM;
  500. addr = ofnode_get_addr(subnode);
  501. if (addr == FDT_ADDR_T_NONE)
  502. return -ENOMEM;
  503. instance->port_base = map_sysmem(addr, 0);
  504. instance->index = index;
  505. instance->np = ofnode_to_np(subnode);
  506. tphy->phys[index] = instance;
  507. index++;
  508. err = clk_get_optional_nodev(subnode, "ref",
  509. &instance->ref_clk);
  510. if (err)
  511. return err;
  512. err = clk_get_optional_nodev(subnode, "da_ref",
  513. &instance->da_ref_clk);
  514. if (err)
  515. return err;
  516. }
  517. return 0;
  518. }
  519. static const struct udevice_id mtk_tphy_id_table[] = {
  520. { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
  521. { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
  522. { }
  523. };
  524. U_BOOT_DRIVER(mtk_tphy) = {
  525. .name = "mtk-tphy",
  526. .id = UCLASS_PHY,
  527. .of_match = mtk_tphy_id_table,
  528. .ops = &mtk_tphy_ops,
  529. .probe = mtk_tphy_probe,
  530. .priv_auto_alloc_size = sizeof(struct mtk_tphy),
  531. };