octeon_i2c.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <i2c.h>
  9. #include <pci_ids.h>
  10. #include <asm/io.h>
  11. #include <linux/bitfield.h>
  12. #include <linux/compat.h>
  13. #include <linux/delay.h>
  14. #define TWSI_SW_TWSI 0x00
  15. #define TWSI_TWSI_SW 0x08
  16. #define TWSI_INT 0x10
  17. #define TWSI_SW_TWSI_EXT 0x18
  18. #define TWSI_SW_DATA_MASK GENMASK_ULL(31, 0)
  19. #define TWSI_SW_EOP_IA_MASK GENMASK_ULL(34, 32)
  20. #define TWSI_SW_IA_MASK GENMASK_ULL(39, 35)
  21. #define TWSI_SW_ADDR_MASK GENMASK_ULL(49, 40)
  22. #define TWSI_SW_SCR_MASK GENMASK_ULL(51, 50)
  23. #define TWSI_SW_SIZE_MASK GENMASK_ULL(54, 52)
  24. #define TWSI_SW_SOVR BIT_ULL(55)
  25. #define TWSI_SW_R BIT_ULL(56)
  26. #define TWSI_SW_OP_MASK GENMASK_ULL(60, 57)
  27. #define TWSI_SW_EIA GENMASK_ULL(61)
  28. #define TWSI_SW_SLONLY BIT_ULL(62)
  29. #define TWSI_SW_V BIT_ULL(63)
  30. #define TWSI_INT_SDA_OVR BIT_ULL(8)
  31. #define TWSI_INT_SCL_OVR BIT_ULL(9)
  32. #define TWSI_INT_SDA BIT_ULL(10)
  33. #define TWSI_INT_SCL BIT_ULL(11)
  34. enum {
  35. TWSI_OP_WRITE = 0,
  36. TWSI_OP_READ = 1,
  37. };
  38. enum {
  39. TWSI_EOP_SLAVE_ADDR = 0,
  40. TWSI_EOP_CLK_CTL = 3,
  41. TWSI_SW_EOP_IA = 6,
  42. };
  43. enum {
  44. TWSI_SLAVEADD = 0,
  45. TWSI_DATA = 1,
  46. TWSI_CTL = 2,
  47. TWSI_CLKCTL = 3,
  48. TWSI_STAT = 3,
  49. TWSI_SLAVEADD_EXT = 4,
  50. TWSI_RST = 7,
  51. };
  52. enum {
  53. TWSI_CTL_AAK = BIT(2),
  54. TWSI_CTL_IFLG = BIT(3),
  55. TWSI_CTL_STP = BIT(4),
  56. TWSI_CTL_STA = BIT(5),
  57. TWSI_CTL_ENAB = BIT(6),
  58. TWSI_CTL_CE = BIT(7),
  59. };
  60. /*
  61. * Internal errors. When debugging is enabled, the driver will report the
  62. * error number and the user / developer can check the table below for the
  63. * detailed error description.
  64. */
  65. enum {
  66. /** Bus error */
  67. TWSI_STAT_BUS_ERROR = 0x00,
  68. /** Start condition transmitted */
  69. TWSI_STAT_START = 0x08,
  70. /** Repeat start condition transmitted */
  71. TWSI_STAT_RSTART = 0x10,
  72. /** Address + write bit transmitted, ACK received */
  73. TWSI_STAT_TXADDR_ACK = 0x18,
  74. /** Address + write bit transmitted, /ACK received */
  75. TWSI_STAT_TXADDR_NAK = 0x20,
  76. /** Data byte transmitted in master mode, ACK received */
  77. TWSI_STAT_TXDATA_ACK = 0x28,
  78. /** Data byte transmitted in master mode, ACK received */
  79. TWSI_STAT_TXDATA_NAK = 0x30,
  80. /** Arbitration lost in address or data byte */
  81. TWSI_STAT_TX_ARB_LOST = 0x38,
  82. /** Address + read bit transmitted, ACK received */
  83. TWSI_STAT_RXADDR_ACK = 0x40,
  84. /** Address + read bit transmitted, /ACK received */
  85. TWSI_STAT_RXADDR_NAK = 0x48,
  86. /** Data byte received in master mode, ACK transmitted */
  87. TWSI_STAT_RXDATA_ACK_SENT = 0x50,
  88. /** Data byte received, NACK transmitted */
  89. TWSI_STAT_RXDATA_NAK_SENT = 0x58,
  90. /** Slave address received, sent ACK */
  91. TWSI_STAT_SLAVE_RXADDR_ACK = 0x60,
  92. /**
  93. * Arbitration lost in address as master, slave address + write bit
  94. * received, ACK transmitted
  95. */
  96. TWSI_STAT_TX_ACK_ARB_LOST = 0x68,
  97. /** General call address received, ACK transmitted */
  98. TWSI_STAT_RX_GEN_ADDR_ACK = 0x70,
  99. /**
  100. * Arbitration lost in address as master, general call address
  101. * received, ACK transmitted
  102. */
  103. TWSI_STAT_RX_GEN_ADDR_ARB_LOST = 0x78,
  104. /** Data byte received after slave address received, ACK transmitted */
  105. TWSI_STAT_SLAVE_RXDATA_ACK = 0x80,
  106. /** Data byte received after slave address received, /ACK transmitted */
  107. TWSI_STAT_SLAVE_RXDATA_NAK = 0x88,
  108. /**
  109. * Data byte received after general call address received, ACK
  110. * transmitted
  111. */
  112. TWSI_STAT_GEN_RXADDR_ACK = 0x90,
  113. /**
  114. * Data byte received after general call address received, /ACK
  115. * transmitted
  116. */
  117. TWSI_STAT_GEN_RXADDR_NAK = 0x98,
  118. /** STOP or repeated START condition received in slave mode */
  119. TWSI_STAT_STOP_MULTI_START = 0xa0,
  120. /** Slave address + read bit received, ACK transmitted */
  121. TWSI_STAT_SLAVE_RXADDR2_ACK = 0xa8,
  122. /**
  123. * Arbitration lost in address as master, slave address + read bit
  124. * received, ACK transmitted
  125. */
  126. TWSI_STAT_RXDATA_ACK_ARB_LOST = 0xb0,
  127. /** Data byte transmitted in slave mode, ACK received */
  128. TWSI_STAT_SLAVE_TXDATA_ACK = 0xb8,
  129. /** Data byte transmitted in slave mode, /ACK received */
  130. TWSI_STAT_SLAVE_TXDATA_NAK = 0xc0,
  131. /** Last byte transmitted in slave mode, ACK received */
  132. TWSI_STAT_SLAVE_TXDATA_END_ACK = 0xc8,
  133. /** Second address byte + write bit transmitted, ACK received */
  134. TWSI_STAT_TXADDR2DATA_ACK = 0xd0,
  135. /** Second address byte + write bit transmitted, /ACK received */
  136. TWSI_STAT_TXADDR2DATA_NAK = 0xd8,
  137. /** No relevant status information */
  138. TWSI_STAT_IDLE = 0xf8
  139. };
  140. #define CONFIG_SYS_I2C_OCTEON_SLAVE_ADDR 0x77
  141. enum {
  142. PROBE_PCI = 0, /* PCI based probing */
  143. PROBE_DT, /* DT based probing */
  144. };
  145. enum {
  146. CLK_METHOD_OCTEON = 0,
  147. CLK_METHOD_OCTEONTX2,
  148. };
  149. /**
  150. * struct octeon_i2c_data - SoC specific data of this driver
  151. *
  152. * @probe: Probing of this SoC (DT vs PCI)
  153. * @reg_offs: Register offset
  154. * @thp: THP define for divider calculation
  155. * @clk_method: Clock calculation method
  156. */
  157. struct octeon_i2c_data {
  158. int probe;
  159. u32 reg_offs;
  160. int thp;
  161. int clk_method;
  162. };
  163. /**
  164. * struct octeon_twsi - Private data of this driver
  165. *
  166. * @base: Base address of i2c registers
  167. * @data: Pointer to SoC specific data struct
  168. */
  169. struct octeon_twsi {
  170. void __iomem *base;
  171. const struct octeon_i2c_data *data;
  172. struct clk clk;
  173. };
  174. static void twsi_unblock(void *base);
  175. static int twsi_stop(void *base);
  176. /**
  177. * Returns true if we lost arbitration
  178. *
  179. * @code status code
  180. * @final_read true if this is the final read operation
  181. * @return true if arbitration has been lost, false if it hasn't been lost.
  182. */
  183. static int twsi_i2c_lost_arb(u8 code, int final_read)
  184. {
  185. switch (code) {
  186. case TWSI_STAT_TX_ARB_LOST:
  187. case TWSI_STAT_TX_ACK_ARB_LOST:
  188. case TWSI_STAT_RX_GEN_ADDR_ARB_LOST:
  189. case TWSI_STAT_RXDATA_ACK_ARB_LOST:
  190. /* Arbitration lost */
  191. return -EAGAIN;
  192. case TWSI_STAT_SLAVE_RXADDR_ACK:
  193. case TWSI_STAT_RX_GEN_ADDR_ACK:
  194. case TWSI_STAT_GEN_RXADDR_ACK:
  195. case TWSI_STAT_GEN_RXADDR_NAK:
  196. /* Being addressed as slave, should back off and listen */
  197. return -EIO;
  198. case TWSI_STAT_SLAVE_RXDATA_ACK:
  199. case TWSI_STAT_SLAVE_RXDATA_NAK:
  200. case TWSI_STAT_STOP_MULTI_START:
  201. case TWSI_STAT_SLAVE_RXADDR2_ACK:
  202. case TWSI_STAT_SLAVE_TXDATA_ACK:
  203. case TWSI_STAT_SLAVE_TXDATA_NAK:
  204. case TWSI_STAT_SLAVE_TXDATA_END_ACK:
  205. /* Core busy as slave */
  206. return -EIO;
  207. case TWSI_STAT_RXDATA_ACK_SENT:
  208. /* Ack allowed on pre-terminal bytes only */
  209. if (!final_read)
  210. return 0;
  211. return -EAGAIN;
  212. case TWSI_STAT_RXDATA_NAK_SENT:
  213. /* NAK allowed on terminal byte only */
  214. if (!final_read)
  215. return 0;
  216. return -EAGAIN;
  217. case TWSI_STAT_TXDATA_NAK:
  218. case TWSI_STAT_TXADDR_NAK:
  219. case TWSI_STAT_RXADDR_NAK:
  220. case TWSI_STAT_TXADDR2DATA_NAK:
  221. return -EAGAIN;
  222. }
  223. return 0;
  224. }
  225. /**
  226. * Writes to the MIO_TWS(0..5)_SW_TWSI register
  227. *
  228. * @base Base address of i2c registers
  229. * @val value to write
  230. * @return 0 for success, otherwise error
  231. */
  232. static u64 twsi_write_sw(void __iomem *base, u64 val)
  233. {
  234. unsigned long start = get_timer(0);
  235. val &= ~TWSI_SW_R;
  236. val |= TWSI_SW_V;
  237. debug("%s(%p, 0x%llx)\n", __func__, base, val);
  238. writeq(val, base + TWSI_SW_TWSI);
  239. do {
  240. val = readq(base + TWSI_SW_TWSI);
  241. } while ((val & TWSI_SW_V) && (get_timer(start) < 50));
  242. if (val & TWSI_SW_V)
  243. debug("%s: timed out\n", __func__);
  244. return val;
  245. }
  246. /**
  247. * Reads the MIO_TWS(0..5)_SW_TWSI register
  248. *
  249. * @base Base address of i2c registers
  250. * @val value for eia and op, etc. to read
  251. * @return value of the register
  252. */
  253. static u64 twsi_read_sw(void __iomem *base, u64 val)
  254. {
  255. unsigned long start = get_timer(0);
  256. val |= TWSI_SW_R | TWSI_SW_V;
  257. debug("%s(%p, 0x%llx)\n", __func__, base, val);
  258. writeq(val, base + TWSI_SW_TWSI);
  259. do {
  260. val = readq(base + TWSI_SW_TWSI);
  261. } while ((val & TWSI_SW_V) && (get_timer(start) < 50));
  262. if (val & TWSI_SW_V)
  263. debug("%s: Error writing 0x%llx\n", __func__, val);
  264. debug("%s: Returning 0x%llx\n", __func__, val);
  265. return val;
  266. }
  267. /**
  268. * Write control register
  269. *
  270. * @base Base address for i2c registers
  271. * @data data to write
  272. */
  273. static void twsi_write_ctl(void __iomem *base, u8 data)
  274. {
  275. u64 val;
  276. debug("%s(%p, 0x%x)\n", __func__, base, data);
  277. val = data | FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CTL) |
  278. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  279. twsi_write_sw(base, val);
  280. }
  281. /**
  282. * Reads the TWSI Control Register
  283. *
  284. * @base Base address for i2c
  285. * @return 8-bit TWSI control register
  286. */
  287. static u8 twsi_read_ctl(void __iomem *base)
  288. {
  289. u64 val;
  290. val = FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CTL) |
  291. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  292. val = twsi_read_sw(base, val);
  293. debug("%s(%p): 0x%x\n", __func__, base, (u8)val);
  294. return (u8)val;
  295. }
  296. /**
  297. * Read i2c status register
  298. *
  299. * @base Base address of i2c registers
  300. * @return value of status register
  301. */
  302. static u8 twsi_read_status(void __iomem *base)
  303. {
  304. u64 val;
  305. val = FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_STAT) |
  306. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  307. return twsi_read_sw(base, val);
  308. }
  309. /**
  310. * Waits for an i2c operation to complete
  311. *
  312. * @param base Base address of registers
  313. * @return 0 for success, 1 if timeout
  314. */
  315. static int twsi_wait(void __iomem *base)
  316. {
  317. unsigned long start = get_timer(0);
  318. u8 twsi_ctl;
  319. debug("%s(%p)\n", __func__, base);
  320. do {
  321. twsi_ctl = twsi_read_ctl(base);
  322. twsi_ctl &= TWSI_CTL_IFLG;
  323. } while (!twsi_ctl && get_timer(start) < 50);
  324. debug(" return: %u\n", !twsi_ctl);
  325. return !twsi_ctl;
  326. }
  327. /**
  328. * Unsticks the i2c bus
  329. *
  330. * @base base address of registers
  331. */
  332. static int twsi_start_unstick(void __iomem *base)
  333. {
  334. twsi_stop(base);
  335. twsi_unblock(base);
  336. return 0;
  337. }
  338. /**
  339. * Sends an i2c start condition
  340. *
  341. * @base base address of registers
  342. * @return 0 for success, otherwise error
  343. */
  344. static int twsi_start(void __iomem *base)
  345. {
  346. int ret;
  347. u8 stat;
  348. debug("%s(%p)\n", __func__, base);
  349. twsi_write_ctl(base, TWSI_CTL_STA | TWSI_CTL_ENAB);
  350. ret = twsi_wait(base);
  351. if (ret) {
  352. stat = twsi_read_status(base);
  353. debug("%s: ret: 0x%x, status: 0x%x\n", __func__, ret, stat);
  354. switch (stat) {
  355. case TWSI_STAT_START:
  356. case TWSI_STAT_RSTART:
  357. return 0;
  358. case TWSI_STAT_RXADDR_ACK:
  359. default:
  360. return twsi_start_unstick(base);
  361. }
  362. }
  363. debug("%s: success\n", __func__);
  364. return 0;
  365. }
  366. /**
  367. * Sends an i2c stop condition
  368. *
  369. * @base register base address
  370. * @return 0 for success, -1 if error
  371. */
  372. static int twsi_stop(void __iomem *base)
  373. {
  374. u8 stat;
  375. twsi_write_ctl(base, TWSI_CTL_STP | TWSI_CTL_ENAB);
  376. stat = twsi_read_status(base);
  377. if (stat != TWSI_STAT_IDLE) {
  378. debug("%s: Bad status on bus@%p\n", __func__, base);
  379. return -1;
  380. }
  381. return 0;
  382. }
  383. /**
  384. * Writes data to the i2c bus
  385. *
  386. * @base register base address
  387. * @slave_addr address of slave to write to
  388. * @buffer Pointer to buffer to write
  389. * @length Number of bytes in buffer to write
  390. * @return 0 for success, otherwise error
  391. */
  392. static int twsi_write_data(void __iomem *base, u8 slave_addr,
  393. u8 *buffer, unsigned int length)
  394. {
  395. unsigned int curr = 0;
  396. u64 val;
  397. int ret;
  398. debug("%s(%p, 0x%x, %p, 0x%x)\n", __func__, base, slave_addr,
  399. buffer, length);
  400. ret = twsi_start(base);
  401. if (ret) {
  402. debug("%s: Could not start BUS transaction\n", __func__);
  403. return -1;
  404. }
  405. ret = twsi_wait(base);
  406. if (ret) {
  407. debug("%s: wait failed\n", __func__);
  408. return ret;
  409. }
  410. val = (u32)(slave_addr << 1) | TWSI_OP_WRITE |
  411. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) |
  412. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  413. twsi_write_sw(base, val);
  414. twsi_write_ctl(base, TWSI_CTL_ENAB);
  415. debug("%s: Waiting\n", __func__);
  416. ret = twsi_wait(base);
  417. if (ret) {
  418. debug("%s: Timed out writing slave address 0x%x to target\n",
  419. __func__, slave_addr);
  420. return ret;
  421. }
  422. ret = twsi_read_status(base);
  423. debug("%s: status: 0x%x\n", __func__, ret);
  424. if (ret != TWSI_STAT_TXADDR_ACK) {
  425. debug("%s: status: 0x%x\n", __func__, ret);
  426. twsi_stop(base);
  427. return twsi_i2c_lost_arb(ret, 0);
  428. }
  429. while (curr < length) {
  430. val = buffer[curr++] |
  431. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) |
  432. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  433. twsi_write_sw(base, val);
  434. twsi_write_ctl(base, TWSI_CTL_ENAB);
  435. debug("%s: Writing 0x%llx\n", __func__, val);
  436. ret = twsi_wait(base);
  437. if (ret) {
  438. debug("%s: Timed out writing data to 0x%x\n",
  439. __func__, slave_addr);
  440. return ret;
  441. }
  442. ret = twsi_read_status(base);
  443. debug("%s: status: 0x%x\n", __func__, ret);
  444. }
  445. debug("%s: Stopping\n", __func__);
  446. return twsi_stop(base);
  447. }
  448. /**
  449. * Manually clear the I2C bus and send a stop
  450. *
  451. * @base register base address
  452. */
  453. static void twsi_unblock(void __iomem *base)
  454. {
  455. int i;
  456. for (i = 0; i < 9; i++) {
  457. writeq(0, base + TWSI_INT);
  458. udelay(5);
  459. writeq(TWSI_INT_SCL_OVR, base + TWSI_INT);
  460. udelay(5);
  461. }
  462. writeq(TWSI_INT_SCL_OVR | TWSI_INT_SDA_OVR, base + TWSI_INT);
  463. udelay(5);
  464. writeq(TWSI_INT_SDA_OVR, base + TWSI_INT);
  465. udelay(5);
  466. writeq(0, base + TWSI_INT);
  467. udelay(5);
  468. }
  469. /**
  470. * Performs a read transaction on the i2c bus
  471. *
  472. * @base Base address of twsi registers
  473. * @slave_addr i2c bus address to read from
  474. * @buffer buffer to read into
  475. * @length number of bytes to read
  476. * @return 0 for success, otherwise error
  477. */
  478. static int twsi_read_data(void __iomem *base, u8 slave_addr,
  479. u8 *buffer, unsigned int length)
  480. {
  481. unsigned int curr = 0;
  482. u64 val;
  483. int ret;
  484. debug("%s(%p, 0x%x, %p, %u)\n", __func__, base, slave_addr,
  485. buffer, length);
  486. ret = twsi_start(base);
  487. if (ret) {
  488. debug("%s: start failed\n", __func__);
  489. return ret;
  490. }
  491. ret = twsi_wait(base);
  492. if (ret) {
  493. debug("%s: wait failed\n", __func__);
  494. return ret;
  495. }
  496. val = (u32)(slave_addr << 1) | TWSI_OP_READ |
  497. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) |
  498. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  499. twsi_write_sw(base, val);
  500. twsi_write_ctl(base, TWSI_CTL_ENAB);
  501. ret = twsi_wait(base);
  502. if (ret) {
  503. debug("%s: waiting for sending addr failed\n", __func__);
  504. return ret;
  505. }
  506. ret = twsi_read_status(base);
  507. debug("%s: status: 0x%x\n", __func__, ret);
  508. if (ret != TWSI_STAT_RXADDR_ACK) {
  509. debug("%s: status: 0x%x\n", __func__, ret);
  510. twsi_stop(base);
  511. return twsi_i2c_lost_arb(ret, 0);
  512. }
  513. while (curr < length) {
  514. twsi_write_ctl(base, TWSI_CTL_ENAB |
  515. ((curr < length - 1) ? TWSI_CTL_AAK : 0));
  516. ret = twsi_wait(base);
  517. if (ret) {
  518. debug("%s: waiting for data failed\n", __func__);
  519. return ret;
  520. }
  521. val = twsi_read_sw(base, val);
  522. buffer[curr++] = (u8)val;
  523. }
  524. twsi_stop(base);
  525. return 0;
  526. }
  527. /**
  528. * Calculate the divisor values
  529. *
  530. * @speed Speed to set
  531. * @m_div Pointer to M divisor
  532. * @n_div Pointer to N divisor
  533. * @return 0 for success, otherwise error
  534. */
  535. static void twsi_calc_div(struct udevice *bus, ulong sclk, unsigned int speed,
  536. int *m_div, int *n_div)
  537. {
  538. struct octeon_twsi *twsi = dev_get_priv(bus);
  539. int thp = twsi->data->thp;
  540. int tclk, fsamp;
  541. int ndiv, mdiv;
  542. if (twsi->data->clk_method == CLK_METHOD_OCTEON) {
  543. tclk = sclk / (2 * (thp + 1));
  544. } else {
  545. /* Refclk src in mode register defaults to 100MHz clock */
  546. sclk = 100000000; /* 100 Mhz */
  547. tclk = sclk / (thp + 2);
  548. }
  549. debug("%s( io_clock %lu tclk %u)\n", __func__, sclk, tclk);
  550. /*
  551. * Compute the clocks M divider:
  552. *
  553. * TWSI freq = (core freq) / (10 x (M+1) x 2 * (thp+1) x 2^N)
  554. * M = ((core freq) / (10 x (TWSI freq) x 2 * (thp+1) x 2^N)) - 1
  555. *
  556. * For OcteonTX2 -
  557. * TWSI freq = (core freq) / (10 x (M+1) x (thp+2) x 2^N)
  558. * M = ((core freq) / (10 x (TWSI freq) x (thp+2) x 2^N)) - 1
  559. */
  560. for (ndiv = 0; ndiv < 8; ndiv++) {
  561. fsamp = tclk / (1 << ndiv);
  562. mdiv = fsamp / speed / 10;
  563. mdiv -= 1;
  564. if (mdiv < 16)
  565. break;
  566. }
  567. *m_div = mdiv;
  568. *n_div = ndiv;
  569. }
  570. /**
  571. * Init I2C controller
  572. *
  573. * @base Base address of twsi registers
  574. * @slave_addr I2C slave address to configure this controller to
  575. * @return 0 for success, otherwise error
  576. */
  577. static int twsi_init(void __iomem *base, int slaveaddr)
  578. {
  579. u64 val;
  580. debug("%s (%p, 0x%x)\n", __func__, base, slaveaddr);
  581. val = slaveaddr << 1 |
  582. FIELD_PREP(TWSI_SW_EOP_IA_MASK, 0) |
  583. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) |
  584. TWSI_SW_V;
  585. twsi_write_sw(base, val);
  586. /* Set slave address */
  587. val = slaveaddr |
  588. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_EOP_SLAVE_ADDR) |
  589. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) |
  590. TWSI_SW_V;
  591. twsi_write_sw(base, val);
  592. return 0;
  593. }
  594. /**
  595. * Transfers data over the i2c bus
  596. *
  597. * @bus i2c bus to transfer data over
  598. * @msg Array of i2c messages
  599. * @nmsgs Number of messages to send/receive
  600. * @return 0 for success, otherwise error
  601. */
  602. static int octeon_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  603. int nmsgs)
  604. {
  605. struct octeon_twsi *twsi = dev_get_priv(bus);
  606. int ret;
  607. int i;
  608. debug("%s: %d messages\n", __func__, nmsgs);
  609. for (i = 0; i < nmsgs; i++, msg++) {
  610. debug("%s: chip=0x%x, len=0x%x\n", __func__, msg->addr,
  611. msg->len);
  612. if (msg->flags & I2C_M_RD) {
  613. debug("%s: Reading data\n", __func__);
  614. ret = twsi_read_data(twsi->base, msg->addr,
  615. msg->buf, msg->len);
  616. } else {
  617. debug("%s: Writing data\n", __func__);
  618. ret = twsi_write_data(twsi->base, msg->addr,
  619. msg->buf, msg->len);
  620. }
  621. if (ret) {
  622. debug("%s: error sending\n", __func__);
  623. return -EREMOTEIO;
  624. }
  625. }
  626. return 0;
  627. }
  628. /**
  629. * Set I2C bus speed
  630. *
  631. * @bus i2c bus to transfer data over
  632. * @speed Speed in Hz to set
  633. * @return 0 for success, otherwise error
  634. */
  635. static int octeon_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  636. {
  637. struct octeon_twsi *twsi = dev_get_priv(bus);
  638. int m_div, n_div;
  639. ulong clk_rate;
  640. u64 val;
  641. debug("%s(%p, %u)\n", __func__, bus, speed);
  642. clk_rate = clk_get_rate(&twsi->clk);
  643. if (IS_ERR_VALUE(clk_rate))
  644. return -EINVAL;
  645. twsi_calc_div(bus, clk_rate, speed, &m_div, &n_div);
  646. if (m_div >= 16)
  647. return -1;
  648. val = (u32)(((m_div & 0xf) << 3) | ((n_div & 0x7) << 0)) |
  649. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CLKCTL) |
  650. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) |
  651. TWSI_SW_V;
  652. /* Only init non-slave ports */
  653. writeq(val, twsi->base + TWSI_SW_TWSI);
  654. debug("%s: Wrote 0x%llx to sw_twsi\n", __func__, val);
  655. return 0;
  656. }
  657. /**
  658. * Driver probe function
  659. *
  660. * @dev I2C device to probe
  661. * @return 0 for success, otherwise error
  662. */
  663. static int octeon_i2c_probe(struct udevice *dev)
  664. {
  665. struct octeon_twsi *twsi = dev_get_priv(dev);
  666. u32 i2c_slave_addr;
  667. int ret;
  668. twsi->data = (const struct octeon_i2c_data *)dev_get_driver_data(dev);
  669. if (twsi->data->probe == PROBE_PCI) {
  670. pci_dev_t bdf = dm_pci_get_bdf(dev);
  671. debug("TWSI PCI device: %x\n", bdf);
  672. dev->req_seq = PCI_FUNC(bdf);
  673. twsi->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
  674. PCI_REGION_MEM);
  675. } else {
  676. twsi->base = dev_remap_addr(dev);
  677. }
  678. twsi->base += twsi->data->reg_offs;
  679. i2c_slave_addr = dev_read_u32_default(dev, "i2c-sda-hold-time-ns",
  680. CONFIG_SYS_I2C_OCTEON_SLAVE_ADDR);
  681. ret = clk_get_by_index(dev, 0, &twsi->clk);
  682. if (ret < 0)
  683. return ret;
  684. ret = clk_enable(&twsi->clk);
  685. if (ret)
  686. return ret;
  687. debug("TWSI bus %d at %p\n", dev->seq, twsi->base);
  688. /* Start with standard speed, real speed set via DT or cmd */
  689. return twsi_init(twsi->base, i2c_slave_addr);
  690. }
  691. static const struct dm_i2c_ops octeon_i2c_ops = {
  692. .xfer = octeon_i2c_xfer,
  693. .set_bus_speed = octeon_i2c_set_bus_speed,
  694. };
  695. static const struct octeon_i2c_data i2c_octeon_data = {
  696. .probe = PROBE_DT,
  697. .reg_offs = 0x0000,
  698. .thp = 3,
  699. .clk_method = CLK_METHOD_OCTEON,
  700. };
  701. static const struct octeon_i2c_data i2c_octeontx_data = {
  702. .probe = PROBE_PCI,
  703. .reg_offs = 0x8000,
  704. .thp = 3,
  705. .clk_method = CLK_METHOD_OCTEON,
  706. };
  707. static const struct octeon_i2c_data i2c_octeontx2_data = {
  708. .probe = PROBE_PCI,
  709. .reg_offs = 0x8000,
  710. .thp = 24,
  711. .clk_method = CLK_METHOD_OCTEONTX2,
  712. };
  713. static const struct udevice_id octeon_i2c_ids[] = {
  714. { .compatible = "cavium,octeon-7890-twsi",
  715. .data = (ulong)&i2c_octeon_data },
  716. { .compatible = "cavium,thunder-8890-twsi",
  717. .data = (ulong)&i2c_octeontx_data },
  718. { .compatible = "cavium,thunder2-99xx-twsi",
  719. .data = (ulong)&i2c_octeontx2_data },
  720. { }
  721. };
  722. U_BOOT_DRIVER(octeon_pci_twsi) = {
  723. .name = "i2c_octeon",
  724. .id = UCLASS_I2C,
  725. .of_match = octeon_i2c_ids,
  726. .probe = octeon_i2c_probe,
  727. .priv_auto_alloc_size = sizeof(struct octeon_twsi),
  728. .ops = &octeon_i2c_ops,
  729. };
  730. static struct pci_device_id octeon_twsi_supported[] = {
  731. { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_TWSI),
  732. .driver_data = (ulong)&i2c_octeontx2_data },
  733. { },
  734. };
  735. U_BOOT_PCI_DEVICE(octeon_pci_twsi, octeon_twsi_supported);