versalpl.c 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2019, Xilinx, Inc,
  4. * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <log.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <memalign.h>
  11. #include <versalpl.h>
  12. #include <zynqmp_firmware.h>
  13. #include <asm/cache.h>
  14. static ulong versal_align_dma_buffer(ulong *buf, u32 len)
  15. {
  16. ulong *new_buf;
  17. if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  18. new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  19. memcpy(new_buf, buf, len);
  20. buf = new_buf;
  21. }
  22. return (ulong)buf;
  23. }
  24. static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
  25. bitstream_type bstype)
  26. {
  27. ulong bin_buf;
  28. int ret;
  29. u32 buf_lo, buf_hi;
  30. u32 ret_payload[5];
  31. bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
  32. debug("%s called!\n", __func__);
  33. flush_dcache_range(bin_buf, bin_buf + bsize);
  34. buf_lo = lower_32_bits(bin_buf);
  35. buf_hi = upper_32_bits(bin_buf);
  36. ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
  37. buf_hi, 0, ret_payload);
  38. if (ret)
  39. printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
  40. return ret;
  41. }
  42. struct xilinx_fpga_op versal_op = {
  43. .load = versal_load,
  44. };