ti_sci.h 55 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Texas Instruments System Control Interface (TISCI) Protocol
  4. *
  5. * Communication protocol with TI SCI hardware
  6. * The system works in a message response protocol
  7. * See: http://processors.wiki.ti.com/index.php/TISCI for details
  8. *
  9. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  10. * Based on drivers/firmware/ti_sci.h from Linux.
  11. *
  12. */
  13. #ifndef __TI_SCI_H
  14. #define __TI_SCI_H
  15. /* Generic Messages */
  16. #include <linux/bitops.h>
  17. #define TI_SCI_MSG_ENABLE_WDT 0x0000
  18. #define TI_SCI_MSG_WAKE_RESET 0x0001
  19. #define TI_SCI_MSG_VERSION 0x0002
  20. #define TI_SCI_MSG_WAKE_REASON 0x0003
  21. #define TI_SCI_MSG_GOODBYE 0x0004
  22. #define TI_SCI_MSG_SYS_RESET 0x0005
  23. #define TI_SCI_MSG_BOARD_CONFIG 0x000b
  24. #define TI_SCI_MSG_BOARD_CONFIG_RM 0x000c
  25. #define TI_SCI_MSG_BOARD_CONFIG_SECURITY 0x000d
  26. #define TI_SCI_MSG_BOARD_CONFIG_PM 0x000e
  27. #define TISCI_MSG_QUERY_MSMC 0x0020
  28. /* Device requests */
  29. #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
  30. #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
  31. #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
  32. /* Clock requests */
  33. #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
  34. #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
  35. #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
  36. #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
  37. #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
  38. #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
  39. #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
  40. #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
  41. /* Processor Control Messages */
  42. #define TISCI_MSG_PROC_REQUEST 0xc000
  43. #define TISCI_MSG_PROC_RELEASE 0xc001
  44. #define TISCI_MSG_PROC_HANDOVER 0xc005
  45. #define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
  46. #define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
  47. #define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
  48. #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
  49. #define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
  50. /* Resource Management Requests */
  51. #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
  52. /* NAVSS resource management */
  53. /* Ringacc requests */
  54. #define TI_SCI_MSG_RM_RING_CFG 0x1110
  55. /* PSI-L requests */
  56. #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
  57. #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
  58. #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
  59. #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
  60. #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
  61. #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
  62. #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
  63. #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
  64. #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
  65. #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
  66. #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
  67. #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
  68. #define TISCI_MSG_FWL_SET 0x9000
  69. #define TISCI_MSG_FWL_GET 0x9001
  70. #define TISCI_MSG_FWL_CHANGE_OWNER 0x9002
  71. /**
  72. * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
  73. * @type: Type of messages: One of TI_SCI_MSG* values
  74. * @host: Host of the message
  75. * @seq: Message identifier indicating a transfer sequence
  76. * @flags: Flag for the message
  77. */
  78. struct ti_sci_msg_hdr {
  79. u16 type;
  80. u8 host;
  81. u8 seq;
  82. #define TI_SCI_MSG_FLAG(val) (1 << (val))
  83. #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
  84. #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
  85. #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
  86. #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
  87. #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
  88. /* Additional Flags */
  89. u32 flags;
  90. } __packed;
  91. /**
  92. * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
  93. * via secure transport.
  94. * @checksum: crc16 checksum for the entire message
  95. * @reserved: Reserved for future use.
  96. */
  97. struct ti_sci_secure_msg_hdr {
  98. u16 checksum;
  99. u16 reserved;
  100. } __packed;
  101. /**
  102. * struct ti_sci_msg_resp_version - Response for a message
  103. * @hdr: Generic header
  104. * @firmware_description: String describing the firmware
  105. * @firmware_revision: Firmware revision
  106. * @abi_major: Major version of the ABI that firmware supports
  107. * @abi_minor: Minor version of the ABI that firmware supports
  108. *
  109. * In general, ABI version changes follow the rule that minor version increments
  110. * are backward compatible. Major revision changes in ABI may not be
  111. * backward compatible.
  112. *
  113. * Response to a generic message with message type TI_SCI_MSG_VERSION
  114. */
  115. struct ti_sci_msg_resp_version {
  116. struct ti_sci_msg_hdr hdr;
  117. char firmware_description[32];
  118. u16 firmware_revision;
  119. u8 abi_major;
  120. u8 abi_minor;
  121. } __packed;
  122. /**
  123. * struct ti_sci_msg_req_reboot - Reboot the SoC
  124. * @hdr: Generic Header
  125. *
  126. * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
  127. * ACK/NACK message.
  128. */
  129. struct ti_sci_msg_req_reboot {
  130. struct ti_sci_msg_hdr hdr;
  131. } __packed;
  132. /**
  133. * struct ti_sci_msg_board_config - Board configuration message
  134. * @hdr: Generic Header
  135. * @boardcfgp_low: Lower 32 bit of the pointer pointing to the board
  136. * configuration data
  137. * @boardcfgp_high: Upper 32 bit of the pointer pointing to the board
  138. * configuration data
  139. * @boardcfg_size: Size of board configuration data object
  140. * Request type is TI_SCI_MSG_BOARD_CONFIG, responded with a generic
  141. * ACK/NACK message.
  142. */
  143. struct ti_sci_msg_board_config {
  144. struct ti_sci_msg_hdr hdr;
  145. u32 boardcfgp_low;
  146. u32 boardcfgp_high;
  147. u16 boardcfg_size;
  148. } __packed;
  149. /**
  150. * struct ti_sci_msg_resp_query_msmc - Query msmc message response structure
  151. * @hdr: Generic Header
  152. * @msmc_start_low: Lower 32 bit of msmc start
  153. * @msmc_start_high: Upper 32 bit of msmc start
  154. * @msmc_end_low: Lower 32 bit of msmc end
  155. * @msmc_end_high: Upper 32 bit of msmc end
  156. *
  157. * Response to a generic message with message type TISCI_MSG_QUERY_MSMC
  158. */
  159. struct ti_sci_msg_resp_query_msmc {
  160. struct ti_sci_msg_hdr hdr;
  161. u32 msmc_start_low;
  162. u32 msmc_start_high;
  163. u32 msmc_end_low;
  164. u32 msmc_end_high;
  165. } __packed;
  166. /**
  167. * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
  168. * @hdr: Generic header
  169. * @id: Indicates which device to modify
  170. * @reserved: Reserved space in message, must be 0 for backward compatibility
  171. * @state: The desired state of the device.
  172. *
  173. * Certain flags can also be set to alter the device state:
  174. * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
  175. * The meaning of this flag will vary slightly from device to device and from
  176. * SoC to SoC but it generally allows the device to wake the SoC out of deep
  177. * suspend states.
  178. * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
  179. * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
  180. * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
  181. * If another host already has this device set to STATE_RETENTION or STATE_ON,
  182. * the message will fail. Once successful, other hosts attempting to set
  183. * STATE_RETENTION or STATE_ON will fail.
  184. *
  185. * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
  186. * ACK/NACK message.
  187. */
  188. struct ti_sci_msg_req_set_device_state {
  189. /* Additional hdr->flags options */
  190. #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
  191. #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
  192. #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
  193. struct ti_sci_msg_hdr hdr;
  194. u32 id;
  195. u32 reserved;
  196. #define MSG_DEVICE_SW_STATE_AUTO_OFF 0
  197. #define MSG_DEVICE_SW_STATE_RETENTION 1
  198. #define MSG_DEVICE_SW_STATE_ON 2
  199. u8 state;
  200. } __packed;
  201. /**
  202. * struct ti_sci_msg_req_get_device_state - Request to get device.
  203. * @hdr: Generic header
  204. * @id: Device Identifier
  205. *
  206. * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
  207. * information
  208. */
  209. struct ti_sci_msg_req_get_device_state {
  210. struct ti_sci_msg_hdr hdr;
  211. u32 id;
  212. } __packed;
  213. /**
  214. * struct ti_sci_msg_resp_get_device_state - Response to get device request.
  215. * @hdr: Generic header
  216. * @context_loss_count: Indicates how many times the device has lost context. A
  217. * driver can use this monotonic counter to determine if the device has
  218. * lost context since the last time this message was exchanged.
  219. * @resets: Programmed state of the reset lines.
  220. * @programmed_state: The state as programmed by set_device.
  221. * - Uses the MSG_DEVICE_SW_* macros
  222. * @current_state: The actual state of the hardware.
  223. *
  224. * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
  225. */
  226. struct ti_sci_msg_resp_get_device_state {
  227. struct ti_sci_msg_hdr hdr;
  228. u32 context_loss_count;
  229. u32 resets;
  230. u8 programmed_state;
  231. #define MSG_DEVICE_HW_STATE_OFF 0
  232. #define MSG_DEVICE_HW_STATE_ON 1
  233. #define MSG_DEVICE_HW_STATE_TRANS 2
  234. u8 current_state;
  235. } __packed;
  236. /**
  237. * struct ti_sci_msg_req_set_device_resets - Set the desired resets
  238. * configuration of the device
  239. * @hdr: Generic header
  240. * @id: Indicates which device to modify
  241. * @resets: A bit field of resets for the device. The meaning, behavior,
  242. * and usage of the reset flags are device specific. 0 for a bit
  243. * indicates releasing the reset represented by that bit while 1
  244. * indicates keeping it held.
  245. *
  246. * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
  247. * ACK/NACK message.
  248. */
  249. struct ti_sci_msg_req_set_device_resets {
  250. struct ti_sci_msg_hdr hdr;
  251. u32 id;
  252. u32 resets;
  253. } __packed;
  254. /**
  255. * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
  256. * @hdr: Generic Header, Certain flags can be set specific to the clocks:
  257. * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
  258. * via spread spectrum clocking.
  259. * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
  260. * frequency to be changed while it is running so long as it
  261. * is within the min/max limits.
  262. * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
  263. * is only applicable to clock inputs on the SoC pseudo-device.
  264. * @dev_id: Device identifier this request is for
  265. * @clk_id: Clock identifier for the device for this request.
  266. * Each device has it's own set of clock inputs. This indexes
  267. * which clock input to modify.
  268. * @request_state: Request the state for the clock to be set to.
  269. * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
  270. * it can be disabled, regardless of the state of the device
  271. * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
  272. * automatically manage the state of this clock. If the device
  273. * is enabled, then the clock is enabled. If the device is set
  274. * to off or retention, then the clock is internally set as not
  275. * being required by the device.(default)
  276. * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
  277. * regardless of the state of the device.
  278. *
  279. * Normally, all required clocks are managed by TISCI entity, this is used
  280. * only for specific control *IF* required. Auto managed state is
  281. * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
  282. * will explicitly control.
  283. *
  284. * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
  285. * ACK or NACK message.
  286. */
  287. struct ti_sci_msg_req_set_clock_state {
  288. /* Additional hdr->flags options */
  289. #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
  290. #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
  291. #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
  292. struct ti_sci_msg_hdr hdr;
  293. u32 dev_id;
  294. u8 clk_id;
  295. #define MSG_CLOCK_SW_STATE_UNREQ 0
  296. #define MSG_CLOCK_SW_STATE_AUTO 1
  297. #define MSG_CLOCK_SW_STATE_REQ 2
  298. u8 request_state;
  299. } __packed;
  300. /**
  301. * struct ti_sci_msg_req_get_clock_state - Request for clock state
  302. * @hdr: Generic Header
  303. * @dev_id: Device identifier this request is for
  304. * @clk_id: Clock identifier for the device for this request.
  305. * Each device has it's own set of clock inputs. This indexes
  306. * which clock input to get state of.
  307. *
  308. * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
  309. * of the clock
  310. */
  311. struct ti_sci_msg_req_get_clock_state {
  312. struct ti_sci_msg_hdr hdr;
  313. u32 dev_id;
  314. u8 clk_id;
  315. } __packed;
  316. /**
  317. * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
  318. * @hdr: Generic Header
  319. * @programmed_state: Any programmed state of the clock. This is one of
  320. * MSG_CLOCK_SW_STATE* values.
  321. * @current_state: Current state of the clock. This is one of:
  322. * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
  323. * MSG_CLOCK_HW_STATE_READY: Clock is ready
  324. *
  325. * Response to TI_SCI_MSG_GET_CLOCK_STATE.
  326. */
  327. struct ti_sci_msg_resp_get_clock_state {
  328. struct ti_sci_msg_hdr hdr;
  329. u8 programmed_state;
  330. #define MSG_CLOCK_HW_STATE_NOT_READY 0
  331. #define MSG_CLOCK_HW_STATE_READY 1
  332. u8 current_state;
  333. } __packed;
  334. /**
  335. * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
  336. * @hdr: Generic Header
  337. * @dev_id: Device identifier this request is for
  338. * @clk_id: Clock identifier for the device for this request.
  339. * Each device has it's own set of clock inputs. This indexes
  340. * which clock input to modify.
  341. * @parent_id: The new clock parent is selectable by an index via this
  342. * parameter.
  343. *
  344. * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
  345. * ACK / NACK message.
  346. */
  347. struct ti_sci_msg_req_set_clock_parent {
  348. struct ti_sci_msg_hdr hdr;
  349. u32 dev_id;
  350. u8 clk_id;
  351. u8 parent_id;
  352. } __packed;
  353. /**
  354. * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
  355. * @hdr: Generic Header
  356. * @dev_id: Device identifier this request is for
  357. * @clk_id: Clock identifier for the device for this request.
  358. * Each device has it's own set of clock inputs. This indexes
  359. * which clock input to get the parent for.
  360. *
  361. * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
  362. */
  363. struct ti_sci_msg_req_get_clock_parent {
  364. struct ti_sci_msg_hdr hdr;
  365. u32 dev_id;
  366. u8 clk_id;
  367. } __packed;
  368. /**
  369. * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
  370. * @hdr: Generic Header
  371. * @parent_id: The current clock parent
  372. *
  373. * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
  374. */
  375. struct ti_sci_msg_resp_get_clock_parent {
  376. struct ti_sci_msg_hdr hdr;
  377. u8 parent_id;
  378. } __packed;
  379. /**
  380. * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
  381. * @hdr: Generic header
  382. * @dev_id: Device identifier this request is for
  383. * @clk_id: Clock identifier for the device for this request.
  384. *
  385. * This request provides information about how many clock parent options
  386. * are available for a given clock to a device. This is typically used
  387. * for input clocks.
  388. *
  389. * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
  390. * message, or NACK in case of inability to satisfy request.
  391. */
  392. struct ti_sci_msg_req_get_clock_num_parents {
  393. struct ti_sci_msg_hdr hdr;
  394. u32 dev_id;
  395. u8 clk_id;
  396. } __packed;
  397. /**
  398. * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
  399. * @hdr: Generic header
  400. * @num_parents: Number of clock parents
  401. *
  402. * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
  403. */
  404. struct ti_sci_msg_resp_get_clock_num_parents {
  405. struct ti_sci_msg_hdr hdr;
  406. u8 num_parents;
  407. } __packed;
  408. /**
  409. * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
  410. * @hdr: Generic Header
  411. * @dev_id: Device identifier this request is for
  412. * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
  413. * allowable programmed frequency and does not account for clock
  414. * tolerances and jitter.
  415. * @target_freq_hz: The target clock frequency. A frequency will be found
  416. * as close to this target frequency as possible.
  417. * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
  418. * allowable programmed frequency and does not account for clock
  419. * tolerances and jitter.
  420. * @clk_id: Clock identifier for the device for this request.
  421. *
  422. * NOTE: Normally clock frequency management is automatically done by TISCI
  423. * entity. In case of specific requests, TISCI evaluates capability to achieve
  424. * requested frequency within provided range and responds with
  425. * result message.
  426. *
  427. * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
  428. * or NACK in case of inability to satisfy request.
  429. */
  430. struct ti_sci_msg_req_query_clock_freq {
  431. struct ti_sci_msg_hdr hdr;
  432. u32 dev_id;
  433. u64 min_freq_hz;
  434. u64 target_freq_hz;
  435. u64 max_freq_hz;
  436. u8 clk_id;
  437. } __packed;
  438. /**
  439. * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
  440. * @hdr: Generic Header
  441. * @freq_hz: Frequency that is the best match in Hz.
  442. *
  443. * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
  444. * cannot be satisfied, the message will be of type NACK.
  445. */
  446. struct ti_sci_msg_resp_query_clock_freq {
  447. struct ti_sci_msg_hdr hdr;
  448. u64 freq_hz;
  449. } __packed;
  450. /**
  451. * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
  452. * @hdr: Generic Header
  453. * @dev_id: Device identifier this request is for
  454. * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
  455. * allowable programmed frequency and does not account for clock
  456. * tolerances and jitter.
  457. * @target_freq_hz: The target clock frequency. The clock will be programmed
  458. * at a rate as close to this target frequency as possible.
  459. * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
  460. * allowable programmed frequency and does not account for clock
  461. * tolerances and jitter.
  462. * @clk_id: Clock identifier for the device for this request.
  463. *
  464. * NOTE: Normally clock frequency management is automatically done by TISCI
  465. * entity. In case of specific requests, TISCI evaluates capability to achieve
  466. * requested range and responds with success/failure message.
  467. *
  468. * This sets the desired frequency for a clock within an allowable
  469. * range. This message will fail on an enabled clock unless
  470. * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
  471. * if other clocks have their frequency modified due to this message,
  472. * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
  473. *
  474. * Calling set frequency on a clock input to the SoC pseudo-device will
  475. * inform the PMMC of that clock's frequency. Setting a frequency of
  476. * zero will indicate the clock is disabled.
  477. *
  478. * Calling set frequency on clock outputs from the SoC pseudo-device will
  479. * function similarly to setting the clock frequency on a device.
  480. *
  481. * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
  482. * message.
  483. */
  484. struct ti_sci_msg_req_set_clock_freq {
  485. struct ti_sci_msg_hdr hdr;
  486. u32 dev_id;
  487. u64 min_freq_hz;
  488. u64 target_freq_hz;
  489. u64 max_freq_hz;
  490. u8 clk_id;
  491. } __packed;
  492. /**
  493. * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
  494. * @hdr: Generic Header
  495. * @dev_id: Device identifier this request is for
  496. * @clk_id: Clock identifier for the device for this request.
  497. *
  498. * NOTE: Normally clock frequency management is automatically done by TISCI
  499. * entity. In some cases, clock frequencies are configured by host.
  500. *
  501. * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
  502. * that the clock is currently at.
  503. */
  504. struct ti_sci_msg_req_get_clock_freq {
  505. struct ti_sci_msg_hdr hdr;
  506. u32 dev_id;
  507. u8 clk_id;
  508. } __packed;
  509. /**
  510. * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
  511. * @hdr: Generic Header
  512. * @freq_hz: Frequency that the clock is currently on, in Hz.
  513. *
  514. * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
  515. */
  516. struct ti_sci_msg_resp_get_clock_freq {
  517. struct ti_sci_msg_hdr hdr;
  518. u64 freq_hz;
  519. } __packed;
  520. #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
  521. /**
  522. * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
  523. * range of resources.
  524. * @hdr: Generic Header
  525. * @type: Unique resource assignment type
  526. * @subtype: Resource assignment subtype within the resource type.
  527. * @secondary_host: Host processing entity to which the resources are
  528. * allocated. This is required only when the destination
  529. * host id id different from ti sci interface host id,
  530. * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
  531. *
  532. * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
  533. * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
  534. */
  535. struct ti_sci_msg_req_get_resource_range {
  536. struct ti_sci_msg_hdr hdr;
  537. #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
  538. #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
  539. u16 type;
  540. u8 subtype;
  541. u8 secondary_host;
  542. } __packed;
  543. /**
  544. * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
  545. * @hdr: Generic Header
  546. * @range_start: Start index of the resource range.
  547. * @range_num: Number of resources in the range.
  548. *
  549. * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
  550. */
  551. struct ti_sci_msg_resp_get_resource_range {
  552. struct ti_sci_msg_hdr hdr;
  553. u16 range_start;
  554. u16 range_num;
  555. } __packed;
  556. #define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
  557. #define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
  558. #define TISCI_ADDR_HIGH_SHIFT 32
  559. /**
  560. * struct ti_sci_msg_req_proc_request - Request a processor
  561. *
  562. * @hdr: Generic Header
  563. * @processor_id: ID of processor
  564. *
  565. * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
  566. * message.
  567. */
  568. struct ti_sci_msg_req_proc_request {
  569. struct ti_sci_msg_hdr hdr;
  570. u8 processor_id;
  571. } __packed;
  572. /**
  573. * struct ti_sci_msg_req_proc_release - Release a processor
  574. *
  575. * @hdr: Generic Header
  576. * @processor_id: ID of processor
  577. *
  578. * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
  579. * message.
  580. */
  581. struct ti_sci_msg_req_proc_release {
  582. struct ti_sci_msg_hdr hdr;
  583. u8 processor_id;
  584. } __packed;
  585. /**
  586. * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
  587. *
  588. * @hdr: Generic Header
  589. * @processor_id: ID of processor
  590. * @host_id: New Host we want to give control to
  591. *
  592. * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
  593. * message.
  594. */
  595. struct ti_sci_msg_req_proc_handover {
  596. struct ti_sci_msg_hdr hdr;
  597. u8 processor_id;
  598. u8 host_id;
  599. } __packed;
  600. /* A53 Config Flags */
  601. #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001
  602. #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002
  603. #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004
  604. #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008
  605. #define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100
  606. /* R5 Config Flags */
  607. #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
  608. #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
  609. #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
  610. #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
  611. #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
  612. #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
  613. #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
  614. #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
  615. /**
  616. * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
  617. * @hdr: Generic Header
  618. * @processor_id: ID of processor
  619. * @bootvector_low: Lower 32bit (Little Endian) of boot vector
  620. * @bootvector_high: Higher 32bit (Little Endian) of boot vector
  621. * @config_flags_set: Optional Processor specific Config Flags to set.
  622. * Setting a bit here implies required bit sets to 1.
  623. * @config_flags_clear: Optional Processor specific Config Flags to clear.
  624. * Setting a bit here implies required bit gets cleared.
  625. *
  626. * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
  627. * ACK/NACK message.
  628. */
  629. struct ti_sci_msg_req_set_proc_boot_config {
  630. struct ti_sci_msg_hdr hdr;
  631. u8 processor_id;
  632. u32 bootvector_low;
  633. u32 bootvector_high;
  634. u32 config_flags_set;
  635. u32 config_flags_clear;
  636. } __packed;
  637. /* R5 Control Flags */
  638. #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
  639. /**
  640. * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
  641. * @hdr: Generic Header
  642. * @processor_id: ID of processor
  643. * @control_flags_set: Optional Processor specific Control Flags to set.
  644. * Setting a bit here implies required bit sets to 1.
  645. * @control_flags_clear:Optional Processor specific Control Flags to clear.
  646. * Setting a bit here implies required bit gets cleared.
  647. *
  648. * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
  649. * message.
  650. */
  651. struct ti_sci_msg_req_set_proc_boot_ctrl {
  652. struct ti_sci_msg_hdr hdr;
  653. u8 processor_id;
  654. u32 control_flags_set;
  655. u32 control_flags_clear;
  656. } __packed;
  657. /**
  658. * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
  659. * @hdr: Generic Header
  660. * @cert_addr_low: Lower 32bit (Little Endian) of certificate
  661. * @cert_addr_high: Higher 32bit (Little Endian) of certificate
  662. *
  663. * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
  664. * ACK/NACK message.
  665. */
  666. struct ti_sci_msg_req_proc_auth_boot_image {
  667. struct ti_sci_msg_hdr hdr;
  668. u32 cert_addr_low;
  669. u32 cert_addr_high;
  670. } __packed;
  671. struct ti_sci_msg_resp_proc_auth_boot_image {
  672. struct ti_sci_msg_hdr hdr;
  673. u32 image_addr_low;
  674. u32 image_addr_high;
  675. u32 image_size;
  676. } __packed;
  677. /**
  678. * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
  679. * @hdr: Generic Header
  680. * @processor_id: ID of processor
  681. *
  682. * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
  683. * message, or NACK in case of inability to satisfy request.
  684. */
  685. struct ti_sci_msg_req_get_proc_boot_status {
  686. struct ti_sci_msg_hdr hdr;
  687. u8 processor_id;
  688. } __packed;
  689. /* ARMv8 Status Flags */
  690. #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
  691. #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
  692. /* R5 Status Flags */
  693. #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
  694. #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
  695. #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
  696. #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
  697. /**
  698. * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
  699. * @hdr: Generic Header
  700. * @processor_id: ID of processor
  701. * @bootvector_low: Lower 32bit (Little Endian) of boot vector
  702. * @bootvector_high: Higher 32bit (Little Endian) of boot vector
  703. * @config_flags: Optional Processor specific Config Flags set.
  704. * @control_flags: Optional Processor specific Control Flags.
  705. * @status_flags: Optional Processor specific Status Flags set.
  706. *
  707. * Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
  708. */
  709. struct ti_sci_msg_resp_get_proc_boot_status {
  710. struct ti_sci_msg_hdr hdr;
  711. u8 processor_id;
  712. u32 bootvector_low;
  713. u32 bootvector_high;
  714. u32 config_flags;
  715. u32 control_flags;
  716. u32 status_flags;
  717. } __packed;
  718. /**
  719. * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor
  720. * boot status
  721. * @hdr: Generic Header
  722. * @processor_id: ID of processor
  723. * @num_wait_iterations: Total number of iterations we will check before
  724. * we will timeout and give up
  725. * @num_match_iterations: How many iterations should we have continued
  726. * status to account for status bits glitching.
  727. * This is to make sure that match occurs for
  728. * consecutive checks. This implies that the
  729. * worst case should consider that the stable
  730. * time should at the worst be num_wait_iterations
  731. * num_match_iterations to prevent timeout.
  732. * @delay_per_iteration_us: Specifies how long to wait (in micro seconds)
  733. * between each status checks. This is the minimum
  734. * duration, and overhead of register reads and
  735. * checks are on top of this and can vary based on
  736. * varied conditions.
  737. * @delay_before_iterations_us: Specifies how long to wait (in micro seconds)
  738. * before the very first check in the first
  739. * iteration of status check loop. This is the
  740. * minimum duration, and overhead of register
  741. * reads and checks are.
  742. * @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
  743. * status matching this field requested MUST be 1.
  744. * @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
  745. * bits matching this field requested MUST be 1.
  746. * @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
  747. * status matching this field requested MUST be 0.
  748. * @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
  749. * bits matching this field requested MUST be 0.
  750. *
  751. * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate
  752. * message, or NACK in case of inability to satisfy request.
  753. */
  754. struct ti_sci_msg_req_wait_proc_boot_status {
  755. struct ti_sci_msg_hdr hdr;
  756. u8 processor_id;
  757. u8 num_wait_iterations;
  758. u8 num_match_iterations;
  759. u8 delay_per_iteration_us;
  760. u8 delay_before_iterations_us;
  761. u32 status_flags_1_set_all_wait;
  762. u32 status_flags_1_set_any_wait;
  763. u32 status_flags_1_clr_all_wait;
  764. u32 status_flags_1_clr_any_wait;
  765. } __packed;
  766. /**
  767. * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
  768. *
  769. * Configures the non-real-time registers of a Navigator Subsystem ring.
  770. * @hdr: Generic Header
  771. * @valid_params: Bitfield defining validity of ring configuration parameters.
  772. * The ring configuration fields are not valid, and will not be used for
  773. * ring configuration, if their corresponding valid bit is zero.
  774. * Valid bit usage:
  775. * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
  776. * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
  777. * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
  778. * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
  779. * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
  780. * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
  781. * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
  782. * @index: ring index to be configured.
  783. * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
  784. * RING_BA_LO register
  785. * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
  786. * RING_BA_HI register.
  787. * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
  788. * modes.
  789. * @mode: Specifies the mode the ring is to be configured.
  790. * @size: Specifies encoded ring element size. To calculate the encoded size use
  791. * the formula (log2(size_bytes) - 2), where size_bytes cannot be
  792. * greater than 256.
  793. * @order_id: Specifies the ring's bus order ID.
  794. */
  795. struct ti_sci_msg_rm_ring_cfg_req {
  796. struct ti_sci_msg_hdr hdr;
  797. u32 valid_params;
  798. u16 nav_id;
  799. u16 index;
  800. u32 addr_lo;
  801. u32 addr_hi;
  802. u32 count;
  803. u8 mode;
  804. u8 size;
  805. u8 order_id;
  806. } __packed;
  807. /**
  808. * struct ti_sci_msg_rm_ring_cfg_resp - Response to configuring a ring.
  809. *
  810. * @hdr: Generic Header
  811. */
  812. struct ti_sci_msg_rm_ring_cfg_resp {
  813. struct ti_sci_msg_hdr hdr;
  814. } __packed;
  815. /**
  816. * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
  817. *
  818. * Gets the configuration of the non-real-time register fields of a ring. The
  819. * host, or a supervisor of the host, who owns the ring must be the requesting
  820. * host. The values of the non-real-time registers are returned in
  821. * @ti_sci_msg_rm_ring_get_cfg_resp.
  822. *
  823. * @hdr: Generic Header
  824. * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
  825. * @index: ring index.
  826. */
  827. struct ti_sci_msg_rm_ring_get_cfg_req {
  828. struct ti_sci_msg_hdr hdr;
  829. u16 nav_id;
  830. u16 index;
  831. } __packed;
  832. /**
  833. * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
  834. *
  835. * Response received by host processor after RM has handled
  836. * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
  837. * non-real-time register values.
  838. *
  839. * @hdr: Generic Header
  840. * @addr_lo: Ring 32 LSBs of base address
  841. * @addr_hi: Ring 16 MSBs of base address.
  842. * @count: Ring number of elements.
  843. * @mode: Ring mode.
  844. * @size: encoded Ring element size
  845. * @order_id: ing order ID.
  846. */
  847. struct ti_sci_msg_rm_ring_get_cfg_resp {
  848. struct ti_sci_msg_hdr hdr;
  849. u32 addr_lo;
  850. u32 addr_hi;
  851. u32 count;
  852. u8 mode;
  853. u8 size;
  854. u8 order_id;
  855. } __packed;
  856. /**
  857. * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
  858. * thread
  859. * @hdr: Generic Header
  860. * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
  861. * used to pair the source and destination threads.
  862. * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
  863. *
  864. * UDMAP transmit channels mapped to source threads will have their
  865. * TCHAN_THRD_ID register programmed with the destination thread if the pairing
  866. * is successful.
  867. * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
  868. * PSI-L destination threads start at index 0x8000. The request is NACK'd if
  869. * the destination thread is not greater than or equal to 0x8000.
  870. *
  871. * UDMAP receive channels mapped to destination threads will have their
  872. * RCHAN_THRD_ID register programmed with the source thread if the pairing
  873. * is successful.
  874. *
  875. * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
  876. * message.
  877. */
  878. struct ti_sci_msg_psil_pair {
  879. struct ti_sci_msg_hdr hdr;
  880. u32 nav_id;
  881. u32 src_thread;
  882. u32 dst_thread;
  883. } __packed;
  884. /**
  885. * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
  886. * destination thread
  887. * @hdr: Generic Header
  888. * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
  889. * used to unpair the source and destination threads.
  890. * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
  891. *
  892. * UDMAP transmit channels mapped to source threads will have their
  893. * TCHAN_THRD_ID register cleared if the unpairing is successful.
  894. *
  895. * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
  896. * PSI-L destination threads start at index 0x8000. The request is NACK'd if
  897. * the destination thread is not greater than or equal to 0x8000.
  898. *
  899. * UDMAP receive channels mapped to destination threads will have their
  900. * RCHAN_THRD_ID register cleared if the unpairing is successful.
  901. *
  902. * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
  903. * message.
  904. */
  905. struct ti_sci_msg_psil_unpair {
  906. struct ti_sci_msg_hdr hdr;
  907. u32 nav_id;
  908. u32 src_thread;
  909. u32 dst_thread;
  910. } __packed;
  911. /**
  912. * Configures a Navigator Subsystem UDMAP transmit channel
  913. *
  914. * Configures the non-real-time registers of a Navigator Subsystem UDMAP
  915. * transmit channel. The channel index must be assigned to the host defined
  916. * in the TISCI header via the RM board configuration resource assignment
  917. * range list.
  918. *
  919. * @hdr: Generic Header
  920. *
  921. * @valid_params: Bitfield defining validity of tx channel configuration
  922. * parameters. The tx channel configuration fields are not valid, and will not
  923. * be used for ch configuration, if their corresponding valid bit is zero.
  924. * Valid bit usage:
  925. * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
  926. * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
  927. * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
  928. * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
  929. * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
  930. * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
  931. * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
  932. * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
  933. * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
  934. * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
  935. * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
  936. * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
  937. * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
  938. * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
  939. *
  940. * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
  941. *
  942. * @index: UDMAP transmit channel index.
  943. *
  944. * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
  945. * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
  946. * register.
  947. *
  948. * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
  949. * configuration to be programmed into the tx_filt_einfo field of the
  950. * channel's TCHAN_TCFG register.
  951. *
  952. * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
  953. * configuration to be programmed into the tx_filt_pswords field of the
  954. * channel's TCHAN_TCFG register.
  955. *
  956. * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
  957. * interpretation configuration to be programmed into the tx_atype field of
  958. * the channel's TCHAN_TCFG register.
  959. *
  960. * @tx_chan_type: UDMAP transmit channel functional channel type and work
  961. * passing mechanism configuration to be programmed into the tx_chan_type
  962. * field of the channel's TCHAN_TCFG register.
  963. *
  964. * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
  965. * configuration to be programmed into the tx_supr_tdpkt field of the channel's
  966. * TCHAN_TCFG register.
  967. *
  968. * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
  969. * fetch configuration to be programmed into the tx_fetch_size field of the
  970. * channel's TCHAN_TCFG register. The user must make sure to set the maximum
  971. * word count that can pass through the channel for any allowed descriptor type.
  972. *
  973. * @tx_credit_count: UDMAP transmit channel transfer request credit count
  974. * configuration to be programmed into the count field of the TCHAN_TCREDIT
  975. * register. Specifies how many credits for complete TRs are available.
  976. *
  977. * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
  978. * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
  979. * completion queue must be assigned to the host, or a subordinate of the host,
  980. * requesting configuration of the transmit channel.
  981. *
  982. * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
  983. * into the priority field of the channel's TCHAN_TPRI_CTRL register.
  984. *
  985. * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
  986. * qos field of the channel's TCHAN_TPRI_CTRL register.
  987. *
  988. * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
  989. * the orderid field of the channel's TCHAN_TPRI_CTRL register.
  990. *
  991. * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
  992. * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
  993. * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
  994. * section of the TRM for restrictions regarding this parameter.
  995. *
  996. * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
  997. * configuration to be programmed into the priority field of the channel's
  998. * TCHAN_TST_SCHED register.
  999. */
  1000. struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
  1001. struct ti_sci_msg_hdr hdr;
  1002. u32 valid_params;
  1003. u16 nav_id;
  1004. u16 index;
  1005. u8 tx_pause_on_err;
  1006. u8 tx_filt_einfo;
  1007. u8 tx_filt_pswords;
  1008. u8 tx_atype;
  1009. u8 tx_chan_type;
  1010. u8 tx_supr_tdpkt;
  1011. u16 tx_fetch_size;
  1012. u8 tx_credit_count;
  1013. u16 txcq_qnum;
  1014. u8 tx_priority;
  1015. u8 tx_qos;
  1016. u8 tx_orderid;
  1017. u16 fdepth;
  1018. u8 tx_sched_priority;
  1019. } __packed;
  1020. /**
  1021. * Response to configuring a UDMAP transmit channel.
  1022. *
  1023. * @hdr: Standard TISCI header
  1024. */
  1025. struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp {
  1026. struct ti_sci_msg_hdr hdr;
  1027. } __packed;
  1028. /**
  1029. * Configures a Navigator Subsystem UDMAP receive channel
  1030. *
  1031. * Configures the non-real-time registers of a Navigator Subsystem UDMAP
  1032. * receive channel. The channel index must be assigned to the host defined
  1033. * in the TISCI header via the RM board configuration resource assignment
  1034. * range list.
  1035. *
  1036. * @hdr: Generic Header
  1037. *
  1038. * @valid_params: Bitfield defining validity of rx channel configuration
  1039. * parameters.
  1040. * The rx channel configuration fields are not valid, and will not be used for
  1041. * ch configuration, if their corresponding valid bit is zero.
  1042. * Valid bit usage:
  1043. * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
  1044. * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
  1045. * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
  1046. * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
  1047. * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
  1048. * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
  1049. * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
  1050. * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
  1051. * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
  1052. * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
  1053. * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
  1054. * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
  1055. * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
  1056. *
  1057. * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
  1058. *
  1059. * @index: UDMAP receive channel index.
  1060. *
  1061. * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
  1062. * fetch configuration to be programmed into the rx_fetch_size field of the
  1063. * channel's RCHAN_RCFG register.
  1064. *
  1065. * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
  1066. * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
  1067. * The specified completion queue must be assigned to the host, or a subordinate
  1068. * of the host, requesting configuration of the receive channel.
  1069. *
  1070. * @rx_priority: UDMAP receive channel receive priority value to be programmed
  1071. * into the priority field of the channel's RCHAN_RPRI_CTRL register.
  1072. *
  1073. * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
  1074. * qos field of the channel's RCHAN_RPRI_CTRL register.
  1075. *
  1076. * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
  1077. * the orderid field of the channel's RCHAN_RPRI_CTRL register.
  1078. *
  1079. * @rx_sched_priority: UDMAP receive channel rx scheduling priority
  1080. * configuration to be programmed into the priority field of the channel's
  1081. * RCHAN_RST_SCHED register.
  1082. *
  1083. * @flowid_start: UDMAP receive channel additional flows starting index
  1084. * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
  1085. * register. Specifies the starting index for flow IDs the receive channel is to
  1086. * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
  1087. * set as valid and configured together. The starting flow ID set by
  1088. * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
  1089. * of flows beyond the default flows statically mapped to receive channels.
  1090. * The additional flows must be assigned to the host, or a subordinate of the
  1091. * host, requesting configuration of the receive channel.
  1092. *
  1093. * @flowid_cnt: UDMAP receive channel additional flows count configuration to
  1094. * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
  1095. * This field specifies how many flow IDs are in the additional contiguous range
  1096. * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
  1097. * set as valid and configured together. Disabling the valid_params field bit
  1098. * for flowid_cnt indicates no flow IDs other than the default are to be
  1099. * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
  1100. * cannot be greater than the number of receive flows in the receive channel's
  1101. * Navigator Subsystem. The additional flows must be assigned to the host, or a
  1102. * subordinate of the host, requesting configuration of the receive channel.
  1103. *
  1104. * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
  1105. * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
  1106. * register.
  1107. *
  1108. * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
  1109. * interpretation configuration to be programmed into the rx_atype field of the
  1110. * channel's RCHAN_RCFG register.
  1111. *
  1112. * @rx_chan_type: UDMAP receive channel functional channel type and work passing
  1113. * mechanism configuration to be programmed into the rx_chan_type field of the
  1114. * channel's RCHAN_RCFG register.
  1115. *
  1116. * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
  1117. * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
  1118. *
  1119. * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
  1120. * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
  1121. */
  1122. struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
  1123. struct ti_sci_msg_hdr hdr;
  1124. u32 valid_params;
  1125. u16 nav_id;
  1126. u16 index;
  1127. u16 rx_fetch_size;
  1128. u16 rxcq_qnum;
  1129. u8 rx_priority;
  1130. u8 rx_qos;
  1131. u8 rx_orderid;
  1132. u8 rx_sched_priority;
  1133. u16 flowid_start;
  1134. u16 flowid_cnt;
  1135. u8 rx_pause_on_err;
  1136. u8 rx_atype;
  1137. u8 rx_chan_type;
  1138. u8 rx_ignore_short;
  1139. u8 rx_ignore_long;
  1140. } __packed;
  1141. /**
  1142. * Response to configuring a UDMAP receive channel.
  1143. *
  1144. * @hdr: Standard TISCI header
  1145. */
  1146. struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp {
  1147. struct ti_sci_msg_hdr hdr;
  1148. } __packed;
  1149. /**
  1150. * Configures a Navigator Subsystem UDMAP receive flow
  1151. *
  1152. * Configures a Navigator Subsystem UDMAP receive flow's registers.
  1153. * Configuration does not include the flow registers which handle size-based
  1154. * free descriptor queue routing.
  1155. *
  1156. * The flow index must be assigned to the host defined in the TISCI header via
  1157. * the RM board configuration resource assignment range list.
  1158. *
  1159. * @hdr: Standard TISCI header
  1160. *
  1161. * @valid_params
  1162. * Bitfield defining validity of rx flow configuration parameters. The
  1163. * rx flow configuration fields are not valid, and will not be used for flow
  1164. * configuration, if their corresponding valid bit is zero. Valid bit usage:
  1165. * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
  1166. * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
  1167. * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
  1168. * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
  1169. * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
  1170. * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
  1171. * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
  1172. * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
  1173. * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
  1174. * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
  1175. * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
  1176. * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
  1177. * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
  1178. * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
  1179. * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
  1180. * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
  1181. * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
  1182. * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
  1183. * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
  1184. *
  1185. * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
  1186. * allocated
  1187. *
  1188. * @flow_index: UDMAP receive flow index for non-optional configuration.
  1189. *
  1190. * @rx_einfo_present:
  1191. * UDMAP receive flow extended packet info present configuration to be
  1192. * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
  1193. *
  1194. * @rx_psinfo_present:
  1195. * UDMAP receive flow PS words present configuration to be programmed into the
  1196. * rx_psinfo_present field of the flow's RFLOW_RFA register.
  1197. *
  1198. * @rx_error_handling:
  1199. * UDMAP receive flow error handling configuration to be programmed into the
  1200. * rx_error_handling field of the flow's RFLOW_RFA register.
  1201. *
  1202. * @rx_desc_type:
  1203. * UDMAP receive flow descriptor type configuration to be programmed into the
  1204. * rx_desc_type field field of the flow's RFLOW_RFA register.
  1205. *
  1206. * @rx_sop_offset:
  1207. * UDMAP receive flow start of packet offset configuration to be programmed
  1208. * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
  1209. * section of the TRM for more information on this setting. Valid values for
  1210. * this field are 0-255 bytes.
  1211. *
  1212. * @rx_dest_qnum:
  1213. * UDMAP receive flow destination queue configuration to be programmed into the
  1214. * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
  1215. * destination queue must be valid within the Navigator Subsystem and must be
  1216. * owned by the host, or a subordinate of the host, requesting allocation and
  1217. * configuration of the receive flow.
  1218. *
  1219. * @rx_src_tag_hi:
  1220. * UDMAP receive flow source tag high byte constant configuration to be
  1221. * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
  1222. * See the UDMAP section of the TRM for more information on this setting.
  1223. *
  1224. * @rx_src_tag_lo:
  1225. * UDMAP receive flow source tag low byte constant configuration to be
  1226. * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
  1227. * See the UDMAP section of the TRM for more information on this setting.
  1228. *
  1229. * @rx_dest_tag_hi:
  1230. * UDMAP receive flow destination tag high byte constant configuration to be
  1231. * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
  1232. * See the UDMAP section of the TRM for more information on this setting.
  1233. *
  1234. * @rx_dest_tag_lo:
  1235. * UDMAP receive flow destination tag low byte constant configuration to be
  1236. * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
  1237. * See the UDMAP section of the TRM for more information on this setting.
  1238. *
  1239. * @rx_src_tag_hi_sel:
  1240. * UDMAP receive flow source tag high byte selector configuration to be
  1241. * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
  1242. * the UDMAP section of the TRM for more information on this setting.
  1243. *
  1244. * @rx_src_tag_lo_sel:
  1245. * UDMAP receive flow source tag low byte selector configuration to be
  1246. * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
  1247. * the UDMAP section of the TRM for more information on this setting.
  1248. *
  1249. * @rx_dest_tag_hi_sel:
  1250. * UDMAP receive flow destination tag high byte selector configuration to be
  1251. * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
  1252. * the UDMAP section of the TRM for more information on this setting.
  1253. *
  1254. * @rx_dest_tag_lo_sel:
  1255. * UDMAP receive flow destination tag low byte selector configuration to be
  1256. * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
  1257. * the UDMAP section of the TRM for more information on this setting.
  1258. *
  1259. * @rx_fdq0_sz0_qnum:
  1260. * UDMAP receive flow free descriptor queue 0 configuration to be programmed
  1261. * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
  1262. * UDMAP section of the TRM for more information on this setting. The specified
  1263. * free queue must be valid within the Navigator Subsystem and must be owned
  1264. * by the host, or a subordinate of the host, requesting allocation and
  1265. * configuration of the receive flow.
  1266. *
  1267. * @rx_fdq1_qnum:
  1268. * UDMAP receive flow free descriptor queue 1 configuration to be programmed
  1269. * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
  1270. * UDMAP section of the TRM for more information on this setting. The specified
  1271. * free queue must be valid within the Navigator Subsystem and must be owned
  1272. * by the host, or a subordinate of the host, requesting allocation and
  1273. * configuration of the receive flow.
  1274. *
  1275. * @rx_fdq2_qnum:
  1276. * UDMAP receive flow free descriptor queue 2 configuration to be programmed
  1277. * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
  1278. * UDMAP section of the TRM for more information on this setting. The specified
  1279. * free queue must be valid within the Navigator Subsystem and must be owned
  1280. * by the host, or a subordinate of the host, requesting allocation and
  1281. * configuration of the receive flow.
  1282. *
  1283. * @rx_fdq3_qnum:
  1284. * UDMAP receive flow free descriptor queue 3 configuration to be programmed
  1285. * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
  1286. * UDMAP section of the TRM for more information on this setting. The specified
  1287. * free queue must be valid within the Navigator Subsystem and must be owned
  1288. * by the host, or a subordinate of the host, requesting allocation and
  1289. * configuration of the receive flow.
  1290. *
  1291. * @rx_ps_location:
  1292. * UDMAP receive flow PS words location configuration to be programmed into the
  1293. * rx_ps_location field of the flow's RFLOW_RFA register.
  1294. */
  1295. struct ti_sci_msg_rm_udmap_flow_cfg_req {
  1296. struct ti_sci_msg_hdr hdr;
  1297. u32 valid_params;
  1298. u16 nav_id;
  1299. u16 flow_index;
  1300. u8 rx_einfo_present;
  1301. u8 rx_psinfo_present;
  1302. u8 rx_error_handling;
  1303. u8 rx_desc_type;
  1304. u16 rx_sop_offset;
  1305. u16 rx_dest_qnum;
  1306. u8 rx_src_tag_hi;
  1307. u8 rx_src_tag_lo;
  1308. u8 rx_dest_tag_hi;
  1309. u8 rx_dest_tag_lo;
  1310. u8 rx_src_tag_hi_sel;
  1311. u8 rx_src_tag_lo_sel;
  1312. u8 rx_dest_tag_hi_sel;
  1313. u8 rx_dest_tag_lo_sel;
  1314. u16 rx_fdq0_sz0_qnum;
  1315. u16 rx_fdq1_qnum;
  1316. u16 rx_fdq2_qnum;
  1317. u16 rx_fdq3_qnum;
  1318. u8 rx_ps_location;
  1319. } __packed;
  1320. /**
  1321. * Response to configuring a Navigator Subsystem UDMAP receive flow
  1322. *
  1323. * @hdr: Standard TISCI header
  1324. */
  1325. struct ti_sci_msg_rm_udmap_flow_cfg_resp {
  1326. struct ti_sci_msg_hdr hdr;
  1327. } __packed;
  1328. #define FWL_MAX_PRIVID_SLOTS 3U
  1329. /**
  1330. * struct ti_sci_msg_fwl_set_firewall_region_req - Request for configuring the firewall permissions.
  1331. *
  1332. * @hdr: Generic Header
  1333. *
  1334. * @fwl_id: Firewall ID in question
  1335. * @region: Region or channel number to set config info
  1336. * This field is unused in case of a simple firewall and must be initialized
  1337. * to zero. In case of a region based firewall, this field indicates the
  1338. * region in question. (index starting from 0) In case of a channel based
  1339. * firewall, this field indicates the channel in question (index starting
  1340. * from 0)
  1341. * @n_permission_regs: Number of permission registers to set
  1342. * @control: Contents of the firewall CONTROL register to set
  1343. * @permissions: Contents of the firewall PERMISSION register to set
  1344. * @start_address: Contents of the firewall START_ADDRESS register to set
  1345. * @end_address: Contents of the firewall END_ADDRESS register to set
  1346. */
  1347. struct ti_sci_msg_fwl_set_firewall_region_req {
  1348. struct ti_sci_msg_hdr hdr;
  1349. u16 fwl_id;
  1350. u16 region;
  1351. u32 n_permission_regs;
  1352. u32 control;
  1353. u32 permissions[FWL_MAX_PRIVID_SLOTS];
  1354. u64 start_address;
  1355. u64 end_address;
  1356. } __packed;
  1357. /**
  1358. * struct ti_sci_msg_fwl_get_firewall_region_req - Request for retrieving the firewall permissions
  1359. *
  1360. * @hdr: Generic Header
  1361. *
  1362. * @fwl_id: Firewall ID in question
  1363. * @region: Region or channel number to get config info
  1364. * This field is unused in case of a simple firewall and must be initialized
  1365. * to zero. In case of a region based firewall, this field indicates the
  1366. * region in question (index starting from 0). In case of a channel based
  1367. * firewall, this field indicates the channel in question (index starting
  1368. * from 0).
  1369. * @n_permission_regs: Number of permission registers to retrieve
  1370. */
  1371. struct ti_sci_msg_fwl_get_firewall_region_req {
  1372. struct ti_sci_msg_hdr hdr;
  1373. u16 fwl_id;
  1374. u16 region;
  1375. u32 n_permission_regs;
  1376. } __packed;
  1377. /**
  1378. * struct ti_sci_msg_fwl_get_firewall_region_resp - Response for retrieving the firewall permissions
  1379. *
  1380. * @hdr: Generic Header
  1381. *
  1382. * @fwl_id: Firewall ID in question
  1383. * @region: Region or channel number to set config info This field is
  1384. * unused in case of a simple firewall and must be initialized to zero. In
  1385. * case of a region based firewall, this field indicates the region in
  1386. * question. (index starting from 0) In case of a channel based firewall, this
  1387. * field indicates the channel in question (index starting from 0)
  1388. * @n_permission_regs: Number of permission registers retrieved
  1389. * @control: Contents of the firewall CONTROL register
  1390. * @permissions: Contents of the firewall PERMISSION registers
  1391. * @start_address: Contents of the firewall START_ADDRESS register This is not applicable for channelized firewalls.
  1392. * @end_address: Contents of the firewall END_ADDRESS register This is not applicable for channelized firewalls.
  1393. */
  1394. struct ti_sci_msg_fwl_get_firewall_region_resp {
  1395. struct ti_sci_msg_hdr hdr;
  1396. u16 fwl_id;
  1397. u16 region;
  1398. u32 n_permission_regs;
  1399. u32 control;
  1400. u32 permissions[FWL_MAX_PRIVID_SLOTS];
  1401. u64 start_address;
  1402. u64 end_address;
  1403. } __packed;
  1404. /**
  1405. * struct ti_sci_msg_fwl_change_owner_info_req - Request for a firewall owner change
  1406. *
  1407. * @hdr: Generic Header
  1408. *
  1409. * @fwl_id: Firewall ID in question
  1410. * @region: Region or channel number if applicable
  1411. * @owner_index: New owner index to transfer ownership to
  1412. */
  1413. struct ti_sci_msg_fwl_change_owner_info_req {
  1414. struct ti_sci_msg_hdr hdr;
  1415. u16 fwl_id;
  1416. u16 region;
  1417. u8 owner_index;
  1418. } __packed;
  1419. /**
  1420. * struct ti_sci_msg_fwl_change_owner_info_resp - Response for a firewall owner change
  1421. *
  1422. * @hdr: Generic Header
  1423. *
  1424. * @fwl_id: Firewall ID specified in request
  1425. * @region: Region or channel number specified in request
  1426. * @owner_index: Owner index specified in request
  1427. * @owner_privid: New owner priv-ID returned by DMSC.
  1428. * @owner_permission_bits: New owner permission bits returned by DMSC.
  1429. */
  1430. struct ti_sci_msg_fwl_change_owner_info_resp {
  1431. struct ti_sci_msg_hdr hdr;
  1432. u16 fwl_id;
  1433. u16 region;
  1434. u8 owner_index;
  1435. u8 owner_privid;
  1436. u16 owner_permission_bits;
  1437. } __packed;
  1438. #endif /* __TI_SCI_H */