ics8n3qv01.c 4.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. *
  6. * based on the gdsys osd driver, which is
  7. *
  8. * (C) Copyright 2010
  9. * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <clk-uclass.h>
  14. #include <i2c.h>
  15. #include <log.h>
  16. const long long ICS8N3QV01_FREF = 114285000;
  17. const long long ICS8N3QV01_FREF_LL = 114285000LL;
  18. const long long ICS8N3QV01_F_DEFAULT_0 = 156250000LL;
  19. const long long ICS8N3QV01_F_DEFAULT_1 = 125000000LL;
  20. const long long ICS8N3QV01_F_DEFAULT_2 = 100000000LL;
  21. const long long ICS8N3QV01_F_DEFAULT_3 = 25175000LL;
  22. const uint MAX_FREQ_INDEX = 3;
  23. struct ics8n3qv01_priv {
  24. ulong rate;
  25. };
  26. static int ics8n3qv01_get_fout_calc(struct udevice *dev, uint index,
  27. uint *fout_calc)
  28. {
  29. u64 n, mint, mfrac;
  30. u8 reg_a, reg_b, reg_c, reg_d, reg_f;
  31. int val[6];
  32. int i;
  33. if (index > MAX_FREQ_INDEX)
  34. return -EINVAL;
  35. for (i = 0; i <= 5; ++i) {
  36. u8 tmp = dm_i2c_reg_read(dev, 4 * i + index);
  37. if (tmp < 0) {
  38. debug("%s: Error while reading i2c register %d.\n",
  39. dev->name, 4 * i + index);
  40. return tmp;
  41. }
  42. val[i] = tmp;
  43. }
  44. reg_a = val[0]; /* Register 0 + index */
  45. reg_b = val[1]; /* Register 4 + index */
  46. reg_c = val[2]; /* Register 8 + index */
  47. reg_d = val[3]; /* Register 12 + index */
  48. reg_f = val[5]; /* Register 20 + index */
  49. mint = ((reg_a >> 1) & 0x1f) | /* MINTi[4-0]*/
  50. (reg_f & 0x20); /* MINTi[5] */
  51. mfrac = ((reg_a & 0x01) << 17) | /* MFRACi[17] */
  52. (reg_b << 9) | /* MFRACi[16-9] */
  53. (reg_c << 1) | /* MFRACi[8-1] */
  54. (reg_d >> 7); /* MFRACi[0] */
  55. n = reg_d & 0x7f; /* Ni[6-0] */
  56. *fout_calc = (mint * ICS8N3QV01_FREF_LL
  57. + mfrac * ICS8N3QV01_FREF_LL / 262144LL
  58. + ICS8N3QV01_FREF_LL / 524288LL
  59. + n / 2)
  60. / n
  61. * 1000000
  62. / (1000000 - 100);
  63. return 0;
  64. }
  65. static int ics8n3qv01_calc_parameters(uint fout, uint *_mint, uint *_mfrac,
  66. uint *_n)
  67. {
  68. uint n, foutiic, fvcoiic, mint;
  69. u64 mfrac;
  70. n = (2215000000U + fout / 2) / fout;
  71. if (fout < 417000000U)
  72. n = 2 * ((2215000000U / 2 + fout / 2) / fout);
  73. else
  74. n = (2215000000U + fout / 2) / fout;
  75. if ((n & 1) && n > 5)
  76. n -= 1;
  77. foutiic = fout - (fout / 10000);
  78. fvcoiic = foutiic * n;
  79. mint = fvcoiic / 114285000;
  80. if (mint < 17 || mint > 63)
  81. return -EINVAL;
  82. mfrac = ((u64)fvcoiic % 114285000LL) * 262144LL
  83. / 114285000LL;
  84. *_mint = mint;
  85. *_mfrac = mfrac;
  86. *_n = n;
  87. return 0;
  88. }
  89. static ulong ics8n3qv01_set_rate(struct clk *clk, ulong fout)
  90. {
  91. struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev);
  92. uint n, mint, mfrac;
  93. uint fout_calc = 0;
  94. u64 fout_prog;
  95. long long off_ppm;
  96. int res, i;
  97. u8 reg[6];
  98. int tmp;
  99. int addr[] = {0, 4, 8, 12, 18, 20};
  100. priv->rate = fout;
  101. res = ics8n3qv01_get_fout_calc(clk->dev, 1, &fout_calc);
  102. if (res) {
  103. debug("%s: Error during output frequency calculation.\n",
  104. clk->dev->name);
  105. return res;
  106. }
  107. off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
  108. / ICS8N3QV01_F_DEFAULT_1;
  109. printf("%s: PLL is off by %lld ppm\n", clk->dev->name, off_ppm);
  110. fout_prog = (u64)fout * (u64)fout_calc
  111. / ICS8N3QV01_F_DEFAULT_1;
  112. res = ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
  113. if (res) {
  114. debug("%s: Cannot determine mint parameter.\n",
  115. clk->dev->name);
  116. return res;
  117. }
  118. /* Register 0 */
  119. tmp = dm_i2c_reg_read(clk->dev, 0) & 0xc0;
  120. if (tmp < 0)
  121. return tmp;
  122. reg[0] = tmp | (mint & 0x1f) << 1;
  123. reg[0] |= (mfrac >> 17) & 0x01;
  124. /* Register 4 */
  125. reg[1] = mfrac >> 9;
  126. /* Register 8 */
  127. reg[2] = mfrac >> 1;
  128. /* Register 12 */
  129. reg[3] = mfrac << 7;
  130. reg[3] |= n & 0x7f;
  131. /* Register 18 */
  132. tmp = dm_i2c_reg_read(clk->dev, 18) & 0x03;
  133. if (tmp < 0)
  134. return tmp;
  135. reg[4] = tmp | 0x20;
  136. /* Register 20 */
  137. tmp = dm_i2c_reg_read(clk->dev, 20) & 0x1f;
  138. if (tmp < 0)
  139. return tmp;
  140. reg[5] = tmp | (mint & (1 << 5));
  141. for (i = 0; i <= 5; ++i) {
  142. res = dm_i2c_reg_write(clk->dev, addr[i], reg[i]);
  143. if (res < 0)
  144. return res;
  145. }
  146. return 0;
  147. }
  148. static int ics8n3qv01_request(struct clk *clock)
  149. {
  150. return 0;
  151. }
  152. static ulong ics8n3qv01_get_rate(struct clk *clk)
  153. {
  154. struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev);
  155. return priv->rate;
  156. }
  157. static int ics8n3qv01_enable(struct clk *clk)
  158. {
  159. return 0;
  160. }
  161. static int ics8n3qv01_disable(struct clk *clk)
  162. {
  163. return 0;
  164. }
  165. static const struct clk_ops ics8n3qv01_ops = {
  166. .request = ics8n3qv01_request,
  167. .get_rate = ics8n3qv01_get_rate,
  168. .set_rate = ics8n3qv01_set_rate,
  169. .enable = ics8n3qv01_enable,
  170. .disable = ics8n3qv01_disable,
  171. };
  172. static const struct udevice_id ics8n3qv01_ids[] = {
  173. { .compatible = "idt,ics8n3qv01" },
  174. { /* sentinel */ }
  175. };
  176. int ics8n3qv01_probe(struct udevice *dev)
  177. {
  178. return 0;
  179. }
  180. U_BOOT_DRIVER(ics8n3qv01) = {
  181. .name = "ics8n3qv01",
  182. .id = UCLASS_CLK,
  183. .ops = &ics8n3qv01_ops,
  184. .of_match = ics8n3qv01_ids,
  185. .probe = ics8n3qv01_probe,
  186. .priv_auto_alloc_size = sizeof(struct ics8n3qv01_priv),
  187. };