board_f.c 25 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2002-2006
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <bloblist.h>
  13. #include <bootstage.h>
  14. #include <clock_legacy.h>
  15. #include <console.h>
  16. #include <cpu.h>
  17. #include <cpu_func.h>
  18. #include <dm.h>
  19. #include <env.h>
  20. #include <env_internal.h>
  21. #include <fdtdec.h>
  22. #include <fs.h>
  23. #include <hang.h>
  24. #include <i2c.h>
  25. #include <init.h>
  26. #include <initcall.h>
  27. #include <lcd.h>
  28. #include <log.h>
  29. #include <malloc.h>
  30. #include <mapmem.h>
  31. #include <os.h>
  32. #include <post.h>
  33. #include <relocate.h>
  34. #include <serial.h>
  35. #ifdef CONFIG_SPL
  36. #include <spl.h>
  37. #endif
  38. #include <status_led.h>
  39. #include <sysreset.h>
  40. #include <timer.h>
  41. #include <trace.h>
  42. #include <video.h>
  43. #include <watchdog.h>
  44. #include <asm/cache.h>
  45. #ifdef CONFIG_MACH_TYPE
  46. #include <asm/mach-types.h>
  47. #endif
  48. #if defined(CONFIG_MP) && defined(CONFIG_PPC)
  49. #include <asm/mp.h>
  50. #endif
  51. #include <asm/io.h>
  52. #include <asm/sections.h>
  53. #include <dm/root.h>
  54. #include <linux/errno.h>
  55. /*
  56. * Pointer to initial global data area
  57. *
  58. * Here we initialize it if needed.
  59. */
  60. #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
  61. #undef XTRN_DECLARE_GLOBAL_DATA_PTR
  62. #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
  63. DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
  64. #else
  65. DECLARE_GLOBAL_DATA_PTR;
  66. #endif
  67. /*
  68. * TODO(sjg@chromium.org): IMO this code should be
  69. * refactored to a single function, something like:
  70. *
  71. * void led_set_state(enum led_colour_t colour, int on);
  72. */
  73. /************************************************************************
  74. * Coloured LED functionality
  75. ************************************************************************
  76. * May be supplied by boards if desired
  77. */
  78. __weak void coloured_LED_init(void) {}
  79. __weak void red_led_on(void) {}
  80. __weak void red_led_off(void) {}
  81. __weak void green_led_on(void) {}
  82. __weak void green_led_off(void) {}
  83. __weak void yellow_led_on(void) {}
  84. __weak void yellow_led_off(void) {}
  85. __weak void blue_led_on(void) {}
  86. __weak void blue_led_off(void) {}
  87. /*
  88. * Why is gd allocated a register? Prior to reloc it might be better to
  89. * just pass it around to each function in this file?
  90. *
  91. * After reloc one could argue that it is hardly used and doesn't need
  92. * to be in a register. Or if it is it should perhaps hold pointers to all
  93. * global data for all modules, so that post-reloc we can avoid the massive
  94. * literal pool we get on ARM. Or perhaps just encourage each module to use
  95. * a structure...
  96. */
  97. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
  98. static int init_func_watchdog_init(void)
  99. {
  100. # if defined(CONFIG_HW_WATCHDOG) && \
  101. (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
  102. defined(CONFIG_SH) || \
  103. defined(CONFIG_DESIGNWARE_WATCHDOG) || \
  104. defined(CONFIG_IMX_WATCHDOG))
  105. hw_watchdog_init();
  106. puts(" Watchdog enabled\n");
  107. # endif
  108. WATCHDOG_RESET();
  109. return 0;
  110. }
  111. int init_func_watchdog_reset(void)
  112. {
  113. WATCHDOG_RESET();
  114. return 0;
  115. }
  116. #endif /* CONFIG_WATCHDOG */
  117. __weak void board_add_ram_info(int use_default)
  118. {
  119. /* please define platform specific board_add_ram_info() */
  120. }
  121. static int init_baud_rate(void)
  122. {
  123. gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
  124. return 0;
  125. }
  126. static int display_text_info(void)
  127. {
  128. #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
  129. ulong bss_start, bss_end, text_base;
  130. bss_start = (ulong)&__bss_start;
  131. bss_end = (ulong)&__bss_end;
  132. #ifdef CONFIG_SYS_TEXT_BASE
  133. text_base = CONFIG_SYS_TEXT_BASE;
  134. #else
  135. text_base = CONFIG_SYS_MONITOR_BASE;
  136. #endif
  137. debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
  138. text_base, bss_start, bss_end);
  139. #endif
  140. return 0;
  141. }
  142. #ifdef CONFIG_SYSRESET
  143. static int print_resetinfo(void)
  144. {
  145. struct udevice *dev;
  146. char status[256];
  147. int ret;
  148. ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
  149. if (ret) {
  150. debug("%s: No sysreset device found (error: %d)\n",
  151. __func__, ret);
  152. /* Not all boards have sysreset drivers available during early
  153. * boot, so don't fail if one can't be found.
  154. */
  155. return 0;
  156. }
  157. if (!sysreset_get_status(dev, status, sizeof(status)))
  158. printf("%s", status);
  159. return 0;
  160. }
  161. #endif
  162. #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
  163. static int print_cpuinfo(void)
  164. {
  165. struct udevice *dev;
  166. char desc[512];
  167. int ret;
  168. dev = cpu_get_current_dev();
  169. if (!dev) {
  170. debug("%s: Could not get CPU device\n",
  171. __func__);
  172. return -ENODEV;
  173. }
  174. ret = cpu_get_desc(dev, desc, sizeof(desc));
  175. if (ret) {
  176. debug("%s: Could not get CPU description (err = %d)\n",
  177. dev->name, ret);
  178. return ret;
  179. }
  180. printf("CPU: %s\n", desc);
  181. return 0;
  182. }
  183. #endif
  184. static int announce_dram_init(void)
  185. {
  186. puts("DRAM: ");
  187. return 0;
  188. }
  189. static int show_dram_config(void)
  190. {
  191. unsigned long long size;
  192. #ifdef CONFIG_NR_DRAM_BANKS
  193. int i;
  194. debug("\nRAM Configuration:\n");
  195. for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  196. size += gd->bd->bi_dram[i].size;
  197. debug("Bank #%d: %llx ", i,
  198. (unsigned long long)(gd->bd->bi_dram[i].start));
  199. #ifdef DEBUG
  200. print_size(gd->bd->bi_dram[i].size, "\n");
  201. #endif
  202. }
  203. debug("\nDRAM: ");
  204. #else
  205. size = gd->ram_size;
  206. #endif
  207. print_size(size, "");
  208. board_add_ram_info(0);
  209. putc('\n');
  210. return 0;
  211. }
  212. __weak int dram_init_banksize(void)
  213. {
  214. #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
  215. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  216. gd->bd->bi_dram[0].size = get_effective_memsize();
  217. #endif
  218. return 0;
  219. }
  220. #if defined(CONFIG_SYS_I2C)
  221. static int init_func_i2c(void)
  222. {
  223. puts("I2C: ");
  224. #ifdef CONFIG_SYS_I2C
  225. i2c_init_all();
  226. #else
  227. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  228. #endif
  229. puts("ready\n");
  230. return 0;
  231. }
  232. #endif
  233. #if defined(CONFIG_VID)
  234. __weak int init_func_vid(void)
  235. {
  236. return 0;
  237. }
  238. #endif
  239. static int setup_mon_len(void)
  240. {
  241. #if defined(__ARM__) || defined(__MICROBLAZE__)
  242. gd->mon_len = (ulong)&__bss_end - (ulong)_start;
  243. #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
  244. gd->mon_len = (ulong)&_end - (ulong)_init;
  245. #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
  246. gd->mon_len = CONFIG_SYS_MONITOR_LEN;
  247. #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
  248. gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
  249. #elif defined(CONFIG_SYS_MONITOR_BASE)
  250. /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
  251. gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
  252. #endif
  253. return 0;
  254. }
  255. static int setup_spl_handoff(void)
  256. {
  257. #if CONFIG_IS_ENABLED(HANDOFF)
  258. gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
  259. sizeof(struct spl_handoff));
  260. debug("Found SPL hand-off info %p\n", gd->spl_handoff);
  261. #endif
  262. return 0;
  263. }
  264. __weak int arch_cpu_init(void)
  265. {
  266. return 0;
  267. }
  268. __weak int mach_cpu_init(void)
  269. {
  270. return 0;
  271. }
  272. /* Get the top of usable RAM */
  273. __weak ulong board_get_usable_ram_top(ulong total_size)
  274. {
  275. #if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
  276. /*
  277. * Detect whether we have so much RAM that it goes past the end of our
  278. * 32-bit address space. If so, clip the usable RAM so it doesn't.
  279. */
  280. if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
  281. /*
  282. * Will wrap back to top of 32-bit space when reservations
  283. * are made.
  284. */
  285. return 0;
  286. #endif
  287. return gd->ram_top;
  288. }
  289. static int setup_dest_addr(void)
  290. {
  291. debug("Monitor len: %08lX\n", gd->mon_len);
  292. /*
  293. * Ram is setup, size stored in gd !!
  294. */
  295. debug("Ram size: %08lX\n", (ulong)gd->ram_size);
  296. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  297. /*
  298. * Subtract specified amount of memory to hide so that it won't
  299. * get "touched" at all by U-Boot. By fixing up gd->ram_size
  300. * the Linux kernel should now get passed the now "corrected"
  301. * memory size and won't touch it either. This should work
  302. * for arch/ppc and arch/powerpc. Only Linux board ports in
  303. * arch/powerpc with bootwrapper support, that recalculate the
  304. * memory size from the SDRAM controller setup will have to
  305. * get fixed.
  306. */
  307. gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
  308. #endif
  309. #ifdef CONFIG_SYS_SDRAM_BASE
  310. gd->ram_base = CONFIG_SYS_SDRAM_BASE;
  311. #endif
  312. gd->ram_top = gd->ram_base + get_effective_memsize();
  313. gd->ram_top = board_get_usable_ram_top(gd->mon_len);
  314. gd->relocaddr = gd->ram_top;
  315. debug("Ram top: %08lX\n", (ulong)gd->ram_top);
  316. #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
  317. /*
  318. * We need to make sure the location we intend to put secondary core
  319. * boot code is reserved and not used by any part of u-boot
  320. */
  321. if (gd->relocaddr > determine_mp_bootpg(NULL)) {
  322. gd->relocaddr = determine_mp_bootpg(NULL);
  323. debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
  324. }
  325. #endif
  326. return 0;
  327. }
  328. #ifdef CONFIG_PRAM
  329. /* reserve protected RAM */
  330. static int reserve_pram(void)
  331. {
  332. ulong reg;
  333. reg = env_get_ulong("pram", 10, CONFIG_PRAM);
  334. gd->relocaddr -= (reg << 10); /* size is in kB */
  335. debug("Reserving %ldk for protected RAM at %08lx\n", reg,
  336. gd->relocaddr);
  337. return 0;
  338. }
  339. #endif /* CONFIG_PRAM */
  340. /* Round memory pointer down to next 4 kB limit */
  341. static int reserve_round_4k(void)
  342. {
  343. gd->relocaddr &= ~(4096 - 1);
  344. return 0;
  345. }
  346. __weak int arch_reserve_mmu(void)
  347. {
  348. return 0;
  349. }
  350. static int reserve_video(void)
  351. {
  352. #ifdef CONFIG_DM_VIDEO
  353. ulong addr;
  354. int ret;
  355. addr = gd->relocaddr;
  356. ret = video_reserve(&addr);
  357. if (ret)
  358. return ret;
  359. gd->relocaddr = addr;
  360. #elif defined(CONFIG_LCD)
  361. # ifdef CONFIG_FB_ADDR
  362. gd->fb_base = CONFIG_FB_ADDR;
  363. # else
  364. /* reserve memory for LCD display (always full pages) */
  365. gd->relocaddr = lcd_setmem(gd->relocaddr);
  366. gd->fb_base = gd->relocaddr;
  367. # endif /* CONFIG_FB_ADDR */
  368. #endif
  369. return 0;
  370. }
  371. static int reserve_trace(void)
  372. {
  373. #ifdef CONFIG_TRACE
  374. gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
  375. gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
  376. debug("Reserving %luk for trace data at: %08lx\n",
  377. (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
  378. #endif
  379. return 0;
  380. }
  381. static int reserve_uboot(void)
  382. {
  383. if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
  384. /*
  385. * reserve memory for U-Boot code, data & bss
  386. * round down to next 4 kB limit
  387. */
  388. gd->relocaddr -= gd->mon_len;
  389. gd->relocaddr &= ~(4096 - 1);
  390. #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
  391. /* round down to next 64 kB limit so that IVPR stays aligned */
  392. gd->relocaddr &= ~(65536 - 1);
  393. #endif
  394. debug("Reserving %ldk for U-Boot at: %08lx\n",
  395. gd->mon_len >> 10, gd->relocaddr);
  396. }
  397. gd->start_addr_sp = gd->relocaddr;
  398. return 0;
  399. }
  400. /*
  401. * reserve after start_addr_sp the requested size and make the stack pointer
  402. * 16-byte aligned, this alignment is needed for cast on the reserved memory
  403. * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
  404. * = ARMv8 Instruction Set Overview: quad word, 16 bytes
  405. */
  406. static unsigned long reserve_stack_aligned(size_t size)
  407. {
  408. return ALIGN_DOWN(gd->start_addr_sp - size, 16);
  409. }
  410. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  411. static int reserve_noncached(void)
  412. {
  413. /*
  414. * The value of gd->start_addr_sp must match the value of malloc_start
  415. * calculated in boatrd_f.c:initr_malloc(), which is passed to
  416. * board_r.c:mem_malloc_init() and then used by
  417. * cache.c:noncached_init()
  418. *
  419. * These calculations must match the code in cache.c:noncached_init()
  420. */
  421. gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
  422. MMU_SECTION_SIZE;
  423. gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
  424. MMU_SECTION_SIZE);
  425. debug("Reserving %dM for noncached_alloc() at: %08lx\n",
  426. CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
  427. return 0;
  428. }
  429. #endif
  430. /* reserve memory for malloc() area */
  431. static int reserve_malloc(void)
  432. {
  433. gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
  434. debug("Reserving %dk for malloc() at: %08lx\n",
  435. TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
  436. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  437. reserve_noncached();
  438. #endif
  439. return 0;
  440. }
  441. /* (permanently) allocate a Board Info struct */
  442. static int reserve_board(void)
  443. {
  444. if (!gd->bd) {
  445. gd->start_addr_sp = reserve_stack_aligned(sizeof(bd_t));
  446. gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
  447. memset(gd->bd, '\0', sizeof(bd_t));
  448. debug("Reserving %zu Bytes for Board Info at: %08lx\n",
  449. sizeof(bd_t), gd->start_addr_sp);
  450. }
  451. return 0;
  452. }
  453. static int setup_machine(void)
  454. {
  455. #ifdef CONFIG_MACH_TYPE
  456. gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
  457. #endif
  458. return 0;
  459. }
  460. static int reserve_global_data(void)
  461. {
  462. gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
  463. gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
  464. debug("Reserving %zu Bytes for Global Data at: %08lx\n",
  465. sizeof(gd_t), gd->start_addr_sp);
  466. return 0;
  467. }
  468. static int reserve_fdt(void)
  469. {
  470. #ifndef CONFIG_OF_EMBED
  471. /*
  472. * If the device tree is sitting immediately above our image then we
  473. * must relocate it. If it is embedded in the data section, then it
  474. * will be relocated with other data.
  475. */
  476. if (gd->fdt_blob) {
  477. gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
  478. gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
  479. gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
  480. debug("Reserving %lu Bytes for FDT at: %08lx\n",
  481. gd->fdt_size, gd->start_addr_sp);
  482. }
  483. #endif
  484. return 0;
  485. }
  486. static int reserve_bootstage(void)
  487. {
  488. #ifdef CONFIG_BOOTSTAGE
  489. int size = bootstage_get_size();
  490. gd->start_addr_sp = reserve_stack_aligned(size);
  491. gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
  492. debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  493. gd->start_addr_sp);
  494. #endif
  495. return 0;
  496. }
  497. __weak int arch_reserve_stacks(void)
  498. {
  499. return 0;
  500. }
  501. static int reserve_stacks(void)
  502. {
  503. /* make stack pointer 16-byte aligned */
  504. gd->start_addr_sp = reserve_stack_aligned(16);
  505. /*
  506. * let the architecture-specific code tailor gd->start_addr_sp and
  507. * gd->irq_sp
  508. */
  509. return arch_reserve_stacks();
  510. }
  511. static int reserve_bloblist(void)
  512. {
  513. #ifdef CONFIG_BLOBLIST
  514. gd->start_addr_sp = reserve_stack_aligned(CONFIG_BLOBLIST_SIZE);
  515. gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
  516. #endif
  517. return 0;
  518. }
  519. static int display_new_sp(void)
  520. {
  521. debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
  522. return 0;
  523. }
  524. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  525. defined(CONFIG_SH)
  526. static int setup_board_part1(void)
  527. {
  528. bd_t *bd = gd->bd;
  529. /*
  530. * Save local variables to board info struct
  531. */
  532. bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
  533. bd->bi_memsize = gd->ram_size; /* size in bytes */
  534. #ifdef CONFIG_SYS_SRAM_BASE
  535. bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
  536. bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
  537. #endif
  538. #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  539. bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
  540. #endif
  541. #if defined(CONFIG_M68K)
  542. bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
  543. #endif
  544. #if defined(CONFIG_MPC83xx)
  545. bd->bi_immrbar = CONFIG_SYS_IMMR;
  546. #endif
  547. return 0;
  548. }
  549. #endif
  550. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  551. static int setup_board_part2(void)
  552. {
  553. bd_t *bd = gd->bd;
  554. bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
  555. bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
  556. #if defined(CONFIG_CPM2)
  557. bd->bi_cpmfreq = gd->arch.cpm_clk;
  558. bd->bi_brgfreq = gd->arch.brg_clk;
  559. bd->bi_sccfreq = gd->arch.scc_clk;
  560. bd->bi_vco = gd->arch.vco_out;
  561. #endif /* CONFIG_CPM2 */
  562. #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
  563. bd->bi_pcifreq = gd->pci_clk;
  564. #endif
  565. #if defined(CONFIG_EXTRA_CLOCK)
  566. bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
  567. bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
  568. bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
  569. #endif
  570. return 0;
  571. }
  572. #endif
  573. #ifdef CONFIG_POST
  574. static int init_post(void)
  575. {
  576. post_bootmode_init();
  577. post_run(NULL, POST_ROM | post_bootmode_get(0));
  578. return 0;
  579. }
  580. #endif
  581. static int reloc_fdt(void)
  582. {
  583. #ifndef CONFIG_OF_EMBED
  584. if (gd->flags & GD_FLG_SKIP_RELOC)
  585. return 0;
  586. if (gd->new_fdt) {
  587. memcpy(gd->new_fdt, gd->fdt_blob, fdt_totalsize(gd->fdt_blob));
  588. gd->fdt_blob = gd->new_fdt;
  589. }
  590. #endif
  591. return 0;
  592. }
  593. static int reloc_bootstage(void)
  594. {
  595. #ifdef CONFIG_BOOTSTAGE
  596. if (gd->flags & GD_FLG_SKIP_RELOC)
  597. return 0;
  598. if (gd->new_bootstage) {
  599. int size = bootstage_get_size();
  600. debug("Copying bootstage from %p to %p, size %x\n",
  601. gd->bootstage, gd->new_bootstage, size);
  602. memcpy(gd->new_bootstage, gd->bootstage, size);
  603. gd->bootstage = gd->new_bootstage;
  604. bootstage_relocate();
  605. }
  606. #endif
  607. return 0;
  608. }
  609. static int reloc_bloblist(void)
  610. {
  611. #ifdef CONFIG_BLOBLIST
  612. if (gd->flags & GD_FLG_SKIP_RELOC)
  613. return 0;
  614. if (gd->new_bloblist) {
  615. int size = CONFIG_BLOBLIST_SIZE;
  616. debug("Copying bloblist from %p to %p, size %x\n",
  617. gd->bloblist, gd->new_bloblist, size);
  618. memcpy(gd->new_bloblist, gd->bloblist, size);
  619. gd->bloblist = gd->new_bloblist;
  620. }
  621. #endif
  622. return 0;
  623. }
  624. static int setup_reloc(void)
  625. {
  626. if (gd->flags & GD_FLG_SKIP_RELOC) {
  627. debug("Skipping relocation due to flag\n");
  628. return 0;
  629. }
  630. #ifdef CONFIG_SYS_TEXT_BASE
  631. #ifdef ARM
  632. gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
  633. #elif defined(CONFIG_M68K)
  634. /*
  635. * On all ColdFire arch cpu, monitor code starts always
  636. * just after the default vector table location, so at 0x400
  637. */
  638. gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
  639. #elif !defined(CONFIG_SANDBOX)
  640. gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
  641. #endif
  642. #endif
  643. memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
  644. debug("Relocation Offset is: %08lx\n", gd->reloc_off);
  645. debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
  646. gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
  647. gd->start_addr_sp);
  648. return 0;
  649. }
  650. #ifdef CONFIG_OF_BOARD_FIXUP
  651. static int fix_fdt(void)
  652. {
  653. return board_fix_fdt((void *)gd->fdt_blob);
  654. }
  655. #endif
  656. /* ARM calls relocate_code from its crt0.S */
  657. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  658. !CONFIG_IS_ENABLED(X86_64)
  659. static int jump_to_copy(void)
  660. {
  661. if (gd->flags & GD_FLG_SKIP_RELOC)
  662. return 0;
  663. /*
  664. * x86 is special, but in a nice way. It uses a trampoline which
  665. * enables the dcache if possible.
  666. *
  667. * For now, other archs use relocate_code(), which is implemented
  668. * similarly for all archs. When we do generic relocation, hopefully
  669. * we can make all archs enable the dcache prior to relocation.
  670. */
  671. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  672. /*
  673. * SDRAM and console are now initialised. The final stack can now
  674. * be setup in SDRAM. Code execution will continue in Flash, but
  675. * with the stack in SDRAM and Global Data in temporary memory
  676. * (CPU cache)
  677. */
  678. arch_setup_gd(gd->new_gd);
  679. board_init_f_r_trampoline(gd->start_addr_sp);
  680. #else
  681. relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
  682. #endif
  683. return 0;
  684. }
  685. #endif
  686. /* Record the board_init_f() bootstage (after arch_cpu_init()) */
  687. static int initf_bootstage(void)
  688. {
  689. bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
  690. IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
  691. int ret;
  692. ret = bootstage_init(!from_spl);
  693. if (ret)
  694. return ret;
  695. if (from_spl) {
  696. const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
  697. CONFIG_BOOTSTAGE_STASH_SIZE);
  698. ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
  699. if (ret && ret != -ENOENT) {
  700. debug("Failed to unstash bootstage: err=%d\n", ret);
  701. return ret;
  702. }
  703. }
  704. bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
  705. return 0;
  706. }
  707. static int initf_console_record(void)
  708. {
  709. #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  710. return console_record_init();
  711. #else
  712. return 0;
  713. #endif
  714. }
  715. static int initf_dm(void)
  716. {
  717. #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  718. int ret;
  719. bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
  720. ret = dm_init_and_scan(true);
  721. bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F);
  722. if (ret)
  723. return ret;
  724. #endif
  725. #ifdef CONFIG_TIMER_EARLY
  726. ret = dm_timer_init();
  727. if (ret)
  728. return ret;
  729. #endif
  730. return 0;
  731. }
  732. /* Architecture-specific memory reservation */
  733. __weak int reserve_arch(void)
  734. {
  735. return 0;
  736. }
  737. __weak int arch_cpu_init_dm(void)
  738. {
  739. return 0;
  740. }
  741. __weak int checkcpu(void)
  742. {
  743. return 0;
  744. }
  745. __weak int clear_bss(void)
  746. {
  747. return 0;
  748. }
  749. static const init_fnc_t init_sequence_f[] = {
  750. setup_mon_len,
  751. #ifdef CONFIG_OF_CONTROL
  752. fdtdec_setup,
  753. #endif
  754. #ifdef CONFIG_TRACE_EARLY
  755. trace_early_init,
  756. #endif
  757. initf_malloc,
  758. log_init,
  759. initf_bootstage, /* uses its own timer, so does not need DM */
  760. #ifdef CONFIG_BLOBLIST
  761. bloblist_init,
  762. #endif
  763. setup_spl_handoff,
  764. initf_console_record,
  765. #if defined(CONFIG_HAVE_FSP)
  766. arch_fsp_init,
  767. #endif
  768. arch_cpu_init, /* basic arch cpu dependent setup */
  769. mach_cpu_init, /* SoC/machine dependent CPU setup */
  770. initf_dm,
  771. arch_cpu_init_dm,
  772. #if defined(CONFIG_BOARD_EARLY_INIT_F)
  773. board_early_init_f,
  774. #endif
  775. #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
  776. /* get CPU and bus clocks according to the environment variable */
  777. get_clocks, /* get CPU and bus clocks (etc.) */
  778. #endif
  779. #if !defined(CONFIG_M68K)
  780. timer_init, /* initialize timer */
  781. #endif
  782. #if defined(CONFIG_BOARD_POSTCLK_INIT)
  783. board_postclk_init,
  784. #endif
  785. env_init, /* initialize environment */
  786. init_baud_rate, /* initialze baudrate settings */
  787. serial_init, /* serial communications setup */
  788. console_init_f, /* stage 1 init of console */
  789. display_options, /* say that we are here */
  790. display_text_info, /* show debugging info if required */
  791. checkcpu,
  792. #if defined(CONFIG_SYSRESET)
  793. print_resetinfo,
  794. #endif
  795. #if defined(CONFIG_DISPLAY_CPUINFO)
  796. print_cpuinfo, /* display cpu info (and speed) */
  797. #endif
  798. #if defined(CONFIG_DTB_RESELECT)
  799. embedded_dtb_select,
  800. #endif
  801. #if defined(CONFIG_DISPLAY_BOARDINFO)
  802. show_board_info,
  803. #endif
  804. INIT_FUNC_WATCHDOG_INIT
  805. #if defined(CONFIG_MISC_INIT_F)
  806. misc_init_f,
  807. #endif
  808. INIT_FUNC_WATCHDOG_RESET
  809. #if defined(CONFIG_SYS_I2C)
  810. init_func_i2c,
  811. #endif
  812. #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
  813. init_func_vid,
  814. #endif
  815. announce_dram_init,
  816. dram_init, /* configure available RAM banks */
  817. #ifdef CONFIG_POST
  818. post_init_f,
  819. #endif
  820. INIT_FUNC_WATCHDOG_RESET
  821. #if defined(CONFIG_SYS_DRAM_TEST)
  822. testdram,
  823. #endif /* CONFIG_SYS_DRAM_TEST */
  824. INIT_FUNC_WATCHDOG_RESET
  825. #ifdef CONFIG_POST
  826. init_post,
  827. #endif
  828. INIT_FUNC_WATCHDOG_RESET
  829. /*
  830. * Now that we have DRAM mapped and working, we can
  831. * relocate the code and continue running from DRAM.
  832. *
  833. * Reserve memory at end of RAM for (top down in that order):
  834. * - area that won't get touched by U-Boot and Linux (optional)
  835. * - kernel log buffer
  836. * - protected RAM
  837. * - LCD framebuffer
  838. * - monitor code
  839. * - board info struct
  840. */
  841. setup_dest_addr,
  842. #ifdef CONFIG_PRAM
  843. reserve_pram,
  844. #endif
  845. reserve_round_4k,
  846. arch_reserve_mmu,
  847. reserve_video,
  848. reserve_trace,
  849. reserve_uboot,
  850. reserve_malloc,
  851. reserve_board,
  852. setup_machine,
  853. reserve_global_data,
  854. reserve_fdt,
  855. reserve_bootstage,
  856. reserve_bloblist,
  857. reserve_arch,
  858. reserve_stacks,
  859. dram_init_banksize,
  860. show_dram_config,
  861. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  862. defined(CONFIG_SH)
  863. setup_board_part1,
  864. #endif
  865. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  866. INIT_FUNC_WATCHDOG_RESET
  867. setup_board_part2,
  868. #endif
  869. display_new_sp,
  870. #ifdef CONFIG_OF_BOARD_FIXUP
  871. fix_fdt,
  872. #endif
  873. INIT_FUNC_WATCHDOG_RESET
  874. reloc_fdt,
  875. reloc_bootstage,
  876. reloc_bloblist,
  877. setup_reloc,
  878. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  879. copy_uboot_to_ram,
  880. do_elf_reloc_fixups,
  881. #endif
  882. clear_bss,
  883. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  884. !CONFIG_IS_ENABLED(X86_64)
  885. jump_to_copy,
  886. #endif
  887. NULL,
  888. };
  889. void board_init_f(ulong boot_flags)
  890. {
  891. gd->flags = boot_flags;
  892. gd->have_console = 0;
  893. if (initcall_run_list(init_sequence_f))
  894. hang();
  895. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  896. !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
  897. !defined(CONFIG_ARC)
  898. /* NOTREACHED - jump_to_copy() does not return */
  899. hang();
  900. #endif
  901. }
  902. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  903. /*
  904. * For now this code is only used on x86.
  905. *
  906. * init_sequence_f_r is the list of init functions which are run when
  907. * U-Boot is executing from Flash with a semi-limited 'C' environment.
  908. * The following limitations must be considered when implementing an
  909. * '_f_r' function:
  910. * - 'static' variables are read-only
  911. * - Global Data (gd->xxx) is read/write
  912. *
  913. * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
  914. * supported). It _should_, if possible, copy global data to RAM and
  915. * initialise the CPU caches (to speed up the relocation process)
  916. *
  917. * NOTE: At present only x86 uses this route, but it is intended that
  918. * all archs will move to this when generic relocation is implemented.
  919. */
  920. static const init_fnc_t init_sequence_f_r[] = {
  921. #if !CONFIG_IS_ENABLED(X86_64)
  922. init_cache_f_r,
  923. #endif
  924. NULL,
  925. };
  926. void board_init_f_r(void)
  927. {
  928. if (initcall_run_list(init_sequence_f_r))
  929. hang();
  930. /*
  931. * The pre-relocation drivers may be using memory that has now gone
  932. * away. Mark serial as unavailable - this will fall back to the debug
  933. * UART if available.
  934. *
  935. * Do the same with log drivers since the memory may not be available.
  936. */
  937. gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
  938. #ifdef CONFIG_TIMER
  939. gd->timer = NULL;
  940. #endif
  941. /*
  942. * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
  943. * Transfer execution from Flash to RAM by calculating the address
  944. * of the in-RAM copy of board_init_r() and calling it
  945. */
  946. (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
  947. /* NOTREACHED - board_init_r() does not return */
  948. hang();
  949. }
  950. #endif /* CONFIG_X86 */