lx2160a_common.h 8.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018-2021 NXP
  4. */
  5. #ifndef __LX2_COMMON_H
  6. #define __LX2_COMMON_H
  7. #include <asm/arch/stream_id_lsch3.h>
  8. #include <asm/arch/config.h>
  9. #include <asm/arch/soc.h>
  10. #define CONFIG_REMAKE_ELF
  11. #define CONFIG_FSL_TZPC_BP147
  12. #define CONFIG_FSL_MEMAC
  13. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  14. #define CONFIG_SYS_FLASH_BASE 0x20000000
  15. /* DDR */
  16. #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
  17. #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
  18. #define CONFIG_VERY_BIG_RAM
  19. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  20. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  21. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
  22. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
  23. #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
  24. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  25. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  26. #define SPD_EEPROM_ADDRESS1 0x51
  27. #define SPD_EEPROM_ADDRESS2 0x52
  28. #define SPD_EEPROM_ADDRESS3 0x53
  29. #define SPD_EEPROM_ADDRESS4 0x54
  30. #define SPD_EEPROM_ADDRESS5 0x55
  31. #define SPD_EEPROM_ADDRESS6 0x56
  32. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  33. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  34. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  35. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  36. #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
  37. #define CONFIG_SYS_MONITOR_LEN (936 * 1024)
  38. /* Miscellaneous configurable options */
  39. /* SMP Definitinos */
  40. #define CPU_RELEASE_ADDR secondary_boot_addr
  41. /* Generic Timer Definitions */
  42. /*
  43. * This is not an accurate number. It is used in start.S. The frequency
  44. * will be udpated later when get_bus_freq(0) is available.
  45. */
  46. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  47. /* Serial Port */
  48. #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
  49. #define CONFIG_SYS_SERIAL0 0x21c0000
  50. #define CONFIG_SYS_SERIAL1 0x21d0000
  51. #define CONFIG_SYS_SERIAL2 0x21e0000
  52. #define CONFIG_SYS_SERIAL3 0x21f0000
  53. /*below might needs to be removed*/
  54. #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
  55. (void *)CONFIG_SYS_SERIAL1, \
  56. (void *)CONFIG_SYS_SERIAL2, \
  57. (void *)CONFIG_SYS_SERIAL3 }
  58. /* MC firmware */
  59. #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  60. #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  61. #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  62. #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  63. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  64. /* Define phy_reset function to boot the MC based on mcinitcmd.
  65. * This happens late enough to properly fixup u-boot env MAC addresses.
  66. */
  67. #define CONFIG_RESET_PHY_R
  68. /*
  69. * Carve out a DDR region which will not be used by u-boot/Linux
  70. *
  71. * It will be used by MC and Debug Server. The MC region must be
  72. * 512MB aligned, so the min size to hide is 512MB.
  73. */
  74. #ifdef CONFIG_FSL_MC_ENET
  75. #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
  76. #endif
  77. /* I2C bus multiplexer */
  78. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  79. #define I2C_MUX_CH_DEFAULT 0x8
  80. /* RTC */
  81. #define RTC
  82. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  83. /* EEPROM */
  84. #define CONFIG_SYS_I2C_EEPROM_NXID
  85. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  86. /* Qixis */
  87. #define CONFIG_FSL_QIXIS
  88. #define CONFIG_QIXIS_I2C_ACCESS
  89. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  90. /* PCI */
  91. #ifdef CONFIG_PCI
  92. #define CONFIG_SYS_PCI_64BIT
  93. #define CONFIG_PCI_SCAN_SHOW
  94. #endif
  95. /* SATA */
  96. #ifdef CONFIG_SCSI
  97. #define CONFIG_SCSI_AHCI_PLAT
  98. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  99. #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
  100. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  101. #define CONFIG_SYS_SCSI_MAX_LUN 1
  102. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  103. CONFIG_SYS_SCSI_MAX_LUN)
  104. #endif
  105. /* USB */
  106. #ifdef CONFIG_USB_HOST
  107. #ifndef CONFIG_TARGET_LX2162AQDS
  108. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  109. #endif
  110. #endif
  111. /* GPIO */
  112. #ifdef CONFIG_DM_GPIO
  113. #ifndef CONFIG_MPC8XXX_GPIO
  114. #define CONFIG_MPC8XXX_GPIO
  115. #endif
  116. #endif
  117. #ifndef __ASSEMBLY__
  118. unsigned long get_board_sys_clk(void);
  119. #endif
  120. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  121. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
  122. #define CONFIG_HWCONFIG
  123. #define HWCONFIG_BUFFER_SIZE 128
  124. /* Monitor Command Prompt */
  125. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  126. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  127. sizeof(CONFIG_SYS_PROMPT) + 16)
  128. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  129. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  130. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  131. /* Initial environment variables */
  132. #define XSPI_MC_INIT_CMD \
  133. "sf probe 0:0 && " \
  134. "sf read 0x80640000 0x640000 0x80000 && " \
  135. "sf read $fdt_addr_r 0xf00000 0x100000 && " \
  136. "env exists secureboot && " \
  137. "esbc_validate 0x80640000 && " \
  138. "esbc_validate 0x80680000; " \
  139. "sf read 0x80a00000 0xa00000 0x300000 && " \
  140. "sf read 0x80e00000 0xe00000 0x100000; " \
  141. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  142. #define SD_MC_INIT_CMD \
  143. "mmc read 0x80a00000 0x5000 0x1200;" \
  144. "mmc read 0x80e00000 0x7000 0x800;" \
  145. "mmc read $fdt_addr_r 0x7800 0x800;" \
  146. "env exists secureboot && " \
  147. "mmc read 0x80640000 0x3200 0x20 && " \
  148. "mmc read 0x80680000 0x3400 0x20 && " \
  149. "esbc_validate 0x80640000 && " \
  150. "esbc_validate 0x80680000 ;" \
  151. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  152. #define SD2_MC_INIT_CMD \
  153. "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
  154. "mmc read 0x80e00000 0x7000 0x800;" \
  155. "mmc read $fdt_addr_r 0x7800 0x800;" \
  156. "env exists secureboot && " \
  157. "mmc read 0x80640000 0x3200 0x20 && " \
  158. "mmc read 0x80680000 0x3400 0x20 && " \
  159. "esbc_validate 0x80640000 && " \
  160. "esbc_validate 0x80680000 ;" \
  161. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  162. #define EXTRA_ENV_SETTINGS \
  163. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  164. "ramdisk_addr=0x800000\0" \
  165. "ramdisk_size=0x2000000\0" \
  166. "fdt_high=0xa0000000\0" \
  167. "initrd_high=0xffffffffffffffff\0" \
  168. "fdt_addr=0x64f00000\0" \
  169. "kernel_start=0x1000000\0" \
  170. "kernelheader_start=0x600000\0" \
  171. "scriptaddr=0x80000000\0" \
  172. "scripthdraddr=0x80080000\0" \
  173. "fdtheader_addr_r=0x80100000\0" \
  174. "kernelheader_addr_r=0x80200000\0" \
  175. "kernel_addr_r=0x81000000\0" \
  176. "kernelheader_size=0x40000\0" \
  177. "fdt_addr_r=0x90000000\0" \
  178. "load_addr=0xa0000000\0" \
  179. "kernel_size=0x2800000\0" \
  180. "kernel_addr_sd=0x8000\0" \
  181. "kernelhdr_addr_sd=0x3000\0" \
  182. "kernel_size_sd=0x14000\0" \
  183. "kernelhdr_size_sd=0x20\0" \
  184. "console=ttyAMA0,38400n8\0" \
  185. BOOTENV \
  186. "mcmemsize=0x70000000\0" \
  187. XSPI_MC_INIT_CMD \
  188. "scan_dev_for_boot_part=" \
  189. "part list ${devtype} ${devnum} devplist; " \
  190. "env exists devplist || setenv devplist 1; " \
  191. "for distro_bootpart in ${devplist}; do " \
  192. "if fstype ${devtype} " \
  193. "${devnum}:${distro_bootpart} " \
  194. "bootfstype; then " \
  195. "run scan_dev_for_boot; " \
  196. "fi; " \
  197. "done\0" \
  198. "boot_a_script=" \
  199. "load ${devtype} ${devnum}:${distro_bootpart} " \
  200. "${scriptaddr} ${prefix}${script}; " \
  201. "env exists secureboot && load ${devtype} " \
  202. "${devnum}:${distro_bootpart} " \
  203. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  204. "&& esbc_validate ${scripthdraddr};" \
  205. "source ${scriptaddr}\0"
  206. #define XSPI_NOR_BOOTCOMMAND \
  207. "sf probe 0:0; " \
  208. "sf read 0x806c0000 0x6c0000 0x40000; " \
  209. "env exists mcinitcmd && env exists secureboot" \
  210. " && esbc_validate 0x806c0000; " \
  211. "sf read 0x80d00000 0xd00000 0x100000; " \
  212. "env exists mcinitcmd && " \
  213. "fsl_mc lazyapply dpl 0x80d00000; " \
  214. "run distro_bootcmd;run xspi_bootcmd; " \
  215. "env exists secureboot && esbc_halt;"
  216. #define SD_BOOTCOMMAND \
  217. "env exists mcinitcmd && mmcinfo; " \
  218. "mmc read 0x80d00000 0x6800 0x800; " \
  219. "env exists mcinitcmd && env exists secureboot " \
  220. " && mmc read 0x806C0000 0x3600 0x20 " \
  221. "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
  222. "&& fsl_mc lazyapply dpl 0x80d00000;" \
  223. "run distro_bootcmd;run sd_bootcmd;" \
  224. "env exists secureboot && esbc_halt;"
  225. #define SD2_BOOTCOMMAND \
  226. "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
  227. "mmc read 0x80d00000 0x6800 0x800; " \
  228. "env exists mcinitcmd && env exists secureboot " \
  229. " && mmc read 0x806C0000 0x3600 0x20 " \
  230. "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
  231. "&& fsl_mc lazyapply dpl 0x80d00000;" \
  232. "run distro_bootcmd;run sd2_bootcmd;" \
  233. "env exists secureboot && esbc_halt;"
  234. #define BOOT_TARGET_DEVICES(func) \
  235. func(USB, usb, 0) \
  236. func(MMC, mmc, 0) \
  237. func(MMC, mmc, 1) \
  238. func(SCSI, scsi, 0) \
  239. func(DHCP, dhcp, na)
  240. #include <config_distro_bootcmd.h>
  241. #endif /* __LX2_COMMON_H */