cvmx-qlm.h 8.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. */
  5. #ifndef __CVMX_QLM_H__
  6. #define __CVMX_QLM_H__
  7. /*
  8. * Interface 0 on the 78xx can be connected to qlm 0 or qlm 2. When interface
  9. * 0 is connected to qlm 0, this macro must be set to 0. When interface 0 is
  10. * connected to qlm 2, this macro must be set to 1.
  11. */
  12. #define MUX_78XX_IFACE0 0
  13. /*
  14. * Interface 1 on the 78xx can be connected to qlm 1 or qlm 3. When interface
  15. * 1 is connected to qlm 1, this macro must be set to 0. When interface 1 is
  16. * connected to qlm 3, this macro must be set to 1.
  17. */
  18. #define MUX_78XX_IFACE1 0
  19. /* Uncomment this line to print QLM JTAG state */
  20. /* #define CVMX_QLM_DUMP_STATE 1 */
  21. typedef struct {
  22. const char *name;
  23. int stop_bit;
  24. int start_bit;
  25. } __cvmx_qlm_jtag_field_t;
  26. /**
  27. * Return the number of QLMs supported by the chip
  28. *
  29. * Return: Number of QLMs
  30. */
  31. int cvmx_qlm_get_num(void);
  32. /**
  33. * Return the qlm number based on the interface
  34. *
  35. * @param xiface Interface to look
  36. */
  37. int cvmx_qlm_interface(int xiface);
  38. /**
  39. * Return the qlm number based for a port in the interface
  40. *
  41. * @param xiface interface to look up
  42. * @param index index in an interface
  43. *
  44. * Return: the qlm number based on the xiface
  45. */
  46. int cvmx_qlm_lmac(int xiface, int index);
  47. /**
  48. * Return if only DLM5/DLM6/DLM5+DLM6 is used by BGX
  49. *
  50. * @param BGX BGX to search for.
  51. *
  52. * Return: muxes used 0 = DLM5+DLM6, 1 = DLM5, 2 = DLM6.
  53. */
  54. int cvmx_qlm_mux_interface(int bgx);
  55. /**
  56. * Return number of lanes for a given qlm
  57. *
  58. * @param qlm QLM block to query
  59. *
  60. * Return: Number of lanes
  61. */
  62. int cvmx_qlm_get_lanes(int qlm);
  63. /**
  64. * Get the QLM JTAG fields based on Octeon model on the supported chips.
  65. *
  66. * Return: qlm_jtag_field_t structure
  67. */
  68. const __cvmx_qlm_jtag_field_t *cvmx_qlm_jtag_get_field(void);
  69. /**
  70. * Get the QLM JTAG length by going through qlm_jtag_field for each
  71. * Octeon model that is supported
  72. *
  73. * Return: return the length.
  74. */
  75. int cvmx_qlm_jtag_get_length(void);
  76. /**
  77. * Initialize the QLM layer
  78. */
  79. void cvmx_qlm_init(void);
  80. /**
  81. * Get a field in a QLM JTAG chain
  82. *
  83. * @param qlm QLM to get
  84. * @param lane Lane in QLM to get
  85. * @param name String name of field
  86. *
  87. * Return: JTAG field value
  88. */
  89. u64 cvmx_qlm_jtag_get(int qlm, int lane, const char *name);
  90. /**
  91. * Set a field in a QLM JTAG chain
  92. *
  93. * @param qlm QLM to set
  94. * @param lane Lane in QLM to set, or -1 for all lanes
  95. * @param name String name of field
  96. * @param value Value of the field
  97. */
  98. void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, u64 value);
  99. /**
  100. * Errata G-16094: QLM Gen2 Equalizer Default Setting Change.
  101. * CN68XX pass 1.x and CN66XX pass 1.x QLM tweak. This function tweaks the
  102. * JTAG setting for a QLMs to run better at 5 and 6.25Ghz.
  103. */
  104. void __cvmx_qlm_speed_tweak(void);
  105. /**
  106. * Errata G-16174: QLM Gen2 PCIe IDLE DAC change.
  107. * CN68XX pass 1.x, CN66XX pass 1.x and CN63XX pass 1.0-2.2 QLM tweak.
  108. * This function tweaks the JTAG setting for a QLMs for PCIe to run better.
  109. */
  110. void __cvmx_qlm_pcie_idle_dac_tweak(void);
  111. void __cvmx_qlm_pcie_cfg_rxd_set_tweak(int qlm, int lane);
  112. /**
  113. * Get the speed (Gbaud) of the QLM in Mhz.
  114. *
  115. * @param qlm QLM to examine
  116. *
  117. * Return: Speed in Mhz
  118. */
  119. int cvmx_qlm_get_gbaud_mhz(int qlm);
  120. /**
  121. * Get the speed (Gbaud) of the QLM in Mhz on specific node.
  122. *
  123. * @param node Target QLM node
  124. * @param qlm QLM to examine
  125. *
  126. * Return: Speed in Mhz
  127. */
  128. int cvmx_qlm_get_gbaud_mhz_node(int node, int qlm);
  129. enum cvmx_qlm_mode {
  130. CVMX_QLM_MODE_DISABLED = -1,
  131. CVMX_QLM_MODE_SGMII = 1,
  132. CVMX_QLM_MODE_XAUI,
  133. CVMX_QLM_MODE_RXAUI,
  134. CVMX_QLM_MODE_PCIE, /* gen3 / gen2 / gen1 */
  135. CVMX_QLM_MODE_PCIE_1X2, /* 1x2 gen2 / gen1 */
  136. CVMX_QLM_MODE_PCIE_2X1, /* 2x1 gen2 / gen1 */
  137. CVMX_QLM_MODE_PCIE_1X1, /* 1x1 gen2 / gen1 */
  138. CVMX_QLM_MODE_SRIO_1X4, /* 1x4 short / long */
  139. CVMX_QLM_MODE_SRIO_2X2, /* 2x2 short / long */
  140. CVMX_QLM_MODE_SRIO_4X1, /* 4x1 short / long */
  141. CVMX_QLM_MODE_ILK,
  142. CVMX_QLM_MODE_QSGMII,
  143. CVMX_QLM_MODE_SGMII_SGMII,
  144. CVMX_QLM_MODE_SGMII_DISABLED,
  145. CVMX_QLM_MODE_DISABLED_SGMII,
  146. CVMX_QLM_MODE_SGMII_QSGMII,
  147. CVMX_QLM_MODE_QSGMII_QSGMII,
  148. CVMX_QLM_MODE_QSGMII_DISABLED,
  149. CVMX_QLM_MODE_DISABLED_QSGMII,
  150. CVMX_QLM_MODE_QSGMII_SGMII,
  151. CVMX_QLM_MODE_RXAUI_1X2,
  152. CVMX_QLM_MODE_SATA_2X1,
  153. CVMX_QLM_MODE_XLAUI,
  154. CVMX_QLM_MODE_XFI,
  155. CVMX_QLM_MODE_10G_KR,
  156. CVMX_QLM_MODE_40G_KR4,
  157. CVMX_QLM_MODE_PCIE_1X8, /* 1x8 gen3 / gen2 / gen1 */
  158. CVMX_QLM_MODE_RGMII_SGMII,
  159. CVMX_QLM_MODE_RGMII_XFI,
  160. CVMX_QLM_MODE_RGMII_10G_KR,
  161. CVMX_QLM_MODE_RGMII_RXAUI,
  162. CVMX_QLM_MODE_RGMII_XAUI,
  163. CVMX_QLM_MODE_RGMII_XLAUI,
  164. CVMX_QLM_MODE_RGMII_40G_KR4,
  165. CVMX_QLM_MODE_MIXED, /* BGX2 is mixed mode, DLM5(SGMII) & DLM6(XFI) */
  166. CVMX_QLM_MODE_SGMII_2X1, /* Configure BGX2 separate for DLM5 & DLM6 */
  167. CVMX_QLM_MODE_10G_KR_1X2, /* Configure BGX2 separate for DLM5 & DLM6 */
  168. CVMX_QLM_MODE_XFI_1X2, /* Configure BGX2 separate for DLM5 & DLM6 */
  169. CVMX_QLM_MODE_RGMII_SGMII_1X1, /* Configure BGX2, applies to DLM5 */
  170. CVMX_QLM_MODE_RGMII_SGMII_2X1, /* Configure BGX2, applies to DLM6 */
  171. CVMX_QLM_MODE_RGMII_10G_KR_1X1, /* Configure BGX2, applies to DLM6 */
  172. CVMX_QLM_MODE_RGMII_XFI_1X1, /* Configure BGX2, applies to DLM6 */
  173. CVMX_QLM_MODE_SDL, /* RMAC Pipe */
  174. CVMX_QLM_MODE_CPRI, /* RMAC */
  175. CVMX_QLM_MODE_OCI
  176. };
  177. enum cvmx_gmx_inf_mode {
  178. CVMX_GMX_INF_MODE_DISABLED = 0,
  179. CVMX_GMX_INF_MODE_SGMII = 1, /* Other interface can be SGMII or QSGMII */
  180. CVMX_GMX_INF_MODE_QSGMII = 2, /* Other interface can be SGMII or QSGMII */
  181. CVMX_GMX_INF_MODE_RXAUI = 3, /* Only interface 0, interface 1 must be DISABLED */
  182. };
  183. /**
  184. * Eye diagram captures are stored in the following structure
  185. */
  186. typedef struct {
  187. int width; /* Width in the x direction (time) */
  188. int height; /* Height in the y direction (voltage) */
  189. u32 data[64][128]; /* Error count at location, saturates as max */
  190. } cvmx_qlm_eye_t;
  191. /**
  192. * These apply to DLM1 and DLM2 if its not in SATA mode
  193. * Manual refers to lanes as follows:
  194. * DML 0 lane 0 == GSER0 lane 0
  195. * DML 0 lane 1 == GSER0 lane 1
  196. * DML 1 lane 2 == GSER1 lane 0
  197. * DML 1 lane 3 == GSER1 lane 1
  198. * DML 2 lane 4 == GSER2 lane 0
  199. * DML 2 lane 5 == GSER2 lane 1
  200. */
  201. enum cvmx_pemx_cfg_mode {
  202. CVMX_PEM_MD_GEN2_2LANE = 0, /* Valid for PEM0(DLM1), PEM1(DLM2) */
  203. CVMX_PEM_MD_GEN2_1LANE = 1, /* Valid for PEM0(DLM1.0), PEM1(DLM1.1,DLM2.0), PEM2(DLM2.1) */
  204. CVMX_PEM_MD_GEN2_4LANE = 2, /* Valid for PEM0(DLM1-2) */
  205. /* Reserved */
  206. CVMX_PEM_MD_GEN1_2LANE = 4, /* Valid for PEM0(DLM1), PEM1(DLM2) */
  207. CVMX_PEM_MD_GEN1_1LANE = 5, /* Valid for PEM0(DLM1.0), PEM1(DLM1.1,DLM2.0), PEM2(DLM2.1) */
  208. CVMX_PEM_MD_GEN1_4LANE = 6, /* Valid for PEM0(DLM1-2) */
  209. /* Reserved */
  210. };
  211. /*
  212. * Read QLM and return mode.
  213. */
  214. enum cvmx_qlm_mode cvmx_qlm_get_mode(int qlm);
  215. enum cvmx_qlm_mode cvmx_qlm_get_mode_cn78xx(int node, int qlm);
  216. enum cvmx_qlm_mode cvmx_qlm_get_dlm_mode(int dlm_mode, int interface);
  217. void __cvmx_qlm_set_mult(int qlm, int baud_mhz, int old_multiplier);
  218. void cvmx_qlm_display_registers(int qlm);
  219. int cvmx_qlm_measure_clock(int qlm);
  220. /**
  221. * Measure the reference clock of a QLM on a multi-node setup
  222. *
  223. * @param node node to measure
  224. * @param qlm QLM to measure
  225. *
  226. * Return: Clock rate in Hz
  227. */
  228. int cvmx_qlm_measure_clock_node(int node, int qlm);
  229. /*
  230. * Perform RX equalization on a QLM
  231. *
  232. * @param node Node the QLM is on
  233. * @param qlm QLM to perform RX equalization on
  234. * @param lane Lane to use, or -1 for all lanes
  235. *
  236. * Return: Zero on success, negative if any lane failed RX equalization
  237. */
  238. int __cvmx_qlm_rx_equalization(int node, int qlm, int lane);
  239. /**
  240. * Errata GSER-27882 -GSER 10GBASE-KR Transmit Equalizer
  241. * Training may not update PHY Tx Taps. This function is not static
  242. * so we can share it with BGX KR
  243. *
  244. * @param node Node to apply errata workaround
  245. * @param qlm QLM to apply errata workaround
  246. * @param lane Lane to apply the errata
  247. */
  248. int cvmx_qlm_gser_errata_27882(int node, int qlm, int lane);
  249. void cvmx_qlm_gser_errata_25992(int node, int qlm);
  250. #ifdef CVMX_DUMP_GSER
  251. /**
  252. * Dump GSER configuration for node 0
  253. */
  254. int cvmx_dump_gser_config(unsigned int gser);
  255. /**
  256. * Dump GSER status for node 0
  257. */
  258. int cvmx_dump_gser_status(unsigned int gser);
  259. /**
  260. * Dump GSER configuration
  261. */
  262. int cvmx_dump_gser_config_node(unsigned int node, unsigned int gser);
  263. /**
  264. * Dump GSER status
  265. */
  266. int cvmx_dump_gser_status_node(unsigned int node, unsigned int gser);
  267. #endif
  268. int cvmx_qlm_eye_display(int node, int qlm, int qlm_lane, int format, const cvmx_qlm_eye_t *eye);
  269. void cvmx_prbs_process_cmd(int node, int qlm, int mode);
  270. #endif /* __CVMX_QLM_H__ */