cvmx-pip.h 36 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. *
  5. * Interface to the hardware Packet Input Processing unit.
  6. */
  7. #ifndef __CVMX_PIP_H__
  8. #define __CVMX_PIP_H__
  9. #include "cvmx-wqe.h"
  10. #include "cvmx-pki.h"
  11. #include "cvmx-helper-pki.h"
  12. #include "cvmx-helper.h"
  13. #include "cvmx-helper-util.h"
  14. #include "cvmx-pki-resources.h"
  15. #define CVMX_PIP_NUM_INPUT_PORTS 46
  16. #define CVMX_PIP_NUM_WATCHERS 8
  17. /*
  18. * Encodes the different error and exception codes
  19. */
  20. typedef enum {
  21. CVMX_PIP_L4_NO_ERR = 0ull,
  22. /* 1 = TCP (UDP) packet not long enough to cover TCP (UDP) header */
  23. CVMX_PIP_L4_MAL_ERR = 1ull,
  24. /* 2 = TCP/UDP checksum failure */
  25. CVMX_PIP_CHK_ERR = 2ull,
  26. /* 3 = TCP/UDP length check (TCP/UDP length does not match IP length) */
  27. CVMX_PIP_L4_LENGTH_ERR = 3ull,
  28. /* 4 = illegal TCP/UDP port (either source or dest port is zero) */
  29. CVMX_PIP_BAD_PRT_ERR = 4ull,
  30. /* 8 = TCP flags = FIN only */
  31. CVMX_PIP_TCP_FLG8_ERR = 8ull,
  32. /* 9 = TCP flags = 0 */
  33. CVMX_PIP_TCP_FLG9_ERR = 9ull,
  34. /* 10 = TCP flags = FIN+RST+* */
  35. CVMX_PIP_TCP_FLG10_ERR = 10ull,
  36. /* 11 = TCP flags = SYN+URG+* */
  37. CVMX_PIP_TCP_FLG11_ERR = 11ull,
  38. /* 12 = TCP flags = SYN+RST+* */
  39. CVMX_PIP_TCP_FLG12_ERR = 12ull,
  40. /* 13 = TCP flags = SYN+FIN+* */
  41. CVMX_PIP_TCP_FLG13_ERR = 13ull
  42. } cvmx_pip_l4_err_t;
  43. typedef enum {
  44. CVMX_PIP_IP_NO_ERR = 0ull,
  45. /* 1 = not IPv4 or IPv6 */
  46. CVMX_PIP_NOT_IP = 1ull,
  47. /* 2 = IPv4 header checksum violation */
  48. CVMX_PIP_IPV4_HDR_CHK = 2ull,
  49. /* 3 = malformed (packet not long enough to cover IP hdr) */
  50. CVMX_PIP_IP_MAL_HDR = 3ull,
  51. /* 4 = malformed (packet not long enough to cover len in IP hdr) */
  52. CVMX_PIP_IP_MAL_PKT = 4ull,
  53. /* 5 = TTL / hop count equal zero */
  54. CVMX_PIP_TTL_HOP = 5ull,
  55. /* 6 = IPv4 options / IPv6 early extension headers */
  56. CVMX_PIP_OPTS = 6ull
  57. } cvmx_pip_ip_exc_t;
  58. /**
  59. * NOTES
  60. * late collision (data received before collision)
  61. * late collisions cannot be detected by the receiver
  62. * they would appear as JAM bits which would appear as bad FCS
  63. * or carrier extend error which is CVMX_PIP_EXTEND_ERR
  64. */
  65. typedef enum {
  66. /**
  67. * No error
  68. */
  69. CVMX_PIP_RX_NO_ERR = 0ull,
  70. CVMX_PIP_PARTIAL_ERR =
  71. 1ull, /* RGM+SPI 1 = partially received packet (buffering/bandwidth not adequate) */
  72. CVMX_PIP_JABBER_ERR =
  73. 2ull, /* RGM+SPI 2 = receive packet too large and truncated */
  74. CVMX_PIP_OVER_FCS_ERR =
  75. 3ull, /* RGM 3 = max frame error (pkt len > max frame len) (with FCS error) */
  76. CVMX_PIP_OVER_ERR =
  77. 4ull, /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
  78. CVMX_PIP_ALIGN_ERR =
  79. 5ull, /* RGM 5 = nibble error (data not byte multiple - 100M and 10M only) */
  80. CVMX_PIP_UNDER_FCS_ERR =
  81. 6ull, /* RGM 6 = min frame error (pkt len < min frame len) (with FCS error) */
  82. CVMX_PIP_GMX_FCS_ERR = 7ull, /* RGM 7 = FCS error */
  83. CVMX_PIP_UNDER_ERR =
  84. 8ull, /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
  85. CVMX_PIP_EXTEND_ERR = 9ull, /* RGM 9 = Frame carrier extend error */
  86. CVMX_PIP_TERMINATE_ERR =
  87. 9ull, /* XAUI 9 = Packet was terminated with an idle cycle */
  88. CVMX_PIP_LENGTH_ERR =
  89. 10ull, /* RGM 10 = length mismatch (len did not match len in L2 length/type) */
  90. CVMX_PIP_DAT_ERR =
  91. 11ull, /* RGM 11 = Frame error (some or all data bits marked err) */
  92. CVMX_PIP_DIP_ERR = 11ull, /* SPI 11 = DIP4 error */
  93. CVMX_PIP_SKIP_ERR =
  94. 12ull, /* RGM 12 = packet was not large enough to pass the skipper - no inspection could occur */
  95. CVMX_PIP_NIBBLE_ERR =
  96. 13ull, /* RGM 13 = studder error (data not repeated - 100M and 10M only) */
  97. CVMX_PIP_PIP_FCS = 16L, /* RGM+SPI 16 = FCS error */
  98. CVMX_PIP_PIP_SKIP_ERR =
  99. 17L, /* RGM+SPI+PCI 17 = packet was not large enough to pass the skipper - no inspection could occur */
  100. CVMX_PIP_PIP_L2_MAL_HDR =
  101. 18L, /* RGM+SPI+PCI 18 = malformed l2 (packet not long enough to cover L2 hdr) */
  102. CVMX_PIP_PUNY_ERR =
  103. 47L /* SGMII 47 = PUNY error (packet was 4B or less when FCS stripping is enabled) */
  104. /* NOTES
  105. * xx = late collision (data received before collision)
  106. * late collisions cannot be detected by the receiver
  107. * they would appear as JAM bits which would appear as bad FCS
  108. * or carrier extend error which is CVMX_PIP_EXTEND_ERR
  109. */
  110. } cvmx_pip_rcv_err_t;
  111. /**
  112. * This defines the err_code field errors in the work Q entry
  113. */
  114. typedef union {
  115. cvmx_pip_l4_err_t l4_err;
  116. cvmx_pip_ip_exc_t ip_exc;
  117. cvmx_pip_rcv_err_t rcv_err;
  118. } cvmx_pip_err_t;
  119. /**
  120. * Status statistics for a port
  121. */
  122. typedef struct {
  123. u64 dropped_octets;
  124. u64 dropped_packets;
  125. u64 pci_raw_packets;
  126. u64 octets;
  127. u64 packets;
  128. u64 multicast_packets;
  129. u64 broadcast_packets;
  130. u64 len_64_packets;
  131. u64 len_65_127_packets;
  132. u64 len_128_255_packets;
  133. u64 len_256_511_packets;
  134. u64 len_512_1023_packets;
  135. u64 len_1024_1518_packets;
  136. u64 len_1519_max_packets;
  137. u64 fcs_align_err_packets;
  138. u64 runt_packets;
  139. u64 runt_crc_packets;
  140. u64 oversize_packets;
  141. u64 oversize_crc_packets;
  142. u64 inb_packets;
  143. u64 inb_octets;
  144. u64 inb_errors;
  145. u64 mcast_l2_red_packets;
  146. u64 bcast_l2_red_packets;
  147. u64 mcast_l3_red_packets;
  148. u64 bcast_l3_red_packets;
  149. } cvmx_pip_port_status_t;
  150. /**
  151. * Definition of the PIP custom header that can be prepended
  152. * to a packet by external hardware.
  153. */
  154. typedef union {
  155. u64 u64;
  156. struct {
  157. u64 rawfull : 1;
  158. u64 reserved0 : 5;
  159. cvmx_pip_port_parse_mode_t parse_mode : 2;
  160. u64 reserved1 : 1;
  161. u64 skip_len : 7;
  162. u64 grpext : 2;
  163. u64 nqos : 1;
  164. u64 ngrp : 1;
  165. u64 ntt : 1;
  166. u64 ntag : 1;
  167. u64 qos : 3;
  168. u64 grp : 4;
  169. u64 rs : 1;
  170. cvmx_pow_tag_type_t tag_type : 2;
  171. u64 tag : 32;
  172. } s;
  173. } cvmx_pip_pkt_inst_hdr_t;
  174. enum cvmx_pki_pcam_match {
  175. CVMX_PKI_PCAM_MATCH_IP,
  176. CVMX_PKI_PCAM_MATCH_IPV4,
  177. CVMX_PKI_PCAM_MATCH_IPV6,
  178. CVMX_PKI_PCAM_MATCH_TCP
  179. };
  180. /* CSR typedefs have been moved to cvmx-pip-defs.h */
  181. static inline int cvmx_pip_config_watcher(int index, int type, u16 match, u16 mask, int grp,
  182. int qos)
  183. {
  184. if (index >= CVMX_PIP_NUM_WATCHERS) {
  185. debug("ERROR: pip watcher %d is > than supported\n", index);
  186. return -1;
  187. }
  188. if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
  189. /* store in software for now, only when the watcher is enabled program the entry*/
  190. if (type == CVMX_PIP_QOS_WATCH_PROTNH) {
  191. qos_watcher[index].field = CVMX_PKI_PCAM_TERM_L3_FLAGS;
  192. qos_watcher[index].data = (u32)(match << 16);
  193. qos_watcher[index].data_mask = (u32)(mask << 16);
  194. qos_watcher[index].advance = 0;
  195. } else if (type == CVMX_PIP_QOS_WATCH_TCP) {
  196. qos_watcher[index].field = CVMX_PKI_PCAM_TERM_L4_PORT;
  197. qos_watcher[index].data = 0x060000;
  198. qos_watcher[index].data |= (u32)match;
  199. qos_watcher[index].data_mask = (u32)(mask);
  200. qos_watcher[index].advance = 0;
  201. } else if (type == CVMX_PIP_QOS_WATCH_UDP) {
  202. qos_watcher[index].field = CVMX_PKI_PCAM_TERM_L4_PORT;
  203. qos_watcher[index].data = 0x110000;
  204. qos_watcher[index].data |= (u32)match;
  205. qos_watcher[index].data_mask = (u32)(mask);
  206. qos_watcher[index].advance = 0;
  207. } else if (type == 0x4 /*CVMX_PIP_QOS_WATCH_ETHERTYPE*/) {
  208. qos_watcher[index].field = CVMX_PKI_PCAM_TERM_ETHTYPE0;
  209. if (match == 0x8100) {
  210. debug("ERROR: default vlan entry already exist, cant set watcher\n");
  211. return -1;
  212. }
  213. qos_watcher[index].data = (u32)(match << 16);
  214. qos_watcher[index].data_mask = (u32)(mask << 16);
  215. qos_watcher[index].advance = 4;
  216. } else {
  217. debug("ERROR: Unsupported watcher type %d\n", type);
  218. return -1;
  219. }
  220. if (grp >= 32) {
  221. debug("ERROR: grp %d out of range for backward compat 78xx\n", grp);
  222. return -1;
  223. }
  224. qos_watcher[index].sso_grp = (u8)(grp << 3 | qos);
  225. qos_watcher[index].configured = 1;
  226. } else {
  227. /* Implement it later */
  228. }
  229. return 0;
  230. }
  231. static inline int __cvmx_pip_set_tag_type(int node, int style, int tag_type, int field)
  232. {
  233. struct cvmx_pki_style_config style_cfg;
  234. int style_num;
  235. int pcam_offset;
  236. int bank;
  237. struct cvmx_pki_pcam_input pcam_input;
  238. struct cvmx_pki_pcam_action pcam_action;
  239. /* All other style parameters remain same except tag type */
  240. cvmx_pki_read_style_config(node, style, CVMX_PKI_CLUSTER_ALL, &style_cfg);
  241. style_cfg.parm_cfg.tag_type = (enum cvmx_sso_tag_type)tag_type;
  242. style_num = cvmx_pki_style_alloc(node, -1);
  243. if (style_num < 0) {
  244. debug("ERROR: style not available to set tag type\n");
  245. return -1;
  246. }
  247. cvmx_pki_write_style_config(node, style_num, CVMX_PKI_CLUSTER_ALL, &style_cfg);
  248. memset(&pcam_input, 0, sizeof(pcam_input));
  249. memset(&pcam_action, 0, sizeof(pcam_action));
  250. pcam_input.style = style;
  251. pcam_input.style_mask = 0xff;
  252. if (field == CVMX_PKI_PCAM_MATCH_IP) {
  253. pcam_input.field = CVMX_PKI_PCAM_TERM_ETHTYPE0;
  254. pcam_input.field_mask = 0xff;
  255. pcam_input.data = 0x08000000;
  256. pcam_input.data_mask = 0xffff0000;
  257. pcam_action.pointer_advance = 4;
  258. /* legacy will write to all clusters*/
  259. bank = 0;
  260. pcam_offset = cvmx_pki_pcam_entry_alloc(node, CVMX_PKI_FIND_AVAL_ENTRY, bank,
  261. CVMX_PKI_CLUSTER_ALL);
  262. if (pcam_offset < 0) {
  263. debug("ERROR: pcam entry not available to enable qos watcher\n");
  264. cvmx_pki_style_free(node, style_num);
  265. return -1;
  266. }
  267. pcam_action.parse_mode_chg = CVMX_PKI_PARSE_NO_CHG;
  268. pcam_action.layer_type_set = CVMX_PKI_LTYPE_E_NONE;
  269. pcam_action.style_add = (u8)(style_num - style);
  270. cvmx_pki_pcam_write_entry(node, pcam_offset, CVMX_PKI_CLUSTER_ALL, pcam_input,
  271. pcam_action);
  272. field = CVMX_PKI_PCAM_MATCH_IPV6;
  273. }
  274. if (field == CVMX_PKI_PCAM_MATCH_IPV4) {
  275. pcam_input.field = CVMX_PKI_PCAM_TERM_ETHTYPE0;
  276. pcam_input.field_mask = 0xff;
  277. pcam_input.data = 0x08000000;
  278. pcam_input.data_mask = 0xffff0000;
  279. pcam_action.pointer_advance = 4;
  280. } else if (field == CVMX_PKI_PCAM_MATCH_IPV6) {
  281. pcam_input.field = CVMX_PKI_PCAM_TERM_ETHTYPE0;
  282. pcam_input.field_mask = 0xff;
  283. pcam_input.data = 0x86dd00000;
  284. pcam_input.data_mask = 0xffff0000;
  285. pcam_action.pointer_advance = 4;
  286. } else if (field == CVMX_PKI_PCAM_MATCH_TCP) {
  287. pcam_input.field = CVMX_PKI_PCAM_TERM_L4_PORT;
  288. pcam_input.field_mask = 0xff;
  289. pcam_input.data = 0x60000;
  290. pcam_input.data_mask = 0xff0000;
  291. pcam_action.pointer_advance = 0;
  292. }
  293. pcam_action.parse_mode_chg = CVMX_PKI_PARSE_NO_CHG;
  294. pcam_action.layer_type_set = CVMX_PKI_LTYPE_E_NONE;
  295. pcam_action.style_add = (u8)(style_num - style);
  296. bank = pcam_input.field & 0x01;
  297. pcam_offset = cvmx_pki_pcam_entry_alloc(node, CVMX_PKI_FIND_AVAL_ENTRY, bank,
  298. CVMX_PKI_CLUSTER_ALL);
  299. if (pcam_offset < 0) {
  300. debug("ERROR: pcam entry not available to enable qos watcher\n");
  301. cvmx_pki_style_free(node, style_num);
  302. return -1;
  303. }
  304. cvmx_pki_pcam_write_entry(node, pcam_offset, CVMX_PKI_CLUSTER_ALL, pcam_input, pcam_action);
  305. return style_num;
  306. }
  307. /* Only for legacy internal use */
  308. static inline int __cvmx_pip_enable_watcher_78xx(int node, int index, int style)
  309. {
  310. struct cvmx_pki_style_config style_cfg;
  311. struct cvmx_pki_qpg_config qpg_cfg;
  312. struct cvmx_pki_pcam_input pcam_input;
  313. struct cvmx_pki_pcam_action pcam_action;
  314. int style_num;
  315. int qpg_offset;
  316. int pcam_offset;
  317. int bank;
  318. if (!qos_watcher[index].configured) {
  319. debug("ERROR: qos watcher %d should be configured before enable\n", index);
  320. return -1;
  321. }
  322. /* All other style parameters remain same except grp and qos and qps base */
  323. cvmx_pki_read_style_config(node, style, CVMX_PKI_CLUSTER_ALL, &style_cfg);
  324. cvmx_pki_read_qpg_entry(node, style_cfg.parm_cfg.qpg_base, &qpg_cfg);
  325. qpg_cfg.qpg_base = CVMX_PKI_FIND_AVAL_ENTRY;
  326. qpg_cfg.grp_ok = qos_watcher[index].sso_grp;
  327. qpg_cfg.grp_bad = qos_watcher[index].sso_grp;
  328. qpg_offset = cvmx_helper_pki_set_qpg_entry(node, &qpg_cfg);
  329. if (qpg_offset == -1) {
  330. debug("Warning: no new qpg entry available to enable watcher\n");
  331. return -1;
  332. }
  333. /* try to reserve the style, if it is not configured already, reserve
  334. and configure it */
  335. style_cfg.parm_cfg.qpg_base = qpg_offset;
  336. style_num = cvmx_pki_style_alloc(node, -1);
  337. if (style_num < 0) {
  338. debug("ERROR: style not available to enable qos watcher\n");
  339. cvmx_pki_qpg_entry_free(node, qpg_offset, 1);
  340. return -1;
  341. }
  342. cvmx_pki_write_style_config(node, style_num, CVMX_PKI_CLUSTER_ALL, &style_cfg);
  343. /* legacy will write to all clusters*/
  344. bank = qos_watcher[index].field & 0x01;
  345. pcam_offset = cvmx_pki_pcam_entry_alloc(node, CVMX_PKI_FIND_AVAL_ENTRY, bank,
  346. CVMX_PKI_CLUSTER_ALL);
  347. if (pcam_offset < 0) {
  348. debug("ERROR: pcam entry not available to enable qos watcher\n");
  349. cvmx_pki_style_free(node, style_num);
  350. cvmx_pki_qpg_entry_free(node, qpg_offset, 1);
  351. return -1;
  352. }
  353. memset(&pcam_input, 0, sizeof(pcam_input));
  354. memset(&pcam_action, 0, sizeof(pcam_action));
  355. pcam_input.style = style;
  356. pcam_input.style_mask = 0xff;
  357. pcam_input.field = qos_watcher[index].field;
  358. pcam_input.field_mask = 0xff;
  359. pcam_input.data = qos_watcher[index].data;
  360. pcam_input.data_mask = qos_watcher[index].data_mask;
  361. pcam_action.parse_mode_chg = CVMX_PKI_PARSE_NO_CHG;
  362. pcam_action.layer_type_set = CVMX_PKI_LTYPE_E_NONE;
  363. pcam_action.style_add = (u8)(style_num - style);
  364. pcam_action.pointer_advance = qos_watcher[index].advance;
  365. cvmx_pki_pcam_write_entry(node, pcam_offset, CVMX_PKI_CLUSTER_ALL, pcam_input, pcam_action);
  366. return 0;
  367. }
  368. /**
  369. * Configure an ethernet input port
  370. *
  371. * @param ipd_port Port number to configure
  372. * @param port_cfg Port hardware configuration
  373. * @param port_tag_cfg Port POW tagging configuration
  374. */
  375. static inline void cvmx_pip_config_port(u64 ipd_port, cvmx_pip_prt_cfgx_t port_cfg,
  376. cvmx_pip_prt_tagx_t port_tag_cfg)
  377. {
  378. struct cvmx_pki_qpg_config qpg_cfg;
  379. int qpg_offset;
  380. u8 tcp_tag = 0xff;
  381. u8 ip_tag = 0xaa;
  382. int style, nstyle, n4style, n6style;
  383. if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
  384. struct cvmx_pki_port_config pki_prt_cfg;
  385. struct cvmx_xport xp = cvmx_helper_ipd_port_to_xport(ipd_port);
  386. cvmx_pki_get_port_config(ipd_port, &pki_prt_cfg);
  387. style = pki_prt_cfg.pkind_cfg.initial_style;
  388. if (port_cfg.s.ih_pri || port_cfg.s.vlan_len || port_cfg.s.pad_len)
  389. debug("Warning: 78xx: use different config for this option\n");
  390. pki_prt_cfg.style_cfg.parm_cfg.minmax_sel = port_cfg.s.len_chk_sel;
  391. pki_prt_cfg.style_cfg.parm_cfg.lenerr_en = port_cfg.s.lenerr_en;
  392. pki_prt_cfg.style_cfg.parm_cfg.maxerr_en = port_cfg.s.maxerr_en;
  393. pki_prt_cfg.style_cfg.parm_cfg.minerr_en = port_cfg.s.minerr_en;
  394. pki_prt_cfg.style_cfg.parm_cfg.fcs_chk = port_cfg.s.crc_en;
  395. if (port_cfg.s.grp_wat || port_cfg.s.qos_wat || port_cfg.s.grp_wat_47 ||
  396. port_cfg.s.qos_wat_47) {
  397. u8 group_mask = (u8)(port_cfg.s.grp_wat | (u8)(port_cfg.s.grp_wat_47 << 4));
  398. u8 qos_mask = (u8)(port_cfg.s.qos_wat | (u8)(port_cfg.s.qos_wat_47 << 4));
  399. int i;
  400. for (i = 0; i < CVMX_PIP_NUM_WATCHERS; i++) {
  401. if ((group_mask & (1 << i)) || (qos_mask & (1 << i)))
  402. __cvmx_pip_enable_watcher_78xx(xp.node, i, style);
  403. }
  404. }
  405. if (port_tag_cfg.s.tag_mode) {
  406. if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
  407. cvmx_printf("Warning: mask tag is not supported in 78xx pass1\n");
  408. else {
  409. }
  410. /* need to implement for 78xx*/
  411. }
  412. if (port_cfg.s.tag_inc)
  413. debug("Warning: 78xx uses differnet method for tag generation\n");
  414. pki_prt_cfg.style_cfg.parm_cfg.rawdrp = port_cfg.s.rawdrp;
  415. pki_prt_cfg.pkind_cfg.parse_en.inst_hdr = port_cfg.s.inst_hdr;
  416. if (port_cfg.s.hg_qos)
  417. pki_prt_cfg.style_cfg.parm_cfg.qpg_qos = CVMX_PKI_QPG_QOS_HIGIG;
  418. else if (port_cfg.s.qos_vlan)
  419. pki_prt_cfg.style_cfg.parm_cfg.qpg_qos = CVMX_PKI_QPG_QOS_VLAN;
  420. else if (port_cfg.s.qos_diff)
  421. pki_prt_cfg.style_cfg.parm_cfg.qpg_qos = CVMX_PKI_QPG_QOS_DIFFSERV;
  422. if (port_cfg.s.qos_vod)
  423. debug("Warning: 78xx needs pcam entries installed to achieve qos_vod\n");
  424. if (port_cfg.s.qos) {
  425. cvmx_pki_read_qpg_entry(xp.node, pki_prt_cfg.style_cfg.parm_cfg.qpg_base,
  426. &qpg_cfg);
  427. qpg_cfg.qpg_base = CVMX_PKI_FIND_AVAL_ENTRY;
  428. qpg_cfg.grp_ok |= port_cfg.s.qos;
  429. qpg_cfg.grp_bad |= port_cfg.s.qos;
  430. qpg_offset = cvmx_helper_pki_set_qpg_entry(xp.node, &qpg_cfg);
  431. if (qpg_offset == -1)
  432. debug("Warning: no new qpg entry available, will not modify qos\n");
  433. else
  434. pki_prt_cfg.style_cfg.parm_cfg.qpg_base = qpg_offset;
  435. }
  436. if (port_tag_cfg.s.grp != pki_dflt_sso_grp[xp.node].group) {
  437. cvmx_pki_read_qpg_entry(xp.node, pki_prt_cfg.style_cfg.parm_cfg.qpg_base,
  438. &qpg_cfg);
  439. qpg_cfg.qpg_base = CVMX_PKI_FIND_AVAL_ENTRY;
  440. qpg_cfg.grp_ok |= (u8)(port_tag_cfg.s.grp << 3);
  441. qpg_cfg.grp_bad |= (u8)(port_tag_cfg.s.grp << 3);
  442. qpg_offset = cvmx_helper_pki_set_qpg_entry(xp.node, &qpg_cfg);
  443. if (qpg_offset == -1)
  444. debug("Warning: no new qpg entry available, will not modify group\n");
  445. else
  446. pki_prt_cfg.style_cfg.parm_cfg.qpg_base = qpg_offset;
  447. }
  448. pki_prt_cfg.pkind_cfg.parse_en.dsa_en = port_cfg.s.dsa_en;
  449. pki_prt_cfg.pkind_cfg.parse_en.hg_en = port_cfg.s.higig_en;
  450. pki_prt_cfg.style_cfg.tag_cfg.tag_fields.layer_c_src =
  451. port_tag_cfg.s.ip6_src_flag | port_tag_cfg.s.ip4_src_flag;
  452. pki_prt_cfg.style_cfg.tag_cfg.tag_fields.layer_c_dst =
  453. port_tag_cfg.s.ip6_dst_flag | port_tag_cfg.s.ip4_dst_flag;
  454. pki_prt_cfg.style_cfg.tag_cfg.tag_fields.ip_prot_nexthdr =
  455. port_tag_cfg.s.ip6_nxth_flag | port_tag_cfg.s.ip4_pctl_flag;
  456. pki_prt_cfg.style_cfg.tag_cfg.tag_fields.layer_d_src =
  457. port_tag_cfg.s.ip6_sprt_flag | port_tag_cfg.s.ip4_sprt_flag;
  458. pki_prt_cfg.style_cfg.tag_cfg.tag_fields.layer_d_dst =
  459. port_tag_cfg.s.ip6_dprt_flag | port_tag_cfg.s.ip4_dprt_flag;
  460. pki_prt_cfg.style_cfg.tag_cfg.tag_fields.input_port = port_tag_cfg.s.inc_prt_flag;
  461. pki_prt_cfg.style_cfg.tag_cfg.tag_fields.first_vlan = port_tag_cfg.s.inc_vlan;
  462. pki_prt_cfg.style_cfg.tag_cfg.tag_fields.second_vlan = port_tag_cfg.s.inc_vs;
  463. if (port_tag_cfg.s.tcp6_tag_type == port_tag_cfg.s.tcp4_tag_type)
  464. tcp_tag = port_tag_cfg.s.tcp6_tag_type;
  465. if (port_tag_cfg.s.ip6_tag_type == port_tag_cfg.s.ip4_tag_type)
  466. ip_tag = port_tag_cfg.s.ip6_tag_type;
  467. pki_prt_cfg.style_cfg.parm_cfg.tag_type =
  468. (enum cvmx_sso_tag_type)port_tag_cfg.s.non_tag_type;
  469. if (tcp_tag == ip_tag && tcp_tag == port_tag_cfg.s.non_tag_type)
  470. pki_prt_cfg.style_cfg.parm_cfg.tag_type = (enum cvmx_sso_tag_type)tcp_tag;
  471. else if (tcp_tag == ip_tag) {
  472. /* allocate and copy style */
  473. /* modify tag type */
  474. /*pcam entry for ip6 && ip4 match*/
  475. /* default is non tag type */
  476. __cvmx_pip_set_tag_type(xp.node, style, ip_tag, CVMX_PKI_PCAM_MATCH_IP);
  477. } else if (ip_tag == port_tag_cfg.s.non_tag_type) {
  478. /* allocate and copy style */
  479. /* modify tag type */
  480. /*pcam entry for tcp6 & tcp4 match*/
  481. /* default is non tag type */
  482. __cvmx_pip_set_tag_type(xp.node, style, tcp_tag, CVMX_PKI_PCAM_MATCH_TCP);
  483. } else {
  484. if (ip_tag != 0xaa) {
  485. nstyle = __cvmx_pip_set_tag_type(xp.node, style, ip_tag,
  486. CVMX_PKI_PCAM_MATCH_IP);
  487. if (tcp_tag != 0xff)
  488. __cvmx_pip_set_tag_type(xp.node, nstyle, tcp_tag,
  489. CVMX_PKI_PCAM_MATCH_TCP);
  490. else {
  491. n4style = __cvmx_pip_set_tag_type(xp.node, nstyle, ip_tag,
  492. CVMX_PKI_PCAM_MATCH_IPV4);
  493. __cvmx_pip_set_tag_type(xp.node, n4style,
  494. port_tag_cfg.s.tcp4_tag_type,
  495. CVMX_PKI_PCAM_MATCH_TCP);
  496. n6style = __cvmx_pip_set_tag_type(xp.node, nstyle, ip_tag,
  497. CVMX_PKI_PCAM_MATCH_IPV6);
  498. __cvmx_pip_set_tag_type(xp.node, n6style,
  499. port_tag_cfg.s.tcp6_tag_type,
  500. CVMX_PKI_PCAM_MATCH_TCP);
  501. }
  502. } else {
  503. n4style = __cvmx_pip_set_tag_type(xp.node, style,
  504. port_tag_cfg.s.ip4_tag_type,
  505. CVMX_PKI_PCAM_MATCH_IPV4);
  506. n6style = __cvmx_pip_set_tag_type(xp.node, style,
  507. port_tag_cfg.s.ip6_tag_type,
  508. CVMX_PKI_PCAM_MATCH_IPV6);
  509. if (tcp_tag != 0xff) {
  510. __cvmx_pip_set_tag_type(xp.node, n4style, tcp_tag,
  511. CVMX_PKI_PCAM_MATCH_TCP);
  512. __cvmx_pip_set_tag_type(xp.node, n6style, tcp_tag,
  513. CVMX_PKI_PCAM_MATCH_TCP);
  514. } else {
  515. __cvmx_pip_set_tag_type(xp.node, n4style,
  516. port_tag_cfg.s.tcp4_tag_type,
  517. CVMX_PKI_PCAM_MATCH_TCP);
  518. __cvmx_pip_set_tag_type(xp.node, n6style,
  519. port_tag_cfg.s.tcp6_tag_type,
  520. CVMX_PKI_PCAM_MATCH_TCP);
  521. }
  522. }
  523. }
  524. pki_prt_cfg.style_cfg.parm_cfg.qpg_dis_padd = !port_tag_cfg.s.portadd_en;
  525. if (port_cfg.s.mode == 0x1)
  526. pki_prt_cfg.pkind_cfg.initial_parse_mode = CVMX_PKI_PARSE_LA_TO_LG;
  527. else if (port_cfg.s.mode == 0x2)
  528. pki_prt_cfg.pkind_cfg.initial_parse_mode = CVMX_PKI_PARSE_LC_TO_LG;
  529. else
  530. pki_prt_cfg.pkind_cfg.initial_parse_mode = CVMX_PKI_PARSE_NOTHING;
  531. /* This is only for backward compatibility, not all the parameters are supported in 78xx */
  532. cvmx_pki_set_port_config(ipd_port, &pki_prt_cfg);
  533. } else {
  534. if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
  535. int interface, index, pknd;
  536. interface = cvmx_helper_get_interface_num(ipd_port);
  537. index = cvmx_helper_get_interface_index_num(ipd_port);
  538. pknd = cvmx_helper_get_pknd(interface, index);
  539. ipd_port = pknd; /* overload port_num with pknd */
  540. }
  541. csr_wr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
  542. csr_wr(CVMX_PIP_PRT_TAGX(ipd_port), port_tag_cfg.u64);
  543. }
  544. }
  545. /**
  546. * Configure the VLAN priority to QoS queue mapping.
  547. *
  548. * @param vlan_priority
  549. * VLAN priority (0-7)
  550. * @param qos QoS queue for packets matching this watcher
  551. */
  552. static inline void cvmx_pip_config_vlan_qos(u64 vlan_priority, u64 qos)
  553. {
  554. if (!octeon_has_feature(OCTEON_FEATURE_PKND)) {
  555. cvmx_pip_qos_vlanx_t pip_qos_vlanx;
  556. pip_qos_vlanx.u64 = 0;
  557. pip_qos_vlanx.s.qos = qos;
  558. csr_wr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
  559. }
  560. }
  561. /**
  562. * Configure the Diffserv to QoS queue mapping.
  563. *
  564. * @param diffserv Diffserv field value (0-63)
  565. * @param qos QoS queue for packets matching this watcher
  566. */
  567. static inline void cvmx_pip_config_diffserv_qos(u64 diffserv, u64 qos)
  568. {
  569. if (!octeon_has_feature(OCTEON_FEATURE_PKND)) {
  570. cvmx_pip_qos_diffx_t pip_qos_diffx;
  571. pip_qos_diffx.u64 = 0;
  572. pip_qos_diffx.s.qos = qos;
  573. csr_wr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
  574. }
  575. }
  576. /**
  577. * Get the status counters for a port for older non PKI chips.
  578. *
  579. * @param port_num Port number (ipd_port) to get statistics for.
  580. * @param clear Set to 1 to clear the counters after they are read
  581. * @param status Where to put the results.
  582. */
  583. static inline void cvmx_pip_get_port_stats(u64 port_num, u64 clear, cvmx_pip_port_status_t *status)
  584. {
  585. cvmx_pip_stat_ctl_t pip_stat_ctl;
  586. cvmx_pip_stat0_prtx_t stat0;
  587. cvmx_pip_stat1_prtx_t stat1;
  588. cvmx_pip_stat2_prtx_t stat2;
  589. cvmx_pip_stat3_prtx_t stat3;
  590. cvmx_pip_stat4_prtx_t stat4;
  591. cvmx_pip_stat5_prtx_t stat5;
  592. cvmx_pip_stat6_prtx_t stat6;
  593. cvmx_pip_stat7_prtx_t stat7;
  594. cvmx_pip_stat8_prtx_t stat8;
  595. cvmx_pip_stat9_prtx_t stat9;
  596. cvmx_pip_stat10_x_t stat10;
  597. cvmx_pip_stat11_x_t stat11;
  598. cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx;
  599. cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx;
  600. cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx;
  601. int interface = cvmx_helper_get_interface_num(port_num);
  602. int index = cvmx_helper_get_interface_index_num(port_num);
  603. pip_stat_ctl.u64 = 0;
  604. pip_stat_ctl.s.rdclr = clear;
  605. csr_wr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
  606. if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
  607. int pknd = cvmx_helper_get_pknd(interface, index);
  608. /*
  609. * PIP_STAT_CTL[MODE] 0 means pkind.
  610. */
  611. stat0.u64 = csr_rd(CVMX_PIP_STAT0_X(pknd));
  612. stat1.u64 = csr_rd(CVMX_PIP_STAT1_X(pknd));
  613. stat2.u64 = csr_rd(CVMX_PIP_STAT2_X(pknd));
  614. stat3.u64 = csr_rd(CVMX_PIP_STAT3_X(pknd));
  615. stat4.u64 = csr_rd(CVMX_PIP_STAT4_X(pknd));
  616. stat5.u64 = csr_rd(CVMX_PIP_STAT5_X(pknd));
  617. stat6.u64 = csr_rd(CVMX_PIP_STAT6_X(pknd));
  618. stat7.u64 = csr_rd(CVMX_PIP_STAT7_X(pknd));
  619. stat8.u64 = csr_rd(CVMX_PIP_STAT8_X(pknd));
  620. stat9.u64 = csr_rd(CVMX_PIP_STAT9_X(pknd));
  621. stat10.u64 = csr_rd(CVMX_PIP_STAT10_X(pknd));
  622. stat11.u64 = csr_rd(CVMX_PIP_STAT11_X(pknd));
  623. } else {
  624. if (port_num >= 40) {
  625. stat0.u64 = csr_rd(CVMX_PIP_XSTAT0_PRTX(port_num));
  626. stat1.u64 = csr_rd(CVMX_PIP_XSTAT1_PRTX(port_num));
  627. stat2.u64 = csr_rd(CVMX_PIP_XSTAT2_PRTX(port_num));
  628. stat3.u64 = csr_rd(CVMX_PIP_XSTAT3_PRTX(port_num));
  629. stat4.u64 = csr_rd(CVMX_PIP_XSTAT4_PRTX(port_num));
  630. stat5.u64 = csr_rd(CVMX_PIP_XSTAT5_PRTX(port_num));
  631. stat6.u64 = csr_rd(CVMX_PIP_XSTAT6_PRTX(port_num));
  632. stat7.u64 = csr_rd(CVMX_PIP_XSTAT7_PRTX(port_num));
  633. stat8.u64 = csr_rd(CVMX_PIP_XSTAT8_PRTX(port_num));
  634. stat9.u64 = csr_rd(CVMX_PIP_XSTAT9_PRTX(port_num));
  635. if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
  636. stat10.u64 = csr_rd(CVMX_PIP_XSTAT10_PRTX(port_num));
  637. stat11.u64 = csr_rd(CVMX_PIP_XSTAT11_PRTX(port_num));
  638. }
  639. } else {
  640. stat0.u64 = csr_rd(CVMX_PIP_STAT0_PRTX(port_num));
  641. stat1.u64 = csr_rd(CVMX_PIP_STAT1_PRTX(port_num));
  642. stat2.u64 = csr_rd(CVMX_PIP_STAT2_PRTX(port_num));
  643. stat3.u64 = csr_rd(CVMX_PIP_STAT3_PRTX(port_num));
  644. stat4.u64 = csr_rd(CVMX_PIP_STAT4_PRTX(port_num));
  645. stat5.u64 = csr_rd(CVMX_PIP_STAT5_PRTX(port_num));
  646. stat6.u64 = csr_rd(CVMX_PIP_STAT6_PRTX(port_num));
  647. stat7.u64 = csr_rd(CVMX_PIP_STAT7_PRTX(port_num));
  648. stat8.u64 = csr_rd(CVMX_PIP_STAT8_PRTX(port_num));
  649. stat9.u64 = csr_rd(CVMX_PIP_STAT9_PRTX(port_num));
  650. if (OCTEON_IS_OCTEON2() || OCTEON_IS_MODEL(OCTEON_CN70XX)) {
  651. stat10.u64 = csr_rd(CVMX_PIP_STAT10_PRTX(port_num));
  652. stat11.u64 = csr_rd(CVMX_PIP_STAT11_PRTX(port_num));
  653. }
  654. }
  655. }
  656. if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
  657. int pknd = cvmx_helper_get_pknd(interface, index);
  658. pip_stat_inb_pktsx.u64 = csr_rd(CVMX_PIP_STAT_INB_PKTS_PKNDX(pknd));
  659. pip_stat_inb_octsx.u64 = csr_rd(CVMX_PIP_STAT_INB_OCTS_PKNDX(pknd));
  660. pip_stat_inb_errsx.u64 = csr_rd(CVMX_PIP_STAT_INB_ERRS_PKNDX(pknd));
  661. } else {
  662. pip_stat_inb_pktsx.u64 = csr_rd(CVMX_PIP_STAT_INB_PKTSX(port_num));
  663. pip_stat_inb_octsx.u64 = csr_rd(CVMX_PIP_STAT_INB_OCTSX(port_num));
  664. pip_stat_inb_errsx.u64 = csr_rd(CVMX_PIP_STAT_INB_ERRSX(port_num));
  665. }
  666. status->dropped_octets = stat0.s.drp_octs;
  667. status->dropped_packets = stat0.s.drp_pkts;
  668. status->octets = stat1.s.octs;
  669. status->pci_raw_packets = stat2.s.raw;
  670. status->packets = stat2.s.pkts;
  671. status->multicast_packets = stat3.s.mcst;
  672. status->broadcast_packets = stat3.s.bcst;
  673. status->len_64_packets = stat4.s.h64;
  674. status->len_65_127_packets = stat4.s.h65to127;
  675. status->len_128_255_packets = stat5.s.h128to255;
  676. status->len_256_511_packets = stat5.s.h256to511;
  677. status->len_512_1023_packets = stat6.s.h512to1023;
  678. status->len_1024_1518_packets = stat6.s.h1024to1518;
  679. status->len_1519_max_packets = stat7.s.h1519;
  680. status->fcs_align_err_packets = stat7.s.fcs;
  681. status->runt_packets = stat8.s.undersz;
  682. status->runt_crc_packets = stat8.s.frag;
  683. status->oversize_packets = stat9.s.oversz;
  684. status->oversize_crc_packets = stat9.s.jabber;
  685. if (OCTEON_IS_OCTEON2() || OCTEON_IS_MODEL(OCTEON_CN70XX)) {
  686. status->mcast_l2_red_packets = stat10.s.mcast;
  687. status->bcast_l2_red_packets = stat10.s.bcast;
  688. status->mcast_l3_red_packets = stat11.s.mcast;
  689. status->bcast_l3_red_packets = stat11.s.bcast;
  690. }
  691. status->inb_packets = pip_stat_inb_pktsx.s.pkts;
  692. status->inb_octets = pip_stat_inb_octsx.s.octs;
  693. status->inb_errors = pip_stat_inb_errsx.s.errs;
  694. }
  695. /**
  696. * Get the status counters for a port.
  697. *
  698. * @param port_num Port number (ipd_port) to get statistics for.
  699. * @param clear Set to 1 to clear the counters after they are read
  700. * @param status Where to put the results.
  701. */
  702. static inline void cvmx_pip_get_port_status(u64 port_num, u64 clear, cvmx_pip_port_status_t *status)
  703. {
  704. if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
  705. unsigned int node = cvmx_get_node_num();
  706. cvmx_pki_get_port_stats(node, port_num, (struct cvmx_pki_port_stats *)status);
  707. } else {
  708. cvmx_pip_get_port_stats(port_num, clear, status);
  709. }
  710. }
  711. /**
  712. * Configure the hardware CRC engine
  713. *
  714. * @param interface Interface to configure (0 or 1)
  715. * @param invert_result
  716. * Invert the result of the CRC
  717. * @param reflect Reflect
  718. * @param initialization_vector
  719. * CRC initialization vector
  720. */
  721. static inline void cvmx_pip_config_crc(u64 interface, u64 invert_result, u64 reflect,
  722. u32 initialization_vector)
  723. {
  724. /* Only CN38XX & CN58XX */
  725. }
  726. /**
  727. * Clear all bits in a tag mask. This should be called on
  728. * startup before any calls to cvmx_pip_tag_mask_set. Each bit
  729. * set in the final mask represent a byte used in the packet for
  730. * tag generation.
  731. *
  732. * @param mask_index Which tag mask to clear (0..3)
  733. */
  734. static inline void cvmx_pip_tag_mask_clear(u64 mask_index)
  735. {
  736. u64 index;
  737. cvmx_pip_tag_incx_t pip_tag_incx;
  738. pip_tag_incx.u64 = 0;
  739. pip_tag_incx.s.en = 0;
  740. for (index = mask_index * 16; index < (mask_index + 1) * 16; index++)
  741. csr_wr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
  742. }
  743. /**
  744. * Sets a range of bits in the tag mask. The tag mask is used
  745. * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
  746. * There are four separate masks that can be configured.
  747. *
  748. * @param mask_index Which tag mask to modify (0..3)
  749. * @param offset Offset into the bitmask to set bits at. Use the GCC macro
  750. * offsetof() to determine the offsets into packet headers.
  751. * For example, offsetof(ethhdr, protocol) returns the offset
  752. * of the ethernet protocol field. The bitmask selects which bytes
  753. * to include the the tag, with bit offset X selecting byte at offset X
  754. * from the beginning of the packet data.
  755. * @param len Number of bytes to include. Usually this is the sizeof()
  756. * the field.
  757. */
  758. static inline void cvmx_pip_tag_mask_set(u64 mask_index, u64 offset, u64 len)
  759. {
  760. while (len--) {
  761. cvmx_pip_tag_incx_t pip_tag_incx;
  762. u64 index = mask_index * 16 + offset / 8;
  763. pip_tag_incx.u64 = csr_rd(CVMX_PIP_TAG_INCX(index));
  764. pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
  765. csr_wr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
  766. offset++;
  767. }
  768. }
  769. /**
  770. * Set byte count for Max-Sized and Min Sized frame check.
  771. *
  772. * @param interface Which interface to set the limit
  773. * @param max_size Byte count for Max-Size frame check
  774. */
  775. static inline void cvmx_pip_set_frame_check(int interface, u32 max_size)
  776. {
  777. cvmx_pip_frm_len_chkx_t frm_len;
  778. /* max_size and min_size are passed as 0, reset to default values. */
  779. if (max_size < 1536)
  780. max_size = 1536;
  781. /* On CN68XX frame check is enabled for a pkind n and
  782. PIP_PRT_CFG[len_chk_sel] selects which set of
  783. MAXLEN/MINLEN to use. */
  784. if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
  785. int port;
  786. int num_ports = cvmx_helper_ports_on_interface(interface);
  787. for (port = 0; port < num_ports; port++) {
  788. if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
  789. int ipd_port;
  790. ipd_port = cvmx_helper_get_ipd_port(interface, port);
  791. cvmx_pki_set_max_frm_len(ipd_port, max_size);
  792. } else {
  793. int pknd;
  794. int sel;
  795. cvmx_pip_prt_cfgx_t config;
  796. pknd = cvmx_helper_get_pknd(interface, port);
  797. config.u64 = csr_rd(CVMX_PIP_PRT_CFGX(pknd));
  798. sel = config.s.len_chk_sel;
  799. frm_len.u64 = csr_rd(CVMX_PIP_FRM_LEN_CHKX(sel));
  800. frm_len.s.maxlen = max_size;
  801. csr_wr(CVMX_PIP_FRM_LEN_CHKX(sel), frm_len.u64);
  802. }
  803. }
  804. }
  805. /* on cn6xxx and cn7xxx models, PIP_FRM_LEN_CHK0 applies to
  806. * all incoming traffic */
  807. else if (OCTEON_IS_OCTEON2() || OCTEON_IS_MODEL(OCTEON_CN70XX)) {
  808. frm_len.u64 = csr_rd(CVMX_PIP_FRM_LEN_CHKX(0));
  809. frm_len.s.maxlen = max_size;
  810. csr_wr(CVMX_PIP_FRM_LEN_CHKX(0), frm_len.u64);
  811. }
  812. }
  813. /**
  814. * Initialize Bit Select Extractor config. Their are 8 bit positions and valids
  815. * to be used when using the corresponding extractor.
  816. *
  817. * @param bit Bit Select Extractor to use
  818. * @param pos Which position to update
  819. * @param val The value to update the position with
  820. */
  821. static inline void cvmx_pip_set_bsel_pos(int bit, int pos, int val)
  822. {
  823. cvmx_pip_bsel_ext_posx_t bsel_pos;
  824. /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
  825. if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
  826. return;
  827. if (bit < 0 || bit > 3) {
  828. debug("ERROR: cvmx_pip_set_bsel_pos: Invalid Bit-Select Extractor (%d) passed\n",
  829. bit);
  830. return;
  831. }
  832. bsel_pos.u64 = csr_rd(CVMX_PIP_BSEL_EXT_POSX(bit));
  833. switch (pos) {
  834. case 0:
  835. bsel_pos.s.pos0_val = 1;
  836. bsel_pos.s.pos0 = val & 0x7f;
  837. break;
  838. case 1:
  839. bsel_pos.s.pos1_val = 1;
  840. bsel_pos.s.pos1 = val & 0x7f;
  841. break;
  842. case 2:
  843. bsel_pos.s.pos2_val = 1;
  844. bsel_pos.s.pos2 = val & 0x7f;
  845. break;
  846. case 3:
  847. bsel_pos.s.pos3_val = 1;
  848. bsel_pos.s.pos3 = val & 0x7f;
  849. break;
  850. case 4:
  851. bsel_pos.s.pos4_val = 1;
  852. bsel_pos.s.pos4 = val & 0x7f;
  853. break;
  854. case 5:
  855. bsel_pos.s.pos5_val = 1;
  856. bsel_pos.s.pos5 = val & 0x7f;
  857. break;
  858. case 6:
  859. bsel_pos.s.pos6_val = 1;
  860. bsel_pos.s.pos6 = val & 0x7f;
  861. break;
  862. case 7:
  863. bsel_pos.s.pos7_val = 1;
  864. bsel_pos.s.pos7 = val & 0x7f;
  865. break;
  866. default:
  867. debug("Warning: cvmx_pip_set_bsel_pos: Invalid pos(%d)\n", pos);
  868. break;
  869. }
  870. csr_wr(CVMX_PIP_BSEL_EXT_POSX(bit), bsel_pos.u64);
  871. }
  872. /**
  873. * Initialize offset and skip values to use by bit select extractor.
  874. * @param bit Bit Select Extractor to use
  875. * @param offset Offset to add to extractor mem addr to get final address
  876. * to lookup table.
  877. * @param skip Number of bytes to skip from start of packet 0-64
  878. */
  879. static inline void cvmx_pip_bsel_config(int bit, int offset, int skip)
  880. {
  881. cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
  882. /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
  883. if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
  884. return;
  885. bsel_cfg.u64 = csr_rd(CVMX_PIP_BSEL_EXT_CFGX(bit));
  886. bsel_cfg.s.offset = offset;
  887. bsel_cfg.s.skip = skip;
  888. csr_wr(CVMX_PIP_BSEL_EXT_CFGX(bit), bsel_cfg.u64);
  889. }
  890. /**
  891. * Get the entry for the Bit Select Extractor Table.
  892. * @param work pointer to work queue entry
  893. * Return: Index of the Bit Select Extractor Table
  894. */
  895. static inline int cvmx_pip_get_bsel_table_index(cvmx_wqe_t *work)
  896. {
  897. int bit = cvmx_wqe_get_port(work) & 0x3;
  898. /* Get the Bit select table index. */
  899. int index;
  900. int y;
  901. cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
  902. cvmx_pip_bsel_ext_posx_t bsel_pos;
  903. /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
  904. if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
  905. return -1;
  906. bsel_cfg.u64 = csr_rd(CVMX_PIP_BSEL_EXT_CFGX(bit));
  907. bsel_pos.u64 = csr_rd(CVMX_PIP_BSEL_EXT_POSX(bit));
  908. for (y = 0; y < 8; y++) {
  909. char *ptr = (char *)cvmx_phys_to_ptr(work->packet_ptr.s.addr);
  910. int bit_loc = 0;
  911. int bit;
  912. ptr += bsel_cfg.s.skip;
  913. switch (y) {
  914. case 0:
  915. ptr += (bsel_pos.s.pos0 >> 3);
  916. bit_loc = 7 - (bsel_pos.s.pos0 & 0x3);
  917. break;
  918. case 1:
  919. ptr += (bsel_pos.s.pos1 >> 3);
  920. bit_loc = 7 - (bsel_pos.s.pos1 & 0x3);
  921. break;
  922. case 2:
  923. ptr += (bsel_pos.s.pos2 >> 3);
  924. bit_loc = 7 - (bsel_pos.s.pos2 & 0x3);
  925. break;
  926. case 3:
  927. ptr += (bsel_pos.s.pos3 >> 3);
  928. bit_loc = 7 - (bsel_pos.s.pos3 & 0x3);
  929. break;
  930. case 4:
  931. ptr += (bsel_pos.s.pos4 >> 3);
  932. bit_loc = 7 - (bsel_pos.s.pos4 & 0x3);
  933. break;
  934. case 5:
  935. ptr += (bsel_pos.s.pos5 >> 3);
  936. bit_loc = 7 - (bsel_pos.s.pos5 & 0x3);
  937. break;
  938. case 6:
  939. ptr += (bsel_pos.s.pos6 >> 3);
  940. bit_loc = 7 - (bsel_pos.s.pos6 & 0x3);
  941. break;
  942. case 7:
  943. ptr += (bsel_pos.s.pos7 >> 3);
  944. bit_loc = 7 - (bsel_pos.s.pos7 & 0x3);
  945. break;
  946. }
  947. bit = (*ptr >> bit_loc) & 1;
  948. index |= bit << y;
  949. }
  950. index += bsel_cfg.s.offset;
  951. index &= 0x1ff;
  952. return index;
  953. }
  954. static inline int cvmx_pip_get_bsel_qos(cvmx_wqe_t *work)
  955. {
  956. int index = cvmx_pip_get_bsel_table_index(work);
  957. cvmx_pip_bsel_tbl_entx_t bsel_tbl;
  958. /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
  959. if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
  960. return -1;
  961. bsel_tbl.u64 = csr_rd(CVMX_PIP_BSEL_TBL_ENTX(index));
  962. return bsel_tbl.s.qos;
  963. }
  964. static inline int cvmx_pip_get_bsel_grp(cvmx_wqe_t *work)
  965. {
  966. int index = cvmx_pip_get_bsel_table_index(work);
  967. cvmx_pip_bsel_tbl_entx_t bsel_tbl;
  968. /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
  969. if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
  970. return -1;
  971. bsel_tbl.u64 = csr_rd(CVMX_PIP_BSEL_TBL_ENTX(index));
  972. return bsel_tbl.s.grp;
  973. }
  974. static inline int cvmx_pip_get_bsel_tt(cvmx_wqe_t *work)
  975. {
  976. int index = cvmx_pip_get_bsel_table_index(work);
  977. cvmx_pip_bsel_tbl_entx_t bsel_tbl;
  978. /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
  979. if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
  980. return -1;
  981. bsel_tbl.u64 = csr_rd(CVMX_PIP_BSEL_TBL_ENTX(index));
  982. return bsel_tbl.s.tt;
  983. }
  984. static inline int cvmx_pip_get_bsel_tag(cvmx_wqe_t *work)
  985. {
  986. int index = cvmx_pip_get_bsel_table_index(work);
  987. int port = cvmx_wqe_get_port(work);
  988. int bit = port & 0x3;
  989. int upper_tag = 0;
  990. cvmx_pip_bsel_tbl_entx_t bsel_tbl;
  991. cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
  992. cvmx_pip_prt_tagx_t prt_tag;
  993. /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
  994. if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
  995. return -1;
  996. bsel_tbl.u64 = csr_rd(CVMX_PIP_BSEL_TBL_ENTX(index));
  997. bsel_cfg.u64 = csr_rd(CVMX_PIP_BSEL_EXT_CFGX(bit));
  998. prt_tag.u64 = csr_rd(CVMX_PIP_PRT_TAGX(port));
  999. if (prt_tag.s.inc_prt_flag == 0)
  1000. upper_tag = bsel_cfg.s.upper_tag;
  1001. return bsel_tbl.s.tag | ((bsel_cfg.s.tag << 8) & 0xff00) | ((upper_tag << 16) & 0xffff0000);
  1002. }
  1003. #endif /* __CVMX_PIP_H__ */