cvmx-pcie.h 7.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. */
  5. #ifndef __CVMX_PCIE_H__
  6. #define __CVMX_PCIE_H__
  7. #define CVMX_PCIE_MAX_PORTS 4
  8. #define CVMX_PCIE_PORTS \
  9. ((OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX)) ? \
  10. CVMX_PCIE_MAX_PORTS : \
  11. (OCTEON_IS_MODEL(OCTEON_CN70XX) ? 3 : 2))
  12. /*
  13. * The physical memory base mapped by BAR1. 256MB at the end of the
  14. * first 4GB.
  15. */
  16. #define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
  17. #define CVMX_PCIE_BAR1_PHYS_SIZE BIT_ULL(28)
  18. /*
  19. * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
  20. * place BAR1 so it is the same for both.
  21. */
  22. #define CVMX_PCIE_BAR1_RC_BASE BIT_ULL(41)
  23. typedef union {
  24. u64 u64;
  25. struct {
  26. u64 upper : 2; /* Normally 2 for XKPHYS */
  27. u64 reserved_49_61 : 13; /* Must be zero */
  28. u64 io : 1; /* 1 for IO space access */
  29. u64 did : 5; /* PCIe DID = 3 */
  30. u64 subdid : 3; /* PCIe SubDID = 1 */
  31. u64 reserved_38_39 : 2; /* Must be zero */
  32. u64 node : 2; /* Numa node number */
  33. u64 es : 2; /* Endian swap = 1 */
  34. u64 port : 2; /* PCIe port 0,1 */
  35. u64 reserved_29_31 : 3; /* Must be zero */
  36. u64 ty : 1;
  37. u64 bus : 8;
  38. u64 dev : 5;
  39. u64 func : 3;
  40. u64 reg : 12;
  41. } config;
  42. struct {
  43. u64 upper : 2; /* Normally 2 for XKPHYS */
  44. u64 reserved_49_61 : 13; /* Must be zero */
  45. u64 io : 1; /* 1 for IO space access */
  46. u64 did : 5; /* PCIe DID = 3 */
  47. u64 subdid : 3; /* PCIe SubDID = 2 */
  48. u64 reserved_38_39 : 2; /* Must be zero */
  49. u64 node : 2; /* Numa node number */
  50. u64 es : 2; /* Endian swap = 1 */
  51. u64 port : 2; /* PCIe port 0,1 */
  52. u64 address : 32; /* PCIe IO address */
  53. } io;
  54. struct {
  55. u64 upper : 2; /* Normally 2 for XKPHYS */
  56. u64 reserved_49_61 : 13; /* Must be zero */
  57. u64 io : 1; /* 1 for IO space access */
  58. u64 did : 5; /* PCIe DID = 3 */
  59. u64 subdid : 3; /* PCIe SubDID = 3-6 */
  60. u64 reserved_38_39 : 2; /* Must be zero */
  61. u64 node : 2; /* Numa node number */
  62. u64 address : 36; /* PCIe Mem address */
  63. } mem;
  64. } cvmx_pcie_address_t;
  65. /**
  66. * Return the Core virtual base address for PCIe IO access. IOs are
  67. * read/written as an offset from this address.
  68. *
  69. * @param pcie_port PCIe port the IO is for
  70. *
  71. * Return: 64bit Octeon IO base address for read/write
  72. */
  73. u64 cvmx_pcie_get_io_base_address(int pcie_port);
  74. /**
  75. * Size of the IO address region returned at address
  76. * cvmx_pcie_get_io_base_address()
  77. *
  78. * @param pcie_port PCIe port the IO is for
  79. *
  80. * Return: Size of the IO window
  81. */
  82. u64 cvmx_pcie_get_io_size(int pcie_port);
  83. /**
  84. * Return the Core virtual base address for PCIe MEM access. Memory is
  85. * read/written as an offset from this address.
  86. *
  87. * @param pcie_port PCIe port the IO is for
  88. *
  89. * Return: 64bit Octeon IO base address for read/write
  90. */
  91. u64 cvmx_pcie_get_mem_base_address(int pcie_port);
  92. /**
  93. * Size of the Mem address region returned at address
  94. * cvmx_pcie_get_mem_base_address()
  95. *
  96. * @param pcie_port PCIe port the IO is for
  97. *
  98. * Return: Size of the Mem window
  99. */
  100. u64 cvmx_pcie_get_mem_size(int pcie_port);
  101. /**
  102. * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
  103. *
  104. * @param pcie_port PCIe port to initialize
  105. *
  106. * Return: Zero on success
  107. */
  108. int cvmx_pcie_rc_initialize(int pcie_port);
  109. /**
  110. * Shutdown a PCIe port and put it in reset
  111. *
  112. * @param pcie_port PCIe port to shutdown
  113. *
  114. * Return: Zero on success
  115. */
  116. int cvmx_pcie_rc_shutdown(int pcie_port);
  117. /**
  118. * Read 8bits from a Device's config space
  119. *
  120. * @param pcie_port PCIe port the device is on
  121. * @param bus Sub bus
  122. * @param dev Device ID
  123. * @param fn Device sub function
  124. * @param reg Register to access
  125. *
  126. * Return: Result of the read
  127. */
  128. u8 cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg);
  129. /**
  130. * Read 16bits from a Device's config space
  131. *
  132. * @param pcie_port PCIe port the device is on
  133. * @param bus Sub bus
  134. * @param dev Device ID
  135. * @param fn Device sub function
  136. * @param reg Register to access
  137. *
  138. * Return: Result of the read
  139. */
  140. u16 cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg);
  141. /**
  142. * Read 32bits from a Device's config space
  143. *
  144. * @param pcie_port PCIe port the device is on
  145. * @param bus Sub bus
  146. * @param dev Device ID
  147. * @param fn Device sub function
  148. * @param reg Register to access
  149. *
  150. * Return: Result of the read
  151. */
  152. u32 cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg);
  153. /**
  154. * Write 8bits to a Device's config space
  155. *
  156. * @param pcie_port PCIe port the device is on
  157. * @param bus Sub bus
  158. * @param dev Device ID
  159. * @param fn Device sub function
  160. * @param reg Register to access
  161. * @param val Value to write
  162. */
  163. void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, u8 val);
  164. /**
  165. * Write 16bits to a Device's config space
  166. *
  167. * @param pcie_port PCIe port the device is on
  168. * @param bus Sub bus
  169. * @param dev Device ID
  170. * @param fn Device sub function
  171. * @param reg Register to access
  172. * @param val Value to write
  173. */
  174. void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, u16 val);
  175. /**
  176. * Write 32bits to a Device's config space
  177. *
  178. * @param pcie_port PCIe port the device is on
  179. * @param bus Sub bus
  180. * @param dev Device ID
  181. * @param fn Device sub function
  182. * @param reg Register to access
  183. * @param val Value to write
  184. */
  185. void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, u32 val);
  186. /**
  187. * Read a PCIe config space register indirectly. This is used for
  188. * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  189. *
  190. * @param pcie_port PCIe port to read from
  191. * @param cfg_offset Address to read
  192. *
  193. * Return: Value read
  194. */
  195. u32 cvmx_pcie_cfgx_read(int pcie_port, u32 cfg_offset);
  196. u32 cvmx_pcie_cfgx_read_node(int node, int pcie_port, u32 cfg_offset);
  197. /**
  198. * Write a PCIe config space register indirectly. This is used for
  199. * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  200. *
  201. * @param pcie_port PCIe port to write to
  202. * @param cfg_offset Address to write
  203. * @param val Value to write
  204. */
  205. void cvmx_pcie_cfgx_write(int pcie_port, u32 cfg_offset, u32 val);
  206. void cvmx_pcie_cfgx_write_node(int node, int pcie_port, u32 cfg_offset, u32 val);
  207. /**
  208. * Write a 32bit value to the Octeon NPEI register space
  209. *
  210. * @param address Address to write to
  211. * @param val Value to write
  212. */
  213. static inline void cvmx_pcie_npei_write32(u64 address, u32 val)
  214. {
  215. cvmx_write64_uint32(address ^ 4, val);
  216. cvmx_read64_uint32(address ^ 4);
  217. }
  218. /**
  219. * Read a 32bit value from the Octeon NPEI register space
  220. *
  221. * @param address Address to read
  222. * Return: The result
  223. */
  224. static inline u32 cvmx_pcie_npei_read32(u64 address)
  225. {
  226. return cvmx_read64_uint32(address ^ 4);
  227. }
  228. /**
  229. * Initialize a PCIe port for use in target(EP) mode.
  230. *
  231. * @param pcie_port PCIe port to initialize
  232. *
  233. * Return: Zero on success
  234. */
  235. int cvmx_pcie_ep_initialize(int pcie_port);
  236. /**
  237. * Wait for posted PCIe read/writes to reach the other side of
  238. * the internal PCIe switch. This will insure that core
  239. * read/writes are posted before anything after this function
  240. * is called. This may be necessary when writing to memory that
  241. * will later be read using the DMA/PKT engines.
  242. *
  243. * @param pcie_port PCIe port to wait for
  244. */
  245. void cvmx_pcie_wait_for_pending(int pcie_port);
  246. /**
  247. * Returns if a PCIe port is in host or target mode.
  248. *
  249. * @param pcie_port PCIe port number (PEM number)
  250. *
  251. * Return: 0 if PCIe port is in target mode, !0 if in host mode.
  252. */
  253. int cvmx_pcie_is_host_mode(int pcie_port);
  254. #endif