cvmx-hwfau.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. *
  5. * Interface to the hardware Fetch and Add Unit.
  6. */
  7. /**
  8. * @file
  9. *
  10. * Interface to the hardware Fetch and Add Unit.
  11. *
  12. */
  13. #ifndef __CVMX_HWFAU_H__
  14. #define __CVMX_HWFAU_H__
  15. typedef int cvmx_fau_reg64_t;
  16. typedef int cvmx_fau_reg32_t;
  17. typedef int cvmx_fau_reg16_t;
  18. typedef int cvmx_fau_reg8_t;
  19. #define CVMX_FAU_REG_ANY -1
  20. /*
  21. * Octeon Fetch and Add Unit (FAU)
  22. */
  23. #define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0)
  24. #define CVMX_FAU_BITS_SCRADDR 63, 56
  25. #define CVMX_FAU_BITS_LEN 55, 48
  26. #define CVMX_FAU_BITS_INEVAL 35, 14
  27. #define CVMX_FAU_BITS_TAGWAIT 13, 13
  28. #define CVMX_FAU_BITS_NOADD 13, 13
  29. #define CVMX_FAU_BITS_SIZE 12, 11
  30. #define CVMX_FAU_BITS_REGISTER 10, 0
  31. #define CVMX_FAU_MAX_REGISTERS_8 (2048)
  32. typedef enum {
  33. CVMX_FAU_OP_SIZE_8 = 0,
  34. CVMX_FAU_OP_SIZE_16 = 1,
  35. CVMX_FAU_OP_SIZE_32 = 2,
  36. CVMX_FAU_OP_SIZE_64 = 3
  37. } cvmx_fau_op_size_t;
  38. /**
  39. * Tagwait return definition. If a timeout occurs, the error
  40. * bit will be set. Otherwise the value of the register before
  41. * the update will be returned.
  42. */
  43. typedef struct {
  44. u64 error : 1;
  45. s64 value : 63;
  46. } cvmx_fau_tagwait64_t;
  47. /**
  48. * Tagwait return definition. If a timeout occurs, the error
  49. * bit will be set. Otherwise the value of the register before
  50. * the update will be returned.
  51. */
  52. typedef struct {
  53. u64 error : 1;
  54. s32 value : 31;
  55. } cvmx_fau_tagwait32_t;
  56. /**
  57. * Tagwait return definition. If a timeout occurs, the error
  58. * bit will be set. Otherwise the value of the register before
  59. * the update will be returned.
  60. */
  61. typedef struct {
  62. u64 error : 1;
  63. s16 value : 15;
  64. } cvmx_fau_tagwait16_t;
  65. /**
  66. * Tagwait return definition. If a timeout occurs, the error
  67. * bit will be set. Otherwise the value of the register before
  68. * the update will be returned.
  69. */
  70. typedef struct {
  71. u64 error : 1;
  72. int8_t value : 7;
  73. } cvmx_fau_tagwait8_t;
  74. /**
  75. * Asynchronous tagwait return definition. If a timeout occurs,
  76. * the error bit will be set. Otherwise the value of the
  77. * register before the update will be returned.
  78. */
  79. typedef union {
  80. u64 u64;
  81. struct {
  82. u64 invalid : 1;
  83. u64 data : 63; /* unpredictable if invalid is set */
  84. } s;
  85. } cvmx_fau_async_tagwait_result_t;
  86. #define SWIZZLE_8 0
  87. #define SWIZZLE_16 0
  88. #define SWIZZLE_32 0
  89. /**
  90. * @INTERNAL
  91. * Builds a store I/O address for writing to the FAU
  92. *
  93. * @param noadd 0 = Store value is atomically added to the current value
  94. * 1 = Store value is atomically written over the current value
  95. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  96. * - Step by 2 for 16 bit access.
  97. * - Step by 4 for 32 bit access.
  98. * - Step by 8 for 64 bit access.
  99. * Return: Address to store for atomic update
  100. */
  101. static inline u64 __cvmx_hwfau_store_address(u64 noadd, u64 reg)
  102. {
  103. return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
  104. cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
  105. cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
  106. }
  107. /**
  108. * @INTERNAL
  109. * Builds a I/O address for accessing the FAU
  110. *
  111. * @param tagwait Should the atomic add wait for the current tag switch
  112. * operation to complete.
  113. * - 0 = Don't wait
  114. * - 1 = Wait for tag switch to complete
  115. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  116. * - Step by 2 for 16 bit access.
  117. * - Step by 4 for 32 bit access.
  118. * - Step by 8 for 64 bit access.
  119. * @param value Signed value to add.
  120. * Note: When performing 32 and 64 bit access, only the low
  121. * 22 bits are available.
  122. * Return: Address to read from for atomic update
  123. */
  124. static inline u64 __cvmx_hwfau_atomic_address(u64 tagwait, u64 reg, s64 value)
  125. {
  126. return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
  127. cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
  128. cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
  129. cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
  130. }
  131. /**
  132. * Perform an atomic 64 bit add
  133. *
  134. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  135. * - Step by 8 for 64 bit access.
  136. * @param value Signed value to add.
  137. * Note: Only the low 22 bits are available.
  138. * Return: Value of the register before the update
  139. */
  140. static inline s64 cvmx_hwfau_fetch_and_add64(cvmx_fau_reg64_t reg, s64 value)
  141. {
  142. return cvmx_read64_int64(__cvmx_hwfau_atomic_address(0, reg, value));
  143. }
  144. /**
  145. * Perform an atomic 32 bit add
  146. *
  147. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  148. * - Step by 4 for 32 bit access.
  149. * @param value Signed value to add.
  150. * Note: Only the low 22 bits are available.
  151. * Return: Value of the register before the update
  152. */
  153. static inline s32 cvmx_hwfau_fetch_and_add32(cvmx_fau_reg32_t reg, s32 value)
  154. {
  155. reg ^= SWIZZLE_32;
  156. return cvmx_read64_int32(__cvmx_hwfau_atomic_address(0, reg, value));
  157. }
  158. /**
  159. * Perform an atomic 16 bit add
  160. *
  161. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  162. * - Step by 2 for 16 bit access.
  163. * @param value Signed value to add.
  164. * Return: Value of the register before the update
  165. */
  166. static inline s16 cvmx_hwfau_fetch_and_add16(cvmx_fau_reg16_t reg, s16 value)
  167. {
  168. reg ^= SWIZZLE_16;
  169. return cvmx_read64_int16(__cvmx_hwfau_atomic_address(0, reg, value));
  170. }
  171. /**
  172. * Perform an atomic 8 bit add
  173. *
  174. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  175. * @param value Signed value to add.
  176. * Return: Value of the register before the update
  177. */
  178. static inline int8_t cvmx_hwfau_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value)
  179. {
  180. reg ^= SWIZZLE_8;
  181. return cvmx_read64_int8(__cvmx_hwfau_atomic_address(0, reg, value));
  182. }
  183. /**
  184. * Perform an atomic 64 bit add after the current tag switch
  185. * completes
  186. *
  187. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  188. * - Step by 8 for 64 bit access.
  189. * @param value Signed value to add.
  190. * Note: Only the low 22 bits are available.
  191. * Return: If a timeout occurs, the error bit will be set. Otherwise
  192. * the value of the register before the update will be
  193. * returned
  194. */
  195. static inline cvmx_fau_tagwait64_t cvmx_hwfau_tagwait_fetch_and_add64(cvmx_fau_reg64_t reg,
  196. s64 value)
  197. {
  198. union {
  199. u64 i64;
  200. cvmx_fau_tagwait64_t t;
  201. } result;
  202. result.i64 = cvmx_read64_int64(__cvmx_hwfau_atomic_address(1, reg, value));
  203. return result.t;
  204. }
  205. /**
  206. * Perform an atomic 32 bit add after the current tag switch
  207. * completes
  208. *
  209. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  210. * - Step by 4 for 32 bit access.
  211. * @param value Signed value to add.
  212. * Note: Only the low 22 bits are available.
  213. * Return: If a timeout occurs, the error bit will be set. Otherwise
  214. * the value of the register before the update will be
  215. * returned
  216. */
  217. static inline cvmx_fau_tagwait32_t cvmx_hwfau_tagwait_fetch_and_add32(cvmx_fau_reg32_t reg,
  218. s32 value)
  219. {
  220. union {
  221. u64 i32;
  222. cvmx_fau_tagwait32_t t;
  223. } result;
  224. reg ^= SWIZZLE_32;
  225. result.i32 = cvmx_read64_int32(__cvmx_hwfau_atomic_address(1, reg, value));
  226. return result.t;
  227. }
  228. /**
  229. * Perform an atomic 16 bit add after the current tag switch
  230. * completes
  231. *
  232. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  233. * - Step by 2 for 16 bit access.
  234. * @param value Signed value to add.
  235. * Return: If a timeout occurs, the error bit will be set. Otherwise
  236. * the value of the register before the update will be
  237. * returned
  238. */
  239. static inline cvmx_fau_tagwait16_t cvmx_hwfau_tagwait_fetch_and_add16(cvmx_fau_reg16_t reg,
  240. s16 value)
  241. {
  242. union {
  243. u64 i16;
  244. cvmx_fau_tagwait16_t t;
  245. } result;
  246. reg ^= SWIZZLE_16;
  247. result.i16 = cvmx_read64_int16(__cvmx_hwfau_atomic_address(1, reg, value));
  248. return result.t;
  249. }
  250. /**
  251. * Perform an atomic 8 bit add after the current tag switch
  252. * completes
  253. *
  254. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  255. * @param value Signed value to add.
  256. * Return: If a timeout occurs, the error bit will be set. Otherwise
  257. * the value of the register before the update will be
  258. * returned
  259. */
  260. static inline cvmx_fau_tagwait8_t cvmx_hwfau_tagwait_fetch_and_add8(cvmx_fau_reg8_t reg,
  261. int8_t value)
  262. {
  263. union {
  264. u64 i8;
  265. cvmx_fau_tagwait8_t t;
  266. } result;
  267. reg ^= SWIZZLE_8;
  268. result.i8 = cvmx_read64_int8(__cvmx_hwfau_atomic_address(1, reg, value));
  269. return result.t;
  270. }
  271. /**
  272. * @INTERNAL
  273. * Builds I/O data for async operations
  274. *
  275. * @param scraddr Scratch pad byte address to write to. Must be 8 byte aligned
  276. * @param value Signed value to add.
  277. * Note: When performing 32 and 64 bit access, only the low
  278. * 22 bits are available.
  279. * @param tagwait Should the atomic add wait for the current tag switch
  280. * operation to complete.
  281. * - 0 = Don't wait
  282. * - 1 = Wait for tag switch to complete
  283. * @param size The size of the operation:
  284. * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits
  285. * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
  286. * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
  287. * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
  288. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  289. * - Step by 2 for 16 bit access.
  290. * - Step by 4 for 32 bit access.
  291. * - Step by 8 for 64 bit access.
  292. * Return: Data to write using cvmx_send_single
  293. */
  294. static inline u64 __cvmx_fau_iobdma_data(u64 scraddr, s64 value, u64 tagwait,
  295. cvmx_fau_op_size_t size, u64 reg)
  296. {
  297. return (CVMX_FAU_LOAD_IO_ADDRESS | cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) |
  298. cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
  299. cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
  300. cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
  301. cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
  302. cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
  303. }
  304. /**
  305. * Perform an async atomic 64 bit add. The old value is
  306. * placed in the scratch memory at byte address scraddr.
  307. *
  308. * @param scraddr Scratch memory byte address to put response in.
  309. * Must be 8 byte aligned.
  310. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  311. * - Step by 8 for 64 bit access.
  312. * @param value Signed value to add.
  313. * Note: Only the low 22 bits are available.
  314. * Return: Placed in the scratch pad register
  315. */
  316. static inline void cvmx_hwfau_async_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg, s64 value)
  317. {
  318. cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
  319. }
  320. /**
  321. * Perform an async atomic 32 bit add. The old value is
  322. * placed in the scratch memory at byte address scraddr.
  323. *
  324. * @param scraddr Scratch memory byte address to put response in.
  325. * Must be 8 byte aligned.
  326. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  327. * - Step by 4 for 32 bit access.
  328. * @param value Signed value to add.
  329. * Note: Only the low 22 bits are available.
  330. * Return: Placed in the scratch pad register
  331. */
  332. static inline void cvmx_hwfau_async_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg, s32 value)
  333. {
  334. cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
  335. }
  336. /**
  337. * Perform an async atomic 16 bit add. The old value is
  338. * placed in the scratch memory at byte address scraddr.
  339. *
  340. * @param scraddr Scratch memory byte address to put response in.
  341. * Must be 8 byte aligned.
  342. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  343. * - Step by 2 for 16 bit access.
  344. * @param value Signed value to add.
  345. * Return: Placed in the scratch pad register
  346. */
  347. static inline void cvmx_hwfau_async_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg, s16 value)
  348. {
  349. cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
  350. }
  351. /**
  352. * Perform an async atomic 8 bit add. The old value is
  353. * placed in the scratch memory at byte address scraddr.
  354. *
  355. * @param scraddr Scratch memory byte address to put response in.
  356. * Must be 8 byte aligned.
  357. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  358. * @param value Signed value to add.
  359. * Return: Placed in the scratch pad register
  360. */
  361. static inline void cvmx_hwfau_async_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg, int8_t value)
  362. {
  363. cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
  364. }
  365. /**
  366. * Perform an async atomic 64 bit add after the current tag
  367. * switch completes.
  368. *
  369. * @param scraddr Scratch memory byte address to put response in.
  370. * Must be 8 byte aligned.
  371. * If a timeout occurs, the error bit (63) will be set. Otherwise
  372. * the value of the register before the update will be
  373. * returned
  374. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  375. * - Step by 8 for 64 bit access.
  376. * @param value Signed value to add.
  377. * Note: Only the low 22 bits are available.
  378. * Return: Placed in the scratch pad register
  379. */
  380. static inline void cvmx_hwfau_async_tagwait_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg,
  381. s64 value)
  382. {
  383. cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
  384. }
  385. /**
  386. * Perform an async atomic 32 bit add after the current tag
  387. * switch completes.
  388. *
  389. * @param scraddr Scratch memory byte address to put response in.
  390. * Must be 8 byte aligned.
  391. * If a timeout occurs, the error bit (63) will be set. Otherwise
  392. * the value of the register before the update will be
  393. * returned
  394. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  395. * - Step by 4 for 32 bit access.
  396. * @param value Signed value to add.
  397. * Note: Only the low 22 bits are available.
  398. * Return: Placed in the scratch pad register
  399. */
  400. static inline void cvmx_hwfau_async_tagwait_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg,
  401. s32 value)
  402. {
  403. cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
  404. }
  405. /**
  406. * Perform an async atomic 16 bit add after the current tag
  407. * switch completes.
  408. *
  409. * @param scraddr Scratch memory byte address to put response in.
  410. * Must be 8 byte aligned.
  411. * If a timeout occurs, the error bit (63) will be set. Otherwise
  412. * the value of the register before the update will be
  413. * returned
  414. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  415. * - Step by 2 for 16 bit access.
  416. * @param value Signed value to add.
  417. * Return: Placed in the scratch pad register
  418. */
  419. static inline void cvmx_hwfau_async_tagwait_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg,
  420. s16 value)
  421. {
  422. cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
  423. }
  424. /**
  425. * Perform an async atomic 8 bit add after the current tag
  426. * switch completes.
  427. *
  428. * @param scraddr Scratch memory byte address to put response in.
  429. * Must be 8 byte aligned.
  430. * If a timeout occurs, the error bit (63) will be set. Otherwise
  431. * the value of the register before the update will be
  432. * returned
  433. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  434. * @param value Signed value to add.
  435. * Return: Placed in the scratch pad register
  436. */
  437. static inline void cvmx_hwfau_async_tagwait_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg,
  438. int8_t value)
  439. {
  440. cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
  441. }
  442. /**
  443. * Perform an atomic 64 bit add
  444. *
  445. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  446. * - Step by 8 for 64 bit access.
  447. * @param value Signed value to add.
  448. */
  449. static inline void cvmx_hwfau_atomic_add64(cvmx_fau_reg64_t reg, s64 value)
  450. {
  451. cvmx_write64_int64(__cvmx_hwfau_store_address(0, reg), value);
  452. }
  453. /**
  454. * Perform an atomic 32 bit add
  455. *
  456. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  457. * - Step by 4 for 32 bit access.
  458. * @param value Signed value to add.
  459. */
  460. static inline void cvmx_hwfau_atomic_add32(cvmx_fau_reg32_t reg, s32 value)
  461. {
  462. reg ^= SWIZZLE_32;
  463. cvmx_write64_int32(__cvmx_hwfau_store_address(0, reg), value);
  464. }
  465. /**
  466. * Perform an atomic 16 bit add
  467. *
  468. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  469. * - Step by 2 for 16 bit access.
  470. * @param value Signed value to add.
  471. */
  472. static inline void cvmx_hwfau_atomic_add16(cvmx_fau_reg16_t reg, s16 value)
  473. {
  474. reg ^= SWIZZLE_16;
  475. cvmx_write64_int16(__cvmx_hwfau_store_address(0, reg), value);
  476. }
  477. /**
  478. * Perform an atomic 8 bit add
  479. *
  480. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  481. * @param value Signed value to add.
  482. */
  483. static inline void cvmx_hwfau_atomic_add8(cvmx_fau_reg8_t reg, int8_t value)
  484. {
  485. reg ^= SWIZZLE_8;
  486. cvmx_write64_int8(__cvmx_hwfau_store_address(0, reg), value);
  487. }
  488. /**
  489. * Perform an atomic 64 bit write
  490. *
  491. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  492. * - Step by 8 for 64 bit access.
  493. * @param value Signed value to write.
  494. */
  495. static inline void cvmx_hwfau_atomic_write64(cvmx_fau_reg64_t reg, s64 value)
  496. {
  497. cvmx_write64_int64(__cvmx_hwfau_store_address(1, reg), value);
  498. }
  499. /**
  500. * Perform an atomic 32 bit write
  501. *
  502. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  503. * - Step by 4 for 32 bit access.
  504. * @param value Signed value to write.
  505. */
  506. static inline void cvmx_hwfau_atomic_write32(cvmx_fau_reg32_t reg, s32 value)
  507. {
  508. reg ^= SWIZZLE_32;
  509. cvmx_write64_int32(__cvmx_hwfau_store_address(1, reg), value);
  510. }
  511. /**
  512. * Perform an atomic 16 bit write
  513. *
  514. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  515. * - Step by 2 for 16 bit access.
  516. * @param value Signed value to write.
  517. */
  518. static inline void cvmx_hwfau_atomic_write16(cvmx_fau_reg16_t reg, s16 value)
  519. {
  520. reg ^= SWIZZLE_16;
  521. cvmx_write64_int16(__cvmx_hwfau_store_address(1, reg), value);
  522. }
  523. /**
  524. * Perform an atomic 8 bit write
  525. *
  526. * @param reg FAU atomic register to access. 0 <= reg < 2048.
  527. * @param value Signed value to write.
  528. */
  529. static inline void cvmx_hwfau_atomic_write8(cvmx_fau_reg8_t reg, int8_t value)
  530. {
  531. reg ^= SWIZZLE_8;
  532. cvmx_write64_int8(__cvmx_hwfau_store_address(1, reg), value);
  533. }
  534. /** Allocates 64bit FAU register.
  535. * Return: value is the base address of allocated FAU register
  536. */
  537. int cvmx_fau64_alloc(int reserve);
  538. /** Allocates 32bit FAU register.
  539. * Return: value is the base address of allocated FAU register
  540. */
  541. int cvmx_fau32_alloc(int reserve);
  542. /** Allocates 16bit FAU register.
  543. * Return: value is the base address of allocated FAU register
  544. */
  545. int cvmx_fau16_alloc(int reserve);
  546. /** Allocates 8bit FAU register.
  547. * Return: value is the base address of allocated FAU register
  548. */
  549. int cvmx_fau8_alloc(int reserve);
  550. /** Frees the specified FAU register.
  551. * @param address Base address of register to release.
  552. * Return: 0 on success; -1 on failure
  553. */
  554. int cvmx_fau_free(int address);
  555. /** Display the fau registers array
  556. */
  557. void cvmx_fau_show(void);
  558. #endif /* __CVMX_HWFAU_H__ */