cvmx-pcie.c 75 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. *
  5. * Interface to PCIe as a host(RC) or target(EP)
  6. */
  7. #include <log.h>
  8. #include <linux/delay.h>
  9. #include <linux/libfdt.h>
  10. #include <mach/cvmx-regs.h>
  11. #include <mach/octeon-model.h>
  12. #include <mach/cvmx-fuse.h>
  13. #include <mach/octeon-feature.h>
  14. #include <mach/cvmx-qlm.h>
  15. #include <mach/octeon_qlm.h>
  16. #include <mach/cvmx-helper-fdt.h>
  17. #include <mach/cvmx-regs.h>
  18. #include <mach/octeon-model.h>
  19. #include <mach/cvmx-fuse.h>
  20. #include <mach/octeon-feature.h>
  21. #include <mach/cvmx-qlm.h>
  22. #include <mach/octeon_qlm.h>
  23. #include <mach/cvmx-pcie.h>
  24. #include <mach/cvmx-error.h>
  25. #include <mach/cvmx-helper.h>
  26. #include <mach/cvmx-helper-util.h>
  27. #include <mach/cvmx-bgxx-defs.h>
  28. #include <mach/cvmx-ciu-defs.h>
  29. #include <mach/cvmx-gmxx-defs.h>
  30. #include <mach/cvmx-gserx-defs.h>
  31. #include <mach/cvmx-mio-defs.h>
  32. #include <mach/cvmx-pciercx-defs.h>
  33. #include <mach/cvmx-pcieepx-defs.h>
  34. #include <mach/cvmx-pemx-defs.h>
  35. #include <mach/cvmx-pexp-defs.h>
  36. #include <mach/cvmx-rst-defs.h>
  37. #include <mach/cvmx-sata-defs.h>
  38. #include <mach/cvmx-sli-defs.h>
  39. #include <mach/cvmx-sriomaintx-defs.h>
  40. #include <mach/cvmx-sriox-defs.h>
  41. #include <mach/cvmx-dpi-defs.h>
  42. #include <mach/cvmx-sli-defs.h>
  43. #include <mach/cvmx-dtx-defs.h>
  44. DECLARE_GLOBAL_DATA_PTR;
  45. #define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
  46. #define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
  47. /* Endian swap mode. */
  48. #define _CVMX_PCIE_ES 1
  49. #define CVMX_READ_CSR(addr) csr_rd_node(node, addr)
  50. #define CVMX_WRITE_CSR(addr, val) csr_wr_node(node, addr, val)
  51. #define CVMX_PCIE_CFGX_READ(p, addr) cvmx_pcie_cfgx_read_node(node, p, addr)
  52. #define CVMX_PCIE_CFGX_WRITE(p, addr, val) cvmx_pcie_cfgx_write_node(node, p, addr, val)
  53. /* #define DEBUG_PCIE */
  54. /* Delay after link up, before issuing first configuration read */
  55. #define PCIE_DEVICE_READY_WAIT_DELAY_MICROSECONDS 700000
  56. /* Recommended Preset Vector: Drop Preset 10 */
  57. int pcie_preset_vec[4] = { 0x593, 0x593, 0x593, 0x593 };
  58. /* Number of LTSSM transitions to record, must be a power of 2 */
  59. #define LTSSM_HISTORY_SIZE 64
  60. #define MAX_RETRIES 2
  61. bool pcie_link_initialized[CVMX_MAX_NODES][CVMX_PCIE_MAX_PORTS];
  62. int cvmx_primary_pcie_bus_number = 1;
  63. static uint32_t __cvmx_pcie_config_read32(int node, int pcie_port, int bus, int dev, int func,
  64. int reg, int lst);
  65. /**
  66. * Return the Core virtual base address for PCIe IO access. IOs are
  67. * read/written as an offset from this address.
  68. *
  69. * @param pcie_port PCIe port the IO is for
  70. *
  71. * Return: 64bit Octeon IO base address for read/write
  72. */
  73. uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
  74. {
  75. cvmx_pcie_address_t pcie_addr;
  76. pcie_addr.u64 = 0;
  77. pcie_addr.io.upper = 0;
  78. pcie_addr.io.io = 1;
  79. pcie_addr.io.did = 3;
  80. pcie_addr.io.subdid = 2;
  81. pcie_addr.io.node = (pcie_port >> 4) & 0x3;
  82. pcie_addr.io.es = _CVMX_PCIE_ES;
  83. pcie_addr.io.port = (pcie_port & 0x3);
  84. return pcie_addr.u64;
  85. }
  86. /**
  87. * Size of the IO address region returned at address
  88. * cvmx_pcie_get_io_base_address()
  89. *
  90. * @param pcie_port PCIe port the IO is for
  91. *
  92. * Return: Size of the IO window
  93. */
  94. uint64_t cvmx_pcie_get_io_size(int pcie_port)
  95. {
  96. return 1ull << 32;
  97. }
  98. /**
  99. * Return the Core virtual base address for PCIe MEM access. Memory is
  100. * read/written as an offset from this address.
  101. *
  102. * @param pcie_port PCIe port the IO is for
  103. *
  104. * Return: 64bit Octeon IO base address for read/write
  105. */
  106. uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
  107. {
  108. cvmx_pcie_address_t pcie_addr;
  109. pcie_addr.u64 = 0;
  110. pcie_addr.mem.upper = 0;
  111. pcie_addr.mem.io = 1;
  112. pcie_addr.mem.did = 3;
  113. pcie_addr.mem.subdid = 3 + (pcie_port & 0x3);
  114. pcie_addr.mem.node = (pcie_port >> 4) & 0x3;
  115. return pcie_addr.u64;
  116. }
  117. /**
  118. * Size of the Mem address region returned at address
  119. * cvmx_pcie_get_mem_base_address()
  120. *
  121. * @param pcie_port PCIe port the IO is for
  122. *
  123. * Return: Size of the Mem window
  124. */
  125. uint64_t cvmx_pcie_get_mem_size(int pcie_port)
  126. {
  127. return 1ull << 36;
  128. }
  129. /**
  130. * @INTERNAL
  131. * Return the QLM number for the PCIE port.
  132. *
  133. * @param pcie_port QLM number to return for.
  134. *
  135. * Return: QLM number.
  136. */
  137. static int __cvmx_pcie_get_qlm(int node, int pcie_port)
  138. {
  139. if (OCTEON_IS_MODEL(OCTEON_CN73XX)) {
  140. cvmx_pemx_cfg_t pem_cfg;
  141. cvmx_pemx_qlm_t pem_qlm;
  142. cvmx_gserx_cfg_t gserx_cfg;
  143. switch (pcie_port) {
  144. case 0: /* PEM0 */
  145. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(0));
  146. if (gserx_cfg.s.pcie)
  147. return 0; /* PEM0 is on QLM0 and possibly QLM1 */
  148. else
  149. return -1; /* PEM0 is disabled */
  150. case 1: /* PEM1 */
  151. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(0));
  152. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(1));
  153. if (!pem_cfg.cn78xx.lanes8 && gserx_cfg.s.pcie)
  154. return 1; /* PEM1 is on QLM 1 */
  155. else
  156. return -1; /* PEM1 is disabled */
  157. case 2: /* PEM2 */
  158. pem_qlm.u64 = CVMX_READ_CSR(CVMX_PEMX_QLM(2));
  159. if (pem_qlm.cn73xx.pemdlmsel == 1) {
  160. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(5));
  161. if (gserx_cfg.s.pcie)
  162. return 5; /* PEM2 is on DLM5 */
  163. else
  164. return -1; /* PEM2 is disabled */
  165. }
  166. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(2));
  167. if (gserx_cfg.s.pcie)
  168. return 2; /* PEM2 is on QLM2 and possibly QLM3 */
  169. else
  170. return -1; /* PEM2 is disabled */
  171. case 3: /* PEM3 */
  172. pem_qlm.u64 = CVMX_READ_CSR(CVMX_PEMX_QLM(3));
  173. if (pem_qlm.cn73xx.pemdlmsel == 1) {
  174. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(6));
  175. if (gserx_cfg.s.pcie)
  176. return 6; /* PEM2 is on DLM5 */
  177. else
  178. return -1; /* PEM2 is disabled */
  179. }
  180. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(2));
  181. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(3));
  182. if (!pem_cfg.cn78xx.lanes8 && gserx_cfg.s.pcie)
  183. return 3; /* PEM2 is on QLM2 and possibly QLM3 */
  184. else
  185. return -1; /* PEM2 is disabled */
  186. default:
  187. printf("Invalid %d PCIe port\n", pcie_port);
  188. return -2;
  189. }
  190. } else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
  191. cvmx_pemx_cfg_t pem_cfg;
  192. cvmx_gserx_cfg_t gserx_cfg;
  193. switch (pcie_port) {
  194. case 0:
  195. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(0));
  196. if (gserx_cfg.s.pcie)
  197. return 0; /* PEM0 is on QLM0 and possibly QLM1 */
  198. else
  199. return -1; /* PEM0 is disabled */
  200. case 1: /* PEM1 */
  201. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(0));
  202. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(1));
  203. if (!pem_cfg.cn78xx.lanes8 && gserx_cfg.s.pcie)
  204. return 1; /* PEM1 is on QLM 1 */
  205. else
  206. return -1; /* PEM1 is disabled */
  207. case 2: /* PEM2 */
  208. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(2));
  209. if (gserx_cfg.s.pcie)
  210. return 2; /* PEM2 is on QLM2 and possibly QLM3 */
  211. else
  212. return -1; /* PEM2 is disabled */
  213. case 3: /* PEM3 */
  214. {
  215. cvmx_gserx_cfg_t gser4_cfg;
  216. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(2));
  217. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(3));
  218. gser4_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(4));
  219. if (pem_cfg.cn78xx.lanes8) {
  220. if (gser4_cfg.s.pcie)
  221. return 4; /* PEM3 is on QLM4 */
  222. else
  223. return -1; /* PEM3 is disabled */
  224. } else {
  225. if (gserx_cfg.s.pcie)
  226. return 3; /* PEM3 is on QLM3 */
  227. else if (gser4_cfg.s.pcie)
  228. return 4; /* PEM3 is on QLM4 */
  229. else
  230. return -1; /* PEM3 is disabled */
  231. }
  232. }
  233. default:
  234. printf("Invalid %d PCIe port\n", pcie_port);
  235. return -1;
  236. }
  237. } else if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
  238. enum cvmx_qlm_mode mode1 = cvmx_qlm_get_mode(1);
  239. enum cvmx_qlm_mode mode2 = cvmx_qlm_get_mode(2);
  240. switch (pcie_port) {
  241. case 0: /* PCIe0 can be DLM1 with 1, 2 or 4 lanes */
  242. if (mode1 == CVMX_QLM_MODE_PCIE || /* Using DLM 1-2 */
  243. mode1 == CVMX_QLM_MODE_PCIE_1X2 || /* Using DLM 1 */
  244. mode1 == CVMX_QLM_MODE_PCIE_2X1 || /* Using DLM 1, lane 0 */
  245. mode1 == CVMX_QLM_MODE_PCIE_1X1) /* Using DLM 1, l0, l1 not used */
  246. return 1;
  247. else
  248. return -1;
  249. case 1: /* PCIe1 can be DLM1 1 lane(1), DLM2 1 lane(0) or 2 lanes(0-1) */
  250. if (mode1 == CVMX_QLM_MODE_PCIE_2X1)
  251. return 1;
  252. else if (mode2 == CVMX_QLM_MODE_PCIE_1X2)
  253. return 2;
  254. else if (mode2 == CVMX_QLM_MODE_PCIE_2X1)
  255. return 2;
  256. else
  257. return -1;
  258. case 2: /* PCIe2 can be DLM2 1 lanes(1) */
  259. if (mode2 == CVMX_QLM_MODE_PCIE_2X1)
  260. return 2;
  261. else
  262. return -1;
  263. default: /* Only three PEM blocks */
  264. return -1;
  265. }
  266. } else if (OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
  267. cvmx_gserx_cfg_t gserx_cfg;
  268. switch (pcie_port) {
  269. case 0: /* PEM0 */
  270. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(0));
  271. if (gserx_cfg.s.pcie)
  272. return 0; /* PEM0 is on QLM0 and possibly QLM1 */
  273. else
  274. return -1; /* PEM0 is disabled */
  275. case 1: /* PEM1 */
  276. gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(1));
  277. if (gserx_cfg.s.pcie)
  278. return 1; /* PEM1 is on DLM1 */
  279. else
  280. return -1; /* PEM1 is disabled */
  281. default:
  282. return -1;
  283. }
  284. }
  285. return -1;
  286. }
  287. /**
  288. * @INTERNAL
  289. * Initialize the RC config space CSRs
  290. *
  291. * @param node node
  292. * @param pcie_port PCIe port to initialize
  293. */
  294. static void __cvmx_pcie_rc_initialize_config_space(int node, int pcie_port)
  295. {
  296. /* Max Payload Size (PCIE*_CFG030[MPS]) */
  297. /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
  298. /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
  299. /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
  300. {
  301. cvmx_pciercx_cfg030_t pciercx_cfg030;
  302. pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port,
  303. CVMX_PCIERCX_CFG030(pcie_port));
  304. pciercx_cfg030.s.mps = MPS_CN6XXX;
  305. pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
  306. /*
  307. * Enable relaxed order processing. This will allow devices
  308. * to affect read response ordering
  309. */
  310. pciercx_cfg030.s.ro_en = 1;
  311. /* Enable no snoop processing. Not used by Octeon */
  312. pciercx_cfg030.s.ns_en = 1;
  313. /* Correctable error reporting enable. */
  314. pciercx_cfg030.s.ce_en = 1;
  315. /* Non-fatal error reporting enable. */
  316. pciercx_cfg030.s.nfe_en = 1;
  317. /* Fatal error reporting enable. */
  318. pciercx_cfg030.s.fe_en = 1;
  319. /* Unsupported request reporting enable. */
  320. pciercx_cfg030.s.ur_en = 1;
  321. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
  322. pciercx_cfg030.u32);
  323. }
  324. /*
  325. * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
  326. * PCIE*_CFG030[MPS]
  327. */
  328. /*
  329. * Max Read Request Size (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
  330. * PCIE*_CFG030[MRRS]
  331. */
  332. cvmx_dpi_sli_prtx_cfg_t prt_cfg;
  333. cvmx_sli_s2m_portx_ctl_t sli_s2m_portx_ctl;
  334. prt_cfg.u64 = CVMX_READ_CSR(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
  335. prt_cfg.s.mps = MPS_CN6XXX;
  336. prt_cfg.s.mrrs = MRRS_CN6XXX;
  337. /* Max outstanding load request. */
  338. prt_cfg.s.molr = 32;
  339. CVMX_WRITE_CSR(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
  340. sli_s2m_portx_ctl.u64 = CVMX_READ_CSR(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
  341. if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX) ||
  342. OCTEON_IS_MODEL(OCTEON_CNF75XX)))
  343. sli_s2m_portx_ctl.cn61xx.mrrs = MRRS_CN6XXX;
  344. CVMX_WRITE_CSR(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
  345. /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
  346. {
  347. cvmx_pciercx_cfg070_t pciercx_cfg070;
  348. pciercx_cfg070.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
  349. pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
  350. pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
  351. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
  352. }
  353. /* Access Enables (PCIE*_CFG001[MSAE,ME]) */
  354. /* ME and MSAE should always be set. */
  355. /* Interrupt Disable (PCIE*_CFG001[I_DIS]) */
  356. /* System Error Message Enable (PCIE*_CFG001[SEE]) */
  357. {
  358. cvmx_pciercx_cfg001_t pciercx_cfg001;
  359. pciercx_cfg001.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
  360. pciercx_cfg001.s.msae = 1; /* Memory space enable. */
  361. pciercx_cfg001.s.me = 1; /* Bus master enable. */
  362. pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
  363. pciercx_cfg001.s.see = 1; /* SERR# enable */
  364. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
  365. }
  366. /* Advanced Error Recovery Message Enables */
  367. /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
  368. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
  369. /* Use CVMX_PCIERCX_CFG067 hardware default */
  370. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
  371. /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
  372. {
  373. cvmx_pciercx_cfg032_t pciercx_cfg032;
  374. pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  375. pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
  376. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
  377. }
  378. /* Link Width Mode (PCIERCn_CFG452[LME]) - Set during
  379. * cvmx_pcie_rc_initialize_link()
  380. */
  381. /* Primary Bus Number (PCIERCn_CFG006[PBNUM]) */
  382. {
  383. /* We set the primary bus number to 1 so IDT bridges are happy.
  384. * They don't like zero
  385. */
  386. cvmx_pciercx_cfg006_t pciercx_cfg006;
  387. pciercx_cfg006.u32 = 0;
  388. pciercx_cfg006.s.pbnum = cvmx_primary_pcie_bus_number;
  389. pciercx_cfg006.s.sbnum = cvmx_primary_pcie_bus_number;
  390. pciercx_cfg006.s.subbnum = cvmx_primary_pcie_bus_number;
  391. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
  392. }
  393. /* Memory-mapped I/O BAR (PCIERCn_CFG008) */
  394. /* Most applications should disable the memory-mapped I/O BAR by */
  395. /* setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR] */
  396. {
  397. cvmx_pciercx_cfg008_t pciercx_cfg008;
  398. pciercx_cfg008.u32 = 0;
  399. pciercx_cfg008.s.mb_addr = 0x100;
  400. pciercx_cfg008.s.ml_addr = 0;
  401. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
  402. }
  403. /* Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011) */
  404. /* Most applications should disable the prefetchable BAR by setting */
  405. /* PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] < */
  406. /* PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE] */
  407. {
  408. cvmx_pciercx_cfg009_t pciercx_cfg009;
  409. cvmx_pciercx_cfg010_t pciercx_cfg010;
  410. cvmx_pciercx_cfg011_t pciercx_cfg011;
  411. pciercx_cfg009.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
  412. pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
  413. pciercx_cfg011.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
  414. pciercx_cfg009.s.lmem_base = 0x100;
  415. pciercx_cfg009.s.lmem_limit = 0;
  416. pciercx_cfg010.s.umem_base = 0x100;
  417. pciercx_cfg011.s.umem_limit = 0;
  418. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
  419. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
  420. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
  421. }
  422. /* System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE]) */
  423. /* PME Interrupt Enables (PCIERCn_CFG035[PMEIE]) */
  424. {
  425. cvmx_pciercx_cfg035_t pciercx_cfg035;
  426. pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
  427. pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
  428. pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
  429. pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
  430. pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
  431. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
  432. }
  433. /* Advanced Error Recovery Interrupt Enables */
  434. /* (PCIERCn_CFG075[CERE,NFERE,FERE]) */
  435. {
  436. cvmx_pciercx_cfg075_t pciercx_cfg075;
  437. pciercx_cfg075.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
  438. pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
  439. pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
  440. pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
  441. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
  442. }
  443. /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN], */
  444. /* PCIERCn_CFG034[DLLS_EN,CCINT_EN]) */
  445. {
  446. cvmx_pciercx_cfg034_t pciercx_cfg034;
  447. pciercx_cfg034.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
  448. pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
  449. pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
  450. pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
  451. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
  452. }
  453. if (OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX) ||
  454. OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
  455. int qlm = __cvmx_pcie_get_qlm(node, pcie_port);
  456. int speed = cvmx_qlm_get_gbaud_mhz(qlm);
  457. cvmx_pemx_cfg_t pem_cfg;
  458. cvmx_pciercx_cfg031_t cfg031;
  459. cvmx_pciercx_cfg040_t cfg040;
  460. cvmx_pciercx_cfg452_t cfg452;
  461. cvmx_pciercx_cfg089_t cfg089;
  462. cvmx_pciercx_cfg090_t cfg090;
  463. cvmx_pciercx_cfg091_t cfg091;
  464. cvmx_pciercx_cfg092_t cfg092;
  465. cvmx_pciercx_cfg554_t cfg554;
  466. /*
  467. * Make sure the PEM agrees with GSERX about the speed
  468. * its going to try
  469. */
  470. switch (speed) {
  471. case 2500: /* Gen1 */
  472. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
  473. pem_cfg.s.md = 0;
  474. CVMX_WRITE_CSR(CVMX_PEMX_CFG(pcie_port), pem_cfg.u64);
  475. /* Set the target link speed */
  476. cfg040.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG040(pcie_port));
  477. cfg040.s.tls = 1;
  478. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG040(pcie_port), cfg040.u32);
  479. break;
  480. case 5000: /* Gen2 */
  481. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
  482. pem_cfg.s.md = 1;
  483. CVMX_WRITE_CSR(CVMX_PEMX_CFG(pcie_port), pem_cfg.u64);
  484. /* Set the target link speed */
  485. cfg040.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG040(pcie_port));
  486. cfg040.s.tls = 2;
  487. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG040(pcie_port), cfg040.u32);
  488. break;
  489. case 8000: /* Gen3 */
  490. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
  491. pem_cfg.s.md = 2;
  492. CVMX_WRITE_CSR(CVMX_PEMX_CFG(pcie_port), pem_cfg.u64);
  493. /* Set the target link speed */
  494. cfg040.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG040(pcie_port));
  495. cfg040.s.tls = 3;
  496. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG040(pcie_port), cfg040.u32);
  497. break;
  498. default:
  499. break;
  500. }
  501. /* Link Width Mode (PCIERCn_CFG452[LME]) */
  502. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
  503. cfg452.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
  504. if (qlm >= 5)
  505. cfg452.s.lme = 0x3;
  506. else
  507. cfg452.s.lme = (pem_cfg.cn78xx.lanes8) ? 0xf : 0x7;
  508. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), cfg452.u32);
  509. /* Errata PEM-25990 - Disable ASLPMS */
  510. cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
  511. cfg031.s.aslpms = 0;
  512. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), cfg031.u32);
  513. /* CFG554.PRV default changed from 16'h7ff to 16'h593. */
  514. cfg554.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG554(pcie_port));
  515. cfg554.s.prv = pcie_preset_vec[pcie_port];
  516. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG554(pcie_port), cfg554.u32);
  517. /* Errata PEM-26189 - Disable the 2ms timer on all chips */
  518. cfg554.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG554(pcie_port));
  519. cfg554.s.p23td = 1;
  520. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG554(pcie_port), cfg554.u32);
  521. /* Errata PEM-21178 - Change the CFG[089-092] LxUTP & LxDTP defaults. */
  522. cfg089.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG089(pcie_port));
  523. cfg089.s.l1ddtp = 7;
  524. cfg089.s.l1utp = 7;
  525. cfg089.s.l0dtp = 7;
  526. cfg089.s.l0utp = 7;
  527. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG089(pcie_port), cfg089.u32);
  528. cfg090.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG090(pcie_port));
  529. cfg090.s.l3dtp = 7;
  530. cfg090.s.l3utp = 7;
  531. cfg090.s.l2dtp = 7;
  532. cfg090.s.l2utp = 7;
  533. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG090(pcie_port), cfg090.u32);
  534. cfg091.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG091(pcie_port));
  535. cfg091.s.l5dtp = 7;
  536. cfg091.s.l5utp = 7;
  537. cfg091.s.l4dtp = 7;
  538. cfg091.s.l4utp = 7;
  539. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG091(pcie_port), cfg091.u32);
  540. cfg092.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG092(pcie_port));
  541. cfg092.s.l7dtp = 7;
  542. cfg092.s.l7utp = 7;
  543. cfg092.s.l6dtp = 7;
  544. cfg092.s.l6utp = 7;
  545. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG092(pcie_port), cfg092.u32);
  546. }
  547. }
  548. static void __cvmx_increment_ba(cvmx_sli_mem_access_subidx_t *pmas)
  549. {
  550. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  551. pmas->cn68xx.ba++;
  552. else
  553. pmas->cn63xx.ba++;
  554. }
  555. /*
  556. * milliseconds to retry PCIe cfg-space access:
  557. * Value 32(unscaled) was recommended in HRM, but may be too small for
  558. * some PCIe devices. This 200mS default should cover most devices,
  559. * but can be extended by bootparam cvmx-pcie.cfg_timeout, or reduced
  560. * to speed boot if it is known that no devices need so much time.
  561. */
  562. static int cfg_timeout = 200;
  563. static int cfg_retries(void)
  564. {
  565. static int cfg_ticks = -1;
  566. if (cfg_ticks < 0) {
  567. u64 nS = cfg_timeout * 1000000;
  568. const int ceiling = 0xffff;
  569. cfg_ticks = nS / (gd->bus_clk >> 16);
  570. if (cfg_ticks > ceiling)
  571. cfg_ticks = ceiling;
  572. }
  573. return cfg_ticks;
  574. }
  575. /**
  576. * @INTERNAL
  577. * Enable/Disable PEMX_PEMON.pemon based on the direction.
  578. *
  579. * @param node node
  580. * @param pcie_port PCIe port
  581. * @param direction 0 to disable, 1 to enable
  582. */
  583. static void __cvmx_pcie_config_pemon(int node, int pcie_port, bool direction)
  584. {
  585. cvmx_pemx_on_t pemon;
  586. pemon.u64 = CVMX_READ_CSR(CVMX_PEMX_ON(pcie_port));
  587. pemon.s.pemon = direction;
  588. CVMX_WRITE_CSR(CVMX_PEMX_ON(pcie_port), pemon.u64);
  589. pemon.u64 = CVMX_READ_CSR(CVMX_PEMX_ON(pcie_port));
  590. }
  591. /**
  592. * @INTERNAL
  593. * De-assert GSER_PHY.phy_reset for a given qlm
  594. *
  595. * @param node node
  596. * @param qlm qlm for a given PCIe port
  597. */
  598. static void __cvmx_pcie_gser_phy_config(int node, int pcie_port, int qlm)
  599. {
  600. cvmx_pemx_cfg_t pem_cfg;
  601. cvmx_gserx_phy_ctl_t ctrl;
  602. int has_8lanes = 0;
  603. int is_gen3 = 0;
  604. ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm));
  605. /* Assert the reset */
  606. ctrl.s.phy_reset = 1;
  607. CVMX_WRITE_CSR(CVMX_GSERX_PHY_CTL(qlm), ctrl.u64);
  608. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
  609. udelay(10);
  610. has_8lanes = pem_cfg.cn78xx.lanes8;
  611. is_gen3 = pem_cfg.cn78xx.md >= 2;
  612. if (has_8lanes) {
  613. ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm + 1));
  614. ctrl.s.phy_reset = 1;
  615. CVMX_WRITE_CSR(CVMX_GSERX_PHY_CTL(qlm + 1), ctrl.u64);
  616. ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm + 1));
  617. }
  618. ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm));
  619. udelay(10);
  620. /* Deassert the reset */
  621. ctrl.s.phy_reset = 0;
  622. CVMX_WRITE_CSR(CVMX_GSERX_PHY_CTL(qlm), ctrl.u64);
  623. pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
  624. udelay(500);
  625. if (has_8lanes) {
  626. ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm + 1));
  627. ctrl.s.phy_reset = 0;
  628. CVMX_WRITE_CSR(CVMX_GSERX_PHY_CTL(qlm + 1), ctrl.u64);
  629. }
  630. ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm));
  631. udelay(500);
  632. /* Apply some erratas after PHY reset, only applies to PCIe GEN3 */
  633. if (is_gen3) {
  634. int i;
  635. int high_qlm = has_8lanes ? qlm + 1 : qlm;
  636. /* Apply workaround for Errata GSER-26150 */
  637. if (OCTEON_IS_MODEL(OCTEON_CN73XX_PASS1_0)) {
  638. for (i = qlm; i < high_qlm; i++) {
  639. cvmx_gserx_glbl_pll_cfg_3_t pll_cfg_3;
  640. cvmx_gserx_glbl_misc_config_1_t misc_config_1;
  641. /* Update PLL parameters */
  642. /*
  643. * Step 1: Set
  644. * GSER()_GLBL_PLL_CFG_3[PLL_VCTRL_SEL_LCVCO_VAL] = 0x2,
  645. * and
  646. * GSER()_GLBL_PLL_CFG_3[PCS_SDS_PLL_VCO_AMP] = 0
  647. */
  648. pll_cfg_3.u64 = CVMX_READ_CSR(CVMX_GSERX_GLBL_PLL_CFG_3(i));
  649. pll_cfg_3.s.pcs_sds_pll_vco_amp = 0;
  650. pll_cfg_3.s.pll_vctrl_sel_lcvco_val = 2;
  651. CVMX_WRITE_CSR(CVMX_GSERX_GLBL_PLL_CFG_3(i), pll_cfg_3.u64);
  652. /*
  653. * Step 2: Set
  654. * GSER()_GLBL_MISC_CONFIG_1[PCS_SDS_TRIM_CHP_REG] = 0x2.
  655. */
  656. misc_config_1.u64 = CVMX_READ_CSR(CVMX_GSERX_GLBL_MISC_CONFIG_1(i));
  657. misc_config_1.s.pcs_sds_trim_chp_reg = 2;
  658. CVMX_WRITE_CSR(CVMX_GSERX_GLBL_MISC_CONFIG_1(i), misc_config_1.u64);
  659. }
  660. }
  661. /* Apply workaround for Errata GSER-25992 */
  662. if (OCTEON_IS_MODEL(OCTEON_CN73XX_PASS1_X) ||
  663. OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) {
  664. for (i = qlm; i < high_qlm; i++)
  665. cvmx_qlm_gser_errata_25992(node, i);
  666. }
  667. }
  668. }
  669. /* Get the PCIe LTSSM state for the given port
  670. *
  671. * @param node Node to query
  672. * @param pcie_port PEM to query
  673. *
  674. * Return: LTSSM state
  675. */
  676. static int __cvmx_pcie_rc_get_ltssm_state(int node, int pcie_port)
  677. {
  678. u64 debug;
  679. if (OCTEON_IS_MODEL(OCTEON_CN73XX) && pcie_port == 0) {
  680. CVMX_WRITE_CSR(CVMX_DTX_SPEM_SELX(0), 0);
  681. CVMX_READ_CSR(CVMX_DTX_SPEM_SELX(0));
  682. CVMX_WRITE_CSR(CVMX_DTX_SPEM_ENAX(0), 0xfffffffffull);
  683. CVMX_READ_CSR(CVMX_DTX_SPEM_ENAX(0));
  684. /* Read the value */
  685. debug = CVMX_READ_CSR(CVMX_DTX_SPEM_DATX(0));
  686. /* Disable the PEM from driving OCLA signals */
  687. CVMX_WRITE_CSR(CVMX_DTX_SPEM_ENAX(0), 0);
  688. CVMX_READ_CSR(CVMX_DTX_SPEM_ENAX(0));
  689. } else {
  690. /* LTSSM state is in debug select 0 */
  691. CVMX_WRITE_CSR(CVMX_DTX_PEMX_SELX(0, pcie_port), 0);
  692. CVMX_READ_CSR(CVMX_DTX_PEMX_SELX(0, pcie_port));
  693. CVMX_WRITE_CSR(CVMX_DTX_PEMX_ENAX(0, pcie_port), 0xfffffffffull);
  694. CVMX_READ_CSR(CVMX_DTX_PEMX_ENAX(0, pcie_port));
  695. /* Read the value */
  696. debug = CVMX_READ_CSR(CVMX_DTX_PEMX_DATX(0, pcie_port));
  697. /* Disable the PEM from driving OCLA signals */
  698. CVMX_WRITE_CSR(CVMX_DTX_PEMX_ENAX(0, pcie_port), 0);
  699. CVMX_READ_CSR(CVMX_DTX_PEMX_ENAX(0, pcie_port));
  700. }
  701. /* DBGSEL = 0x0, bits[8:3] */
  702. return cvmx_bit_extract(debug, 3, 6);
  703. }
  704. /**
  705. * Get the PCIe LTSSM state for the given port
  706. *
  707. * @param node Node to query
  708. * @param pcie_port PEM to query
  709. *
  710. * Return: LTSSM state
  711. */
  712. static const char *cvmx_pcie_get_ltssm_string(int ltssm)
  713. {
  714. switch (ltssm) {
  715. case 0x00:
  716. return "DETECT_QUIET";
  717. case 0x01:
  718. return "DETECT_ACT";
  719. case 0x02:
  720. return "POLL_ACTIVE";
  721. case 0x03:
  722. return "POLL_COMPLIANCE";
  723. case 0x04:
  724. return "POLL_CONFIG";
  725. case 0x05:
  726. return "PRE_DETECT_QUIET";
  727. case 0x06:
  728. return "DETECT_WAIT";
  729. case 0x07:
  730. return "CFG_LINKWD_START";
  731. case 0x08:
  732. return "CFG_LINKWD_ACEPT";
  733. case 0x09:
  734. return "CFG_LANENUM_WAIT";
  735. case 0x0A:
  736. return "CFG_LANENUM_ACEPT";
  737. case 0x0B:
  738. return "CFG_COMPLETE";
  739. case 0x0C:
  740. return "CFG_IDLE";
  741. case 0x0D:
  742. return "RCVRY_LOCK";
  743. case 0x0E:
  744. return "RCVRY_SPEED";
  745. case 0x0F:
  746. return "RCVRY_RCVRCFG";
  747. case 0x10:
  748. return "RCVRY_IDLE";
  749. case 0x11:
  750. return "L0";
  751. case 0x12:
  752. return "L0S";
  753. case 0x13:
  754. return "L123_SEND_EIDLE";
  755. case 0x14:
  756. return "L1_IDLE";
  757. case 0x15:
  758. return "L2_IDLE";
  759. case 0x16:
  760. return "L2_WAKE";
  761. case 0x17:
  762. return "DISABLED_ENTRY";
  763. case 0x18:
  764. return "DISABLED_IDLE";
  765. case 0x19:
  766. return "DISABLED";
  767. case 0x1A:
  768. return "LPBK_ENTRY";
  769. case 0x1B:
  770. return "LPBK_ACTIVE";
  771. case 0x1C:
  772. return "LPBK_EXIT";
  773. case 0x1D:
  774. return "LPBK_EXIT_TIMEOUT";
  775. case 0x1E:
  776. return "HOT_RESET_ENTRY";
  777. case 0x1F:
  778. return "HOT_RESET";
  779. case 0x20:
  780. return "RCVRY_EQ0";
  781. case 0x21:
  782. return "RCVRY_EQ1";
  783. case 0x22:
  784. return "RCVRY_EQ2";
  785. case 0x23:
  786. return "RCVRY_EQ3";
  787. default:
  788. return "Unknown";
  789. }
  790. }
  791. /**
  792. * During PCIe link initialization we need to make config request to the attached
  793. * device to verify its speed and width. These config access happen very early
  794. * after the device is taken out of reset, so may fail for some amount of time.
  795. * This function automatically retries these config accesses. The normal builtin
  796. * hardware retry isn't enough for this very early access.
  797. *
  798. * @param node Note to read from
  799. * @param pcie_port PCIe port to read from
  800. * @param bus PCIe bus number
  801. * @param dev PCIe device
  802. * @param func PCIe function on the device
  803. * @param reg Register to read
  804. *
  805. * Return: Config register value, or all ones on failure
  806. */
  807. static uint32_t cvmx_pcie_config_read32_retry(int node, int pcie_port, int bus, int dev, int func,
  808. int reg)
  809. {
  810. /*
  811. * Read the PCI config register until we get a valid value. Some cards
  812. * require time after link up to return data. Wait at most 3 seconds
  813. */
  814. u64 timeout = 300;
  815. u32 val;
  816. do {
  817. /* Read PCI capability pointer */
  818. val = __cvmx_pcie_config_read32(node, pcie_port, bus, dev, func, reg, 0);
  819. /* Check the read succeeded */
  820. if (val != 0xffffffff)
  821. return val;
  822. /* Failed, wait a little and try again */
  823. mdelay(10);
  824. } while (--timeout);
  825. debug("N%d.PCIe%d: Config read failed, can't communicate with device\n",
  826. node, pcie_port);
  827. return -1;
  828. }
  829. /**
  830. * @INTERNAL
  831. * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
  832. * port from reset to a link up state. Software can then begin
  833. * configuring the rest of the link.
  834. *
  835. * @param node node
  836. * @param pcie_port PCIe port to initialize
  837. *
  838. * Return: Zero on success
  839. */
  840. static int __cvmx_pcie_rc_initialize_link_gen2(int node, int pcie_port)
  841. {
  842. u64 start_cycle;
  843. cvmx_pemx_ctl_status_t pem_ctl_status;
  844. cvmx_pciercx_cfg032_t pciercx_cfg032;
  845. cvmx_pciercx_cfg448_t pciercx_cfg448;
  846. if (OCTEON_IS_OCTEON3()) {
  847. if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_PEMX_ON(pcie_port), cvmx_pemx_on_t,
  848. pemoor, ==, 1, 100000)) {
  849. printf("%d:PCIe: Port %d PEM not on, skipping\n", node, pcie_port);
  850. return -1;
  851. }
  852. }
  853. /* Bring up the link */
  854. pem_ctl_status.u64 = CVMX_READ_CSR(CVMX_PEMX_CTL_STATUS(pcie_port));
  855. pem_ctl_status.s.lnk_enb = 1;
  856. CVMX_WRITE_CSR(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
  857. /* Wait for the link to come up */
  858. start_cycle = get_timer(0);
  859. do {
  860. if (get_timer(start_cycle) > 1000)
  861. return -1;
  862. udelay(1000);
  863. pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port,
  864. CVMX_PCIERCX_CFG032(pcie_port));
  865. } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
  866. /* Update the Replay Time Limit. Empirically, some PCIe devices take a
  867. * little longer to respond than expected under load. As a workaround
  868. * for this we configure the Replay Time Limit to the value expected
  869. * for a 512 byte MPS instead of our actual 256 byte MPS. The numbers
  870. * below are directly from the PCIe spec table 3-4
  871. */
  872. pciercx_cfg448.u32 = CVMX_PCIE_CFGX_READ(pcie_port,
  873. CVMX_PCIERCX_CFG448(pcie_port));
  874. switch (pciercx_cfg032.s.nlw) {
  875. case 1: /* 1 lane */
  876. pciercx_cfg448.s.rtl = 1677;
  877. break;
  878. case 2: /* 2 lanes */
  879. pciercx_cfg448.s.rtl = 867;
  880. break;
  881. case 4: /* 4 lanes */
  882. pciercx_cfg448.s.rtl = 462;
  883. break;
  884. case 8: /* 8 lanes */
  885. pciercx_cfg448.s.rtl = 258;
  886. break;
  887. }
  888. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
  889. pciercx_cfg448.u32);
  890. return 0;
  891. }
  892. extern int octeon_pcie_get_qlm_from_fdt(int numa_node, int pcie_port);
  893. static int __cvmx_pcie_check_pcie_port(int node, int pcie_port, enum cvmx_qlm_mode mode)
  894. {
  895. if (mode == CVMX_QLM_MODE_SRIO_1X4 || mode == CVMX_QLM_MODE_SRIO_2X2 ||
  896. mode == CVMX_QLM_MODE_SRIO_4X1) {
  897. printf("%d:PCIe: Port %d is SRIO, skipping.\n", node, pcie_port);
  898. return -1;
  899. } else if (mode == CVMX_QLM_MODE_SGMII) {
  900. printf("%d:PCIe: Port %d is SGMII, skipping.\n", node, pcie_port);
  901. return -1;
  902. } else if (mode == CVMX_QLM_MODE_XAUI || mode == CVMX_QLM_MODE_RXAUI) {
  903. printf("%d:PCIe: Port %d is XAUI, skipping.\n", node, pcie_port);
  904. return -1;
  905. } else if (mode == CVMX_QLM_MODE_ILK) {
  906. printf("%d:PCIe: Port %d is ILK, skipping.\n", node, pcie_port);
  907. return -1;
  908. } else if (mode != CVMX_QLM_MODE_PCIE &&
  909. mode != CVMX_QLM_MODE_PCIE_1X8 &&
  910. mode != CVMX_QLM_MODE_PCIE_1X2 &&
  911. mode != CVMX_QLM_MODE_PCIE_2X1 &&
  912. mode != CVMX_QLM_MODE_PCIE_1X1) {
  913. printf("%d:PCIe: Port %d is unknown, skipping.\n",
  914. node, pcie_port);
  915. return -1;
  916. }
  917. return 0;
  918. }
  919. static int __cvmx_pcie_check_qlm_mode(int node, int pcie_port, int qlm)
  920. {
  921. enum cvmx_qlm_mode mode = CVMX_QLM_MODE_DISABLED;
  922. if (qlm < 0)
  923. return -1;
  924. /* Make sure this interface is PCIe */
  925. if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
  926. if (cvmx_qlm_get_dlm_mode(1, pcie_port) ==
  927. CVMX_QLM_MODE_DISABLED) {
  928. printf("PCIe: Port %d not in PCIe mode, skipping\n",
  929. pcie_port);
  930. return -1;
  931. }
  932. } else if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
  933. /*
  934. * Requires reading the MIO_QLMX_CFG register to figure
  935. * out the port type.
  936. */
  937. if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
  938. qlm = 3 - (pcie_port * 2);
  939. } else if (OCTEON_IS_MODEL(OCTEON_CN61XX)) {
  940. cvmx_mio_qlmx_cfg_t qlm_cfg;
  941. qlm_cfg.u64 = csr_rd(CVMX_MIO_QLMX_CFG(1));
  942. if (qlm_cfg.s.qlm_cfg == 1)
  943. qlm = 1;
  944. else
  945. qlm = pcie_port;
  946. } else if (OCTEON_IS_MODEL(OCTEON_CN66XX) ||
  947. OCTEON_IS_MODEL(OCTEON_CN63XX)) {
  948. qlm = pcie_port;
  949. }
  950. /*
  951. * PCIe is allowed only in QLM1, 1 PCIe port in x2 or
  952. * 2 PCIe ports in x1
  953. */
  954. else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
  955. qlm = 1;
  956. mode = cvmx_qlm_get_mode(qlm);
  957. __cvmx_pcie_check_pcie_port(node, pcie_port, mode);
  958. }
  959. return 0;
  960. }
  961. static void __cvmx_pcie_sli_config(int node, int pcie_port)
  962. {
  963. cvmx_pemx_bar_ctl_t pemx_bar_ctl;
  964. cvmx_pemx_ctl_status_t pemx_ctl_status;
  965. cvmx_sli_ctl_portx_t sli_ctl_portx;
  966. cvmx_sli_mem_access_ctl_t sli_mem_access_ctl;
  967. cvmx_sli_mem_access_subidx_t mem_access_subid;
  968. cvmx_pemx_bar1_indexx_t bar1_index;
  969. int i;
  970. /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
  971. sli_mem_access_ctl.u64 = CVMX_READ_CSR(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
  972. sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
  973. sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
  974. CVMX_WRITE_CSR(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
  975. /* Setup Mem access SubDIDs */
  976. mem_access_subid.u64 = 0;
  977. mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
  978. mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
  979. mem_access_subid.s.esr = _CVMX_PCIE_ES; /* Endian-swap for Reads. */
  980. mem_access_subid.s.esw = _CVMX_PCIE_ES; /* Endian-swap for Writes. */
  981. mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
  982. mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
  983. /* PCIe Address Bits <63:34>. */
  984. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  985. mem_access_subid.cn68xx.ba = 0;
  986. else
  987. mem_access_subid.cn63xx.ba = 0;
  988. /* Setup mem access 12-15 for port 0, 16-19 for port 1, supplying 36
  989. * bits of address space
  990. */
  991. for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
  992. CVMX_WRITE_CSR(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
  993. /* Set each SUBID to extend the addressable range */
  994. __cvmx_increment_ba(&mem_access_subid);
  995. }
  996. if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) ||
  997. OCTEON_IS_MODEL(OCTEON_CN68XX) ||
  998. (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))) {
  999. /* Disable the peer to peer forwarding register. This must be
  1000. * setup by the OS after it enumerates the bus and assigns
  1001. * addresses to the PCIe busses
  1002. */
  1003. for (i = 0; i < 4; i++) {
  1004. CVMX_WRITE_CSR(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
  1005. CVMX_WRITE_CSR(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
  1006. }
  1007. }
  1008. /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
  1009. CVMX_WRITE_CSR(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
  1010. /* Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take precedence
  1011. * where they overlap. It also overlaps with the device addresses, so
  1012. * make sure the peer to peer forwarding is set right
  1013. */
  1014. CVMX_WRITE_CSR(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
  1015. /* Setup BAR2 attributes */
  1016. /* Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) */
  1017. /* - PTLP_RO,CTLP_RO should normally be set (except for debug). */
  1018. /* - WAIT_COM=0 will likely work for all applications. */
  1019. /* Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]) */
  1020. pemx_bar_ctl.u64 = CVMX_READ_CSR(CVMX_PEMX_BAR_CTL(pcie_port));
  1021. pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1 */
  1022. pemx_bar_ctl.s.bar2_enb = 1;
  1023. pemx_bar_ctl.s.bar2_esx = _CVMX_PCIE_ES;
  1024. pemx_bar_ctl.s.bar2_cax = 0;
  1025. CVMX_WRITE_CSR(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
  1026. sli_ctl_portx.u64 = CVMX_READ_CSR(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
  1027. sli_ctl_portx.s.ptlp_ro = 1;
  1028. sli_ctl_portx.s.ctlp_ro = 1;
  1029. sli_ctl_portx.s.wait_com = 0;
  1030. sli_ctl_portx.s.waitl_com = 0;
  1031. CVMX_WRITE_CSR(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
  1032. /* BAR1 follows BAR2 */
  1033. CVMX_WRITE_CSR(CVMX_PEMX_P2N_BAR1_START(pcie_port),
  1034. CVMX_PCIE_BAR1_RC_BASE);
  1035. bar1_index.u64 = 0;
  1036. bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
  1037. bar1_index.s.ca = 1; /* Not Cached */
  1038. bar1_index.s.end_swp = _CVMX_PCIE_ES; /* Endian Swap mode */
  1039. bar1_index.s.addr_v = 1; /* Valid entry */
  1040. for (i = 0; i < 16; i++) {
  1041. CVMX_WRITE_CSR(CVMX_PEMX_BAR1_INDEXX(i, pcie_port),
  1042. bar1_index.u64);
  1043. /* 256MB / 16 >> 22 == 4 */
  1044. bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
  1045. }
  1046. /* Wait for 200ms */
  1047. pemx_ctl_status.u64 = CVMX_READ_CSR(CVMX_PEMX_CTL_STATUS(pcie_port));
  1048. pemx_ctl_status.cn63xx.cfg_rtry = cfg_retries();
  1049. CVMX_WRITE_CSR(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
  1050. /*
  1051. * Here is the second part of the config retry changes. Wait for 700ms
  1052. * after setting up the link before continuing. PCIe says the devices
  1053. * may need up to 900ms to come up. 700ms plus 200ms from above gives
  1054. * us a total of 900ms
  1055. */
  1056. if (OCTEON_IS_OCTEON2() || OCTEON_IS_MODEL(OCTEON_CN70XX))
  1057. udelay(PCIE_DEVICE_READY_WAIT_DELAY_MICROSECONDS);
  1058. }
  1059. /**
  1060. * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
  1061. * the bus.
  1062. *
  1063. * @param pcie_port PCIe port to initialize
  1064. *
  1065. * Return: Zero on success
  1066. */
  1067. static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
  1068. {
  1069. cvmx_ciu_soft_prst_t ciu_soft_prst;
  1070. cvmx_mio_rst_ctlx_t mio_rst_ctl;
  1071. cvmx_pemx_bist_status_t pemx_bist_status;
  1072. cvmx_pemx_bist_status2_t pemx_bist_status2;
  1073. cvmx_pciercx_cfg032_t pciercx_cfg032;
  1074. cvmx_pciercx_cfg515_t pciercx_cfg515;
  1075. u64 ciu_soft_prst_reg, rst_ctl_reg;
  1076. int ep_mode;
  1077. int qlm = 0;
  1078. int node = (pcie_port >> 4) & 0x3;
  1079. pcie_port &= 0x3;
  1080. if (pcie_port >= CVMX_PCIE_PORTS) {
  1081. //debug("Invalid PCIe%d port\n", pcie_port);
  1082. return -1;
  1083. }
  1084. if (__cvmx_pcie_check_qlm_mode(node, pcie_port, qlm))
  1085. return -1;
  1086. /* Make sure we aren't trying to setup a target mode interface in host
  1087. * mode
  1088. */
  1089. if (OCTEON_IS_OCTEON3()) {
  1090. ciu_soft_prst_reg = CVMX_RST_SOFT_PRSTX(pcie_port);
  1091. rst_ctl_reg = CVMX_RST_CTLX(pcie_port);
  1092. } else {
  1093. ciu_soft_prst_reg = (pcie_port) ? CVMX_CIU_SOFT_PRST1 : CVMX_CIU_SOFT_PRST;
  1094. rst_ctl_reg = CVMX_MIO_RST_CTLX(pcie_port);
  1095. }
  1096. mio_rst_ctl.u64 = CVMX_READ_CSR(rst_ctl_reg);
  1097. ep_mode = ((OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)) ?
  1098. (mio_rst_ctl.s.prtmode != 1) :
  1099. (!mio_rst_ctl.s.host_mode));
  1100. if (OCTEON_IS_MODEL(OCTEON_CN70XX) && pcie_port) {
  1101. cvmx_pemx_cfg_t pemx_cfg;
  1102. pemx_cfg.u64 = csr_rd(CVMX_PEMX_CFG(0));
  1103. if ((pemx_cfg.s.md & 3) == 2) {
  1104. printf("PCIe: Port %d in 1x4 mode.\n", pcie_port);
  1105. return -1;
  1106. }
  1107. }
  1108. if (ep_mode) {
  1109. printf("%d:PCIe: Port %d in endpoint mode.\n", node, pcie_port);
  1110. return -1;
  1111. }
  1112. /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be
  1113. * programmed
  1114. */
  1115. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
  1116. if (pcie_port) {
  1117. cvmx_ciu_qlm1_t ciu_qlm;
  1118. ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM1);
  1119. ciu_qlm.s.txbypass = 1;
  1120. ciu_qlm.s.txdeemph = 5;
  1121. ciu_qlm.s.txmargin = 0x17;
  1122. csr_wr(CVMX_CIU_QLM1, ciu_qlm.u64);
  1123. } else {
  1124. cvmx_ciu_qlm0_t ciu_qlm;
  1125. ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM0);
  1126. ciu_qlm.s.txbypass = 1;
  1127. ciu_qlm.s.txdeemph = 5;
  1128. ciu_qlm.s.txmargin = 0x17;
  1129. csr_wr(CVMX_CIU_QLM0, ciu_qlm.u64);
  1130. }
  1131. }
  1132. /* Bring the PCIe out of reset */
  1133. ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
  1134. /* After a chip reset the PCIe will also be in reset. If it
  1135. * isn't, most likely someone is trying to init it again
  1136. * without a proper PCIe reset.
  1137. */
  1138. if (ciu_soft_prst.s.soft_prst == 0) {
  1139. /* Reset the port */
  1140. ciu_soft_prst.s.soft_prst = 1;
  1141. CVMX_WRITE_CSR(ciu_soft_prst_reg, ciu_soft_prst.u64);
  1142. /* Read to make sure write happens */
  1143. ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
  1144. /* Keep PERST asserted for 2 ms */
  1145. udelay(2000);
  1146. }
  1147. /* Deassert PERST */
  1148. ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
  1149. ciu_soft_prst.s.soft_prst = 0;
  1150. CVMX_WRITE_CSR(ciu_soft_prst_reg, ciu_soft_prst.u64);
  1151. ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
  1152. /* Wait 1ms for PCIe reset to complete */
  1153. udelay(1000);
  1154. /* Set MPLL multiplier as per Errata 20669. */
  1155. if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
  1156. int qlm = __cvmx_pcie_get_qlm(0, pcie_port);
  1157. enum cvmx_qlm_mode mode;
  1158. int old_mult;
  1159. u64 meas_refclock = cvmx_qlm_measure_clock(qlm);
  1160. if (meas_refclock > 99000000 && meas_refclock < 101000000) {
  1161. old_mult = 35;
  1162. } else if (meas_refclock > 124000000 &&
  1163. meas_refclock < 126000000) {
  1164. old_mult = 56;
  1165. } else if (meas_refclock > 156000000 &&
  1166. meas_refclock < 156500000) {
  1167. old_mult = 45;
  1168. } else {
  1169. printf("%s: Invalid reference clock for qlm %d\n",
  1170. __func__, qlm);
  1171. return -1;
  1172. }
  1173. mode = cvmx_qlm_get_mode(qlm);
  1174. __cvmx_qlm_set_mult(qlm, 2500, old_mult);
  1175. /* Adjust mplls for both dlms when configured as pcie 1x4 */
  1176. if (mode == CVMX_QLM_MODE_PCIE && pcie_port == 0)
  1177. __cvmx_qlm_set_mult(qlm + 1, 2500, old_mult);
  1178. }
  1179. /*
  1180. * Check and make sure PCIe came out of reset. If it doesn't the board
  1181. * probably hasn't wired the clocks up and the interface should be
  1182. * skipped
  1183. */
  1184. if (CVMX_WAIT_FOR_FIELD64_NODE(node, rst_ctl_reg, cvmx_mio_rst_ctlx_t,
  1185. rst_done, ==, 1, 10000)) {
  1186. printf("%d:PCIe: Port %d stuck in reset, skipping.\n", node, pcie_port);
  1187. return -1;
  1188. }
  1189. /* Check BIST status */
  1190. pemx_bist_status.u64 = CVMX_READ_CSR(CVMX_PEMX_BIST_STATUS(pcie_port));
  1191. if (pemx_bist_status.u64)
  1192. printf("%d:PCIe: BIST FAILED for port %d (0x%016llx)\n", node, pcie_port,
  1193. CAST64(pemx_bist_status.u64));
  1194. pemx_bist_status2.u64 = CVMX_READ_CSR(CVMX_PEMX_BIST_STATUS2(pcie_port));
  1195. /*
  1196. * Errata PCIE-14766 may cause the lower 6 bits to be randomly set on
  1197. * CN63XXp1
  1198. */
  1199. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
  1200. pemx_bist_status2.u64 &= ~0x3full;
  1201. if (pemx_bist_status2.u64) {
  1202. printf("%d:PCIe: BIST2 FAILED for port %d (0x%016llx)\n",
  1203. node, pcie_port, CAST64(pemx_bist_status2.u64));
  1204. }
  1205. /* Initialize the config space CSRs */
  1206. __cvmx_pcie_rc_initialize_config_space(node, pcie_port);
  1207. /* Enable gen2 speed selection */
  1208. pciercx_cfg515.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
  1209. pciercx_cfg515.s.dsc = 1;
  1210. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
  1211. /* Bring the link up */
  1212. if (__cvmx_pcie_rc_initialize_link_gen2(node, pcie_port)) {
  1213. /* Some gen1 devices don't handle the gen 2 training correctly.
  1214. * Disable gen2 and try again with only gen1
  1215. */
  1216. cvmx_pciercx_cfg031_t pciercx_cfg031;
  1217. pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
  1218. pciercx_cfg031.s.mls = 1;
  1219. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
  1220. if (__cvmx_pcie_rc_initialize_link_gen2(node, pcie_port)) {
  1221. printf("PCIe: Link timeout on port %d, probably the slot is empty\n",
  1222. pcie_port);
  1223. return -1;
  1224. }
  1225. }
  1226. __cvmx_pcie_sli_config(node, pcie_port);
  1227. /* Display the link status */
  1228. pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  1229. printf("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port,
  1230. pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
  1231. pcie_link_initialized[node][pcie_port] = true;
  1232. return 0;
  1233. }
  1234. /**
  1235. * @INTERNAL
  1236. * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
  1237. * port from reset to a link up state. Software can then begin
  1238. * configuring the rest of the link.
  1239. *
  1240. * @param node node
  1241. * @param pcie_port PCIe port to initialize
  1242. *
  1243. * Return: Zero on success
  1244. */
  1245. static int __cvmx_pcie_rc_initialize_link_gen2_v3(int node, int pcie_port)
  1246. {
  1247. u8 ltssm_history[LTSSM_HISTORY_SIZE];
  1248. int ltssm_history_loc;
  1249. cvmx_pemx_ctl_status_t pem_ctl_status;
  1250. cvmx_pciercx_cfg006_t pciercx_cfg006;
  1251. cvmx_pciercx_cfg031_t pciercx_cfg031;
  1252. cvmx_pciercx_cfg032_t pciercx_cfg032;
  1253. cvmx_pciercx_cfg068_t pciercx_cfg068;
  1254. cvmx_pciercx_cfg448_t pciercx_cfg448;
  1255. cvmx_pciercx_cfg515_t pciercx_cfg515;
  1256. int max_gen, max_width;
  1257. u64 hold_time;
  1258. u64 bounce_allow_time;
  1259. u64 timeout, good_time, current_time;
  1260. int neg_gen, neg_width, bus, dev_gen, dev_width;
  1261. unsigned int cap, cap_next;
  1262. int ltssm_state, desired_gen;
  1263. int desired_width;
  1264. int i, need_speed_change, need_lane_change;
  1265. int do_retry_speed = 0;
  1266. int link_up = 0, is_loop_done = 0;
  1267. if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_PEMX_ON(pcie_port), cvmx_pemx_on_t, pemoor, ==, 1,
  1268. 100000)) {
  1269. printf("N%d:PCIe: Port %d PEM not on, skipping\n", node, pcie_port);
  1270. return -1;
  1271. }
  1272. /* Record starting LTSSM state for debug */
  1273. memset(ltssm_history, -1, sizeof(ltssm_history));
  1274. ltssm_history[0] = __cvmx_pcie_rc_get_ltssm_state(node, pcie_port);
  1275. ltssm_history_loc = 0;
  1276. pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port,
  1277. CVMX_PCIERCX_CFG031(pcie_port));
  1278. /* Max speed of PEM from config (1-3) */
  1279. max_gen = pciercx_cfg031.s.mls;
  1280. /* Max lane width of PEM (1-3) */
  1281. max_width = pciercx_cfg031.s.mlw;
  1282. #ifdef DEBUG_PCIE
  1283. printf("N%d.PCIe%d: Link supports up to %d lanes, speed gen%d\n",
  1284. node, pcie_port, max_width, max_gen);
  1285. #endif
  1286. /* Bring up the link */
  1287. #ifdef DEBUG_PCIE
  1288. printf("N%d.PCIe%d: Enabling the link\n", node, pcie_port);
  1289. #endif
  1290. pem_ctl_status.u64 = CVMX_READ_CSR(CVMX_PEMX_CTL_STATUS(pcie_port));
  1291. pem_ctl_status.s.lnk_enb = 1;
  1292. CVMX_WRITE_CSR(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
  1293. /*
  1294. * Configure SLI after enabling PCIe link. Is required for reading
  1295. * PCIe card capabilities.
  1296. */
  1297. __cvmx_pcie_sli_config(node, pcie_port);
  1298. /*
  1299. * After the link is enabled no prints until link up or error,
  1300. * Otherwise will miss link state captures
  1301. */
  1302. retry_speed:
  1303. /* Clear RC Correctable Error Status Register */
  1304. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG068(pcie_port), -1);
  1305. /* Wait for the link to come up and link training to be complete */
  1306. #ifdef DEBUG_PCIE
  1307. printf("N%d.PCIe%d: Waiting for link\n", node, pcie_port);
  1308. #endif
  1309. /* Timeout of 2 secs */
  1310. timeout = get_timer(0) + 2000;
  1311. /* Records when the link first went good */
  1312. good_time = 0;
  1313. do {
  1314. pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  1315. /*
  1316. * Errata PEM-31375 PEM RSL access to PCLK registers can
  1317. * timeout during speed change. Check for temporary hardware
  1318. * timeout, and rety if happens
  1319. */
  1320. if (pciercx_cfg032.u32 == 0xffffffff)
  1321. continue;
  1322. /* Record LTSSM state for debug */
  1323. ltssm_state = __cvmx_pcie_rc_get_ltssm_state(node, pcie_port);
  1324. if (ltssm_history[ltssm_history_loc] != ltssm_state) {
  1325. ltssm_history_loc = (ltssm_history_loc + 1) & (LTSSM_HISTORY_SIZE - 1);
  1326. ltssm_history[ltssm_history_loc] = ltssm_state;
  1327. }
  1328. /* Check if the link is up */
  1329. // current_time = cvmx_get_cycle();
  1330. current_time = get_timer(0);
  1331. link_up = (pciercx_cfg032.s.dlla && !pciercx_cfg032.s.lt);
  1332. if (link_up) {
  1333. /* Is this the first link up? */
  1334. if (!good_time) {
  1335. /* Mark the time when the link transitioned to good */
  1336. good_time = current_time;
  1337. } else {
  1338. /* Check for a link error */
  1339. pciercx_cfg068.u32 = CVMX_PCIE_CFGX_READ(
  1340. pcie_port, CVMX_PCIERCX_CFG068(pcie_port));
  1341. if (pciercx_cfg068.s.res) {
  1342. /*
  1343. * Ignore errors before we've been
  1344. * stable for bounce_allow_time
  1345. */
  1346. if (good_time + bounce_allow_time <=
  1347. current_time) {
  1348. #ifdef DEBUG_PCIE
  1349. printf("N%d.PCIe%d: Link errors after link up\n",
  1350. node, pcie_port);
  1351. #endif
  1352. /* Link error, signal a retry */
  1353. return 1;
  1354. }
  1355. /*
  1356. * Clear RC Correctable Error
  1357. * Status Register
  1358. */
  1359. CVMX_PCIE_CFGX_WRITE(pcie_port,
  1360. CVMX_PCIERCX_CFG068(pcie_port),
  1361. -1);
  1362. #ifdef DEBUG_PCIE
  1363. printf("N%d.PCIe%d: Ignored error during settling time\n",
  1364. node, pcie_port);
  1365. #endif
  1366. }
  1367. }
  1368. } else if (good_time) {
  1369. if (good_time + bounce_allow_time <= current_time) {
  1370. /*
  1371. * We allow bounces for bounce_allow_time after
  1372. * the link is good. Once this time passes any
  1373. * bounce requires a retry
  1374. */
  1375. #ifdef DEBUG_PCIE
  1376. printf("N%d.PCIe%d: Link bounce detected\n",
  1377. node, pcie_port);
  1378. #endif
  1379. return 1; /* Link bounce, signal a retry */
  1380. }
  1381. #ifdef DEBUG_PCIE
  1382. printf("N%d.PCIe%d: Ignored bounce during settling time\n",
  1383. node, pcie_port);
  1384. #endif
  1385. }
  1386. /* Determine if we've hit the timeout */
  1387. is_loop_done = (current_time >= timeout);
  1388. /*
  1389. * Determine if we've had a good link for the required hold
  1390. * time
  1391. */
  1392. is_loop_done |= link_up && (good_time + hold_time <=
  1393. current_time);
  1394. } while (!is_loop_done);
  1395. /* Trace the LTSSM state */
  1396. #ifdef DEBUG_PCIE
  1397. printf("N%d.PCIe%d: LTSSM History\n", node, pcie_port);
  1398. #endif
  1399. for (i = 0; i < LTSSM_HISTORY_SIZE; i++) {
  1400. ltssm_history_loc = (ltssm_history_loc + 1) & (LTSSM_HISTORY_SIZE - 1);
  1401. #ifdef DEBUG_PCIE
  1402. if (ltssm_history[ltssm_history_loc] != 0xff)
  1403. printf("N%d.PCIe%d: %s\n", node, pcie_port,
  1404. cvmx_pcie_get_ltssm_string(ltssm_history[ltssm_history_loc]));
  1405. #endif
  1406. }
  1407. if (!link_up) {
  1408. ltssm_state = __cvmx_pcie_rc_get_ltssm_state(node, pcie_port);
  1409. #ifdef DEBUG_PCIE
  1410. printf("N%d.PCIe%d: Link down, Data link layer %s(DLLA=%d), Link training %s(LT=%d), LTSSM %s\n",
  1411. node, pcie_port, pciercx_cfg032.s.dlla ? "active" : "down",
  1412. pciercx_cfg032.s.dlla, pciercx_cfg032.s.lt ? "active" : "complete",
  1413. pciercx_cfg032.s.lt, cvmx_pcie_get_ltssm_string(ltssm_state));
  1414. #endif
  1415. return 1; /* Link down, signal a retry */
  1416. }
  1417. /* Report the negotiated link speed and width */
  1418. neg_gen = pciercx_cfg032.s.ls; /* Current speed of PEM (1-3) */
  1419. neg_width = pciercx_cfg032.s.nlw; /* Current lane width of PEM (1-8) */
  1420. #ifdef DEBUG_PCIE
  1421. printf("N%d.PCIe%d: Link negotiated %d lanes, speed gen%d\n", node, pcie_port, neg_width,
  1422. neg_gen);
  1423. #endif
  1424. /* Determine PCIe bus number the directly attached device uses */
  1425. pciercx_cfg006.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
  1426. bus = pciercx_cfg006.s.sbnum;
  1427. /* The SLI has to be initialized so we can read the downstream devices */
  1428. dev_gen = 1; /* Device max speed (1-3) */
  1429. dev_width = 1; /* Device max lane width (1-16) */
  1430. #ifdef DEBUG_PCIE
  1431. printf("N%d.PCIe%d: Reading Bus %d device max speed and width\n", node, pcie_port, bus);
  1432. #endif
  1433. /*
  1434. * Here is the second part of the config retry changes. Wait for 700ms
  1435. * after setting up the link before continuing. PCIe says the devices
  1436. * may need up to 900ms to come up. 700ms plus 200ms from above gives
  1437. * us a total of 900ms
  1438. */
  1439. udelay(PCIE_DEVICE_READY_WAIT_DELAY_MICROSECONDS);
  1440. /* Read PCI capability pointer at offset 0x34 of target */
  1441. cap = cvmx_pcie_config_read32_retry(node, pcie_port, bus, 0, 0, 0x34);
  1442. /* Check if we were able to read capabilities pointer */
  1443. if (cap == 0xffffffff)
  1444. return 1; /* Signal retry needed */
  1445. /* Read device max speed and width */
  1446. cap_next = cap & 0xff;
  1447. while (cap_next) {
  1448. cap = cvmx_pcie_config_read32_retry(node, pcie_port, bus,
  1449. 0, 0, cap_next);
  1450. if (cap == 0xffffffff)
  1451. return 1; /* Signal retry needed */
  1452. /* Is this a PCIe capability (0x10)? */
  1453. if ((cap & 0xff) == 0x10) {
  1454. #ifdef DEBUG_PCIE
  1455. printf("N%d.PCIe%d: Found PCIe capability at offset 0x%x\n",
  1456. node, pcie_port, cap_next);
  1457. #endif
  1458. /* Offset 0xc contains the max link info */
  1459. cap = cvmx_pcie_config_read32_retry(node, pcie_port, bus, 0, 0,
  1460. cap_next + 0xc);
  1461. if (cap == 0xffffffff)
  1462. return 1; /* Signal retry needed */
  1463. dev_gen = cap & 0xf; /* Max speed of PEM from config (1-3) */
  1464. dev_width = (cap >> 4) & 0x3f; /* Max lane width of PEM (1-16) */
  1465. #ifdef DEBUG_PCIE
  1466. printf("N%d.PCIe%d: Device supports %d lanes, speed gen%d\n", node,
  1467. pcie_port, dev_width, dev_gen);
  1468. #endif
  1469. break;
  1470. }
  1471. /* Move to next capability */
  1472. cap_next = (cap >> 8) & 0xff;
  1473. }
  1474. /*
  1475. * Desired link speed and width is either limited by the device or our
  1476. * PEM configuration. Choose the most restrictive limit
  1477. */
  1478. desired_gen = (dev_gen < max_gen) ? dev_gen : max_gen;
  1479. desired_width = (dev_width < max_width) ? dev_width : max_width;
  1480. /*
  1481. * We need a change if we don't match the desired speed or width.
  1482. * Note that we allow better than expected in case the device lied
  1483. * about its capabilities
  1484. */
  1485. need_speed_change = (neg_gen < desired_gen);
  1486. need_lane_change = (neg_width < desired_width);
  1487. if (need_lane_change) {
  1488. /* We didn't get the maximum number of lanes */
  1489. #ifdef DEBUG_PCIE
  1490. printf("N%d.PCIe%d: Link width (%d) less that supported (%d)\n",
  1491. node, pcie_port, neg_width, desired_width);
  1492. #endif
  1493. return 2; /* Link wrong width, signal a retry */
  1494. } else if (need_speed_change) {
  1495. if (do_retry_speed) {
  1496. #ifdef DEBUG_PCIE
  1497. printf("N%d.PCIe%d: Link speed (gen%d) less that supported (gen%d)\n", node,
  1498. pcie_port, neg_gen, desired_gen);
  1499. #endif
  1500. return 1; /* Link at width, but speed low. Request a retry */
  1501. }
  1502. /* We didn't get the maximum speed. Request a speed change */
  1503. #ifdef DEBUG_PCIE
  1504. printf("N%d.PCIe%d: Link speed (gen%d) less that supported (gen%d), requesting a speed change\n",
  1505. node, pcie_port, neg_gen, desired_gen);
  1506. #endif
  1507. pciercx_cfg515.u32 =
  1508. CVMX_PCIE_CFGX_READ(pcie_port,
  1509. CVMX_PCIERCX_CFG515(pcie_port));
  1510. pciercx_cfg515.s.dsc = 1;
  1511. CVMX_PCIE_CFGX_WRITE(pcie_port,
  1512. CVMX_PCIERCX_CFG515(pcie_port),
  1513. pciercx_cfg515.u32);
  1514. mdelay(100);
  1515. do_retry_speed = true;
  1516. goto retry_speed;
  1517. } else {
  1518. #ifdef DEBUG_PCIE
  1519. printf("N%d.PCIe%d: Link at best speed and width\n",
  1520. node, pcie_port);
  1521. #endif
  1522. /* For gen3 links check if we are getting errors over the link */
  1523. if (neg_gen == 3) {
  1524. /* Read RC Correctable Error Status Register */
  1525. pciercx_cfg068.u32 =
  1526. CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG068(pcie_port));
  1527. if (pciercx_cfg068.s.res) {
  1528. #ifdef DEBUG_PCIE
  1529. printf("N%d.PCIe%d: Link reporting error status\n", node,
  1530. pcie_port);
  1531. #endif
  1532. return 1; /* Getting receiver errors, request a retry */
  1533. }
  1534. }
  1535. return 0; /* Link at correct speed and width */
  1536. }
  1537. /* Update the Replay Time Limit. Empirically, some PCIe devices take a
  1538. * little longer to respond than expected under load. As a workaround
  1539. * for this we configure the Replay Time Limit to the value expected
  1540. * for a 512 byte MPS instead of our actual 256 byte MPS. The numbers
  1541. * below are directly from the PCIe spec table 3-4
  1542. */
  1543. pciercx_cfg448.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
  1544. switch (pciercx_cfg032.s.nlw) {
  1545. case 1: /* 1 lane */
  1546. pciercx_cfg448.s.rtl = 1677;
  1547. break;
  1548. case 2: /* 2 lanes */
  1549. pciercx_cfg448.s.rtl = 867;
  1550. break;
  1551. case 4: /* 4 lanes */
  1552. pciercx_cfg448.s.rtl = 462;
  1553. break;
  1554. case 8: /* 8 lanes */
  1555. pciercx_cfg448.s.rtl = 258;
  1556. break;
  1557. }
  1558. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
  1559. return 0;
  1560. }
  1561. static int __cvmx_pcie_rc_initialize_gen2_v3(int pcie_port)
  1562. {
  1563. cvmx_rst_ctlx_t rst_ctl;
  1564. cvmx_rst_soft_prstx_t rst_soft_prst;
  1565. cvmx_pciercx_cfg031_t pciercx_cfg031;
  1566. cvmx_pciercx_cfg032_t pciercx_cfg032;
  1567. cvmx_pciercx_cfg038_t pciercx_cfg038;
  1568. cvmx_pciercx_cfg040_t pciercx_cfg040;
  1569. cvmx_pciercx_cfg515_t pciercx_cfg515;
  1570. cvmx_pciercx_cfg548_t pciercx_cfg548;
  1571. cvmx_pemx_bist_status_t pemx_bist_status;
  1572. u64 rst_soft_prst_reg;
  1573. int qlm;
  1574. int node = (pcie_port >> 4) & 0x3;
  1575. bool requires_pem_reset = 0;
  1576. enum cvmx_qlm_mode mode = CVMX_QLM_MODE_DISABLED;
  1577. int retry_count = 0;
  1578. int result = 0;
  1579. pcie_port &= 0x3;
  1580. /* Assume link down until proven up */
  1581. pcie_link_initialized[node][pcie_port] = false;
  1582. /* Attempt link initialization up to 3 times */
  1583. while (retry_count <= MAX_RETRIES) {
  1584. #ifdef DEBUG_PCIE
  1585. if (retry_count)
  1586. printf("N%d:PCIE%d: Starting link retry %d\n", node, pcie_port,
  1587. retry_count);
  1588. #endif
  1589. if (pcie_port >= CVMX_PCIE_PORTS) {
  1590. #ifdef DEBUG_PCIE
  1591. printf("Invalid PCIe%d port\n", pcie_port);
  1592. #endif
  1593. return -1;
  1594. }
  1595. qlm = __cvmx_pcie_get_qlm(node, pcie_port);
  1596. if (qlm < 0)
  1597. return -1;
  1598. mode = cvmx_qlm_get_mode(qlm);
  1599. if (__cvmx_pcie_check_pcie_port(node, pcie_port, mode))
  1600. return -1;
  1601. rst_soft_prst_reg = CVMX_RST_SOFT_PRSTX(pcie_port);
  1602. rst_ctl.u64 = CVMX_READ_CSR(CVMX_RST_CTLX(pcie_port));
  1603. if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
  1604. CVMX_WRITE_CSR(CVMX_DTX_PEMX_SELX(0, pcie_port), 0x17);
  1605. CVMX_WRITE_CSR(CVMX_DTX_PEMX_SELX(1, pcie_port), 0);
  1606. }
  1607. if (!rst_ctl.s.host_mode) {
  1608. printf("N%d:PCIE: Port %d in endpoint mode.\n",
  1609. node, pcie_port);
  1610. return -1;
  1611. }
  1612. /* Bring the PCIe out of reset */
  1613. rst_soft_prst.u64 = CVMX_READ_CSR(rst_soft_prst_reg);
  1614. /*
  1615. * After a chip reset the PCIe will also be in reset. If it
  1616. * isn't, most likely someone is trying to init it again
  1617. * without a proper PCIe reset.
  1618. */
  1619. if (rst_soft_prst.s.soft_prst == 0) {
  1620. /* Disable the MAC controller before resetting */
  1621. __cvmx_pcie_config_pemon(node, pcie_port, 0);
  1622. /* Reset the port */
  1623. rst_soft_prst.s.soft_prst = 1;
  1624. CVMX_WRITE_CSR(rst_soft_prst_reg, rst_soft_prst.u64);
  1625. /* Read to make sure write happens */
  1626. rst_soft_prst.u64 = CVMX_READ_CSR(rst_soft_prst_reg);
  1627. /* Keep PERST asserted for 2 ms */
  1628. udelay(2000);
  1629. /* Reset GSER_PHY to put in a clean state */
  1630. __cvmx_pcie_gser_phy_config(node, pcie_port, qlm);
  1631. requires_pem_reset = 1;
  1632. /* Enable MAC controller before taking pcie out of reset */
  1633. __cvmx_pcie_config_pemon(node, pcie_port, 1);
  1634. }
  1635. /* Deassert PERST */
  1636. rst_soft_prst.u64 = CVMX_READ_CSR(rst_soft_prst_reg);
  1637. rst_soft_prst.s.soft_prst = 0;
  1638. CVMX_WRITE_CSR(rst_soft_prst_reg, rst_soft_prst.u64);
  1639. rst_soft_prst.u64 = CVMX_READ_CSR(rst_soft_prst_reg);
  1640. /* Check if PLLs are locked after GSER_PHY reset. */
  1641. if (requires_pem_reset) {
  1642. cvmx_pemx_cfg_t pemx_cfg;
  1643. pemx_cfg.u64 = csr_rd(CVMX_PEMX_CFG(pcie_port));
  1644. if (CVMX_WAIT_FOR_FIELD64(CVMX_GSERX_QLM_STAT(qlm), cvmx_gserx_qlm_stat_t,
  1645. rst_rdy, ==, 1, 10000)) {
  1646. printf("QLM%d: Timeout waiting for GSERX_QLM_STAT[rst_rdy]\n", qlm);
  1647. return -1;
  1648. }
  1649. if (pemx_cfg.cn78xx.lanes8 &&
  1650. (CVMX_WAIT_FOR_FIELD64(CVMX_GSERX_QLM_STAT(qlm + 1),
  1651. cvmx_gserx_qlm_stat_t, rst_rdy, ==, 1, 10000))) {
  1652. printf("QLM%d: Timeout waiting for GSERX_QLM_STAT[rst_rdy]\n",
  1653. qlm + 1);
  1654. return -1;
  1655. }
  1656. }
  1657. /* Wait 1ms for PCIe reset to complete */
  1658. udelay(1000);
  1659. /*
  1660. * Check and make sure PCIe came out of reset. If it doesn't
  1661. * the board probably hasn't wired the clocks up and the
  1662. * interface should be skipped
  1663. */
  1664. if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_RST_CTLX(pcie_port),
  1665. cvmx_rst_ctlx_t,
  1666. rst_done, ==, 1, 10000)) {
  1667. printf("N%d:PCIE: Port %d stuck in reset, skipping.\n", node, pcie_port);
  1668. return -1;
  1669. }
  1670. /* Check BIST status */
  1671. pemx_bist_status.u64 = CVMX_READ_CSR(CVMX_PEMX_BIST_STATUS(pcie_port));
  1672. if (pemx_bist_status.u64)
  1673. printf("N%d:PCIE: BIST FAILED for port %d (0x%016llx)\n", node, pcie_port,
  1674. CAST64(pemx_bist_status.u64));
  1675. /* Initialize the config space CSRs */
  1676. #ifdef DEBUG_PCIE
  1677. printf("N%d:PCIE%d Initialize Config Space\n", node, pcie_port);
  1678. #endif
  1679. __cvmx_pcie_rc_initialize_config_space(node, pcie_port);
  1680. /* Enable gen2 speed selection */
  1681. pciercx_cfg515.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
  1682. pciercx_cfg515.s.dsc = 1;
  1683. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
  1684. /* Do the link retries on the PCIe interface */
  1685. if (retry_count == MAX_RETRIES) {
  1686. /*
  1687. * This has to be done AFTER the QLM/PHY interface
  1688. * initialized
  1689. */
  1690. pciercx_cfg031.u32 =
  1691. CVMX_PCIE_CFGX_READ(pcie_port,
  1692. CVMX_PCIERCX_CFG031(pcie_port));
  1693. /*
  1694. * Drop speed to gen2 if link bouncing
  1695. * Result = -1 PEM in reset
  1696. * Result = 0: link speed and width ok no retry needed
  1697. * Result = 1: link errors or speed change needed
  1698. * Result = 2: lane width error
  1699. */
  1700. if (pciercx_cfg031.s.mls == 3 && result != 2) {
  1701. #ifdef DEBUG_PCIE
  1702. printf("N%d:PCIE%d: Dropping speed to gen2\n", node, pcie_port);
  1703. #endif
  1704. pciercx_cfg031.s.mls = 2;
  1705. CVMX_PCIE_CFGX_WRITE(pcie_port,
  1706. CVMX_PCIERCX_CFG031(pcie_port),
  1707. pciercx_cfg031.u32);
  1708. /* Set the target link speed */
  1709. pciercx_cfg040.u32 = CVMX_PCIE_CFGX_READ(
  1710. pcie_port, CVMX_PCIERCX_CFG040(pcie_port));
  1711. pciercx_cfg040.s.tls = 2;
  1712. CVMX_PCIE_CFGX_WRITE(pcie_port,
  1713. CVMX_PCIERCX_CFG040(pcie_port),
  1714. pciercx_cfg040.u32);
  1715. }
  1716. }
  1717. /* Bring the link up */
  1718. result = __cvmx_pcie_rc_initialize_link_gen2_v3(node, pcie_port);
  1719. if (result == 0) {
  1720. #ifdef DEBUG_PCIE
  1721. printf("N%d:PCIE%d: Link does not need a retry\n", node, pcie_port);
  1722. #endif
  1723. break;
  1724. } else if (result > 0) {
  1725. if (retry_count >= MAX_RETRIES) {
  1726. int link_up;
  1727. #ifdef DEBUG_PCIE
  1728. printf("N%d:PCIE%d: Link requested a retry, but hit the max retries\n",
  1729. node, pcie_port);
  1730. #endif
  1731. /* If the link is down, report failure */
  1732. pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(
  1733. pcie_port,
  1734. CVMX_PCIERCX_CFG032(pcie_port));
  1735. link_up = (pciercx_cfg032.s.dlla && !pciercx_cfg032.s.lt);
  1736. if (!link_up)
  1737. result = -1;
  1738. }
  1739. #ifdef DEBUG_PCIE
  1740. else
  1741. printf("N%d.PCIE%d: Link requested a retry\n", node, pcie_port);
  1742. #endif
  1743. }
  1744. if (result < 0) {
  1745. int ltssm_state = __cvmx_pcie_rc_get_ltssm_state(node, pcie_port);
  1746. printf("N%d:PCIE%d: Link timeout, probably the slot is empty (LTSSM %s)\n",
  1747. node, pcie_port, cvmx_pcie_get_ltssm_string(ltssm_state));
  1748. return -1;
  1749. }
  1750. retry_count++;
  1751. }
  1752. pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  1753. /*
  1754. * Errata PEM-28816: Link retrain initiated at GEN1 can cause PCIE
  1755. * link to hang. For Gen1 links we must disable equalization
  1756. */
  1757. if (pciercx_cfg032.s.ls == 1) {
  1758. #ifdef DEBUG_PCIE
  1759. printf("N%d:PCIE%d: Disabling equalization for GEN1 Link\n", node, pcie_port);
  1760. #endif
  1761. pciercx_cfg548.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG548(pcie_port));
  1762. pciercx_cfg548.s.ed = 1;
  1763. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG548(pcie_port), pciercx_cfg548.u32);
  1764. }
  1765. /* Errata PCIE-29440: Atomic operations to work properly */
  1766. pciercx_cfg038.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG038(pcie_port));
  1767. pciercx_cfg038.s.atom_op_eb = 0;
  1768. pciercx_cfg038.s.atom_op = 1;
  1769. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG038(pcie_port), pciercx_cfg038.u32);
  1770. /* Errata PCIE-29566 PEM Link Hangs after going into L1 */
  1771. pciercx_cfg548.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG548(pcie_port));
  1772. pciercx_cfg548.s.grizdnc = 0;
  1773. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG548(pcie_port), pciercx_cfg548.u32);
  1774. if (result < 0)
  1775. return result;
  1776. /* Display the link status */
  1777. pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  1778. printf("N%d:PCIe: Port %d link active, %d lanes, speed gen%d\n", node, pcie_port,
  1779. pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
  1780. pcie_link_initialized[node][pcie_port] = true;
  1781. return 0;
  1782. }
  1783. /**
  1784. * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
  1785. *
  1786. * @param pcie_port PCIe port to initialize for a node
  1787. *
  1788. * Return: Zero on success
  1789. */
  1790. int cvmx_pcie_rc_initialize(int pcie_port)
  1791. {
  1792. int result;
  1793. if (OCTEON_IS_OCTEON2() || OCTEON_IS_MODEL(OCTEON_CN70XX))
  1794. result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
  1795. else
  1796. result = __cvmx_pcie_rc_initialize_gen2_v3(pcie_port);
  1797. if (result == 0)
  1798. cvmx_error_enable_group(CVMX_ERROR_GROUP_PCI, pcie_port);
  1799. return result;
  1800. }
  1801. /**
  1802. * Shutdown a PCIe port and put it in reset
  1803. *
  1804. * @param pcie_port PCIe port to shutdown for a node
  1805. *
  1806. * Return: Zero on success
  1807. */
  1808. int cvmx_pcie_rc_shutdown(int pcie_port)
  1809. {
  1810. u64 ciu_soft_prst_reg;
  1811. cvmx_ciu_soft_prst_t ciu_soft_prst;
  1812. int node;
  1813. /* Shutdown only if PEM is in RC mode */
  1814. if (!cvmx_pcie_is_host_mode(pcie_port))
  1815. return -1;
  1816. node = (pcie_port >> 4) & 0x3;
  1817. pcie_port &= 0x3;
  1818. cvmx_error_disable_group(CVMX_ERROR_GROUP_PCI, pcie_port);
  1819. /* Wait for all pending operations to complete */
  1820. if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_PEMX_CPL_LUT_VALID(pcie_port),
  1821. cvmx_pemx_cpl_lut_valid_t, tag, ==,
  1822. 0, 2000))
  1823. debug("PCIe: Port %d shutdown timeout\n", pcie_port);
  1824. if (OCTEON_IS_OCTEON3()) {
  1825. ciu_soft_prst_reg = CVMX_RST_SOFT_PRSTX(pcie_port);
  1826. } else {
  1827. ciu_soft_prst_reg = (pcie_port) ? CVMX_CIU_SOFT_PRST1 :
  1828. CVMX_CIU_SOFT_PRST;
  1829. }
  1830. /* Force reset */
  1831. ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
  1832. ciu_soft_prst.s.soft_prst = 1;
  1833. CVMX_WRITE_CSR(ciu_soft_prst_reg, ciu_soft_prst.u64);
  1834. return 0;
  1835. }
  1836. /**
  1837. * @INTERNAL
  1838. * Build a PCIe config space request address for a device
  1839. *
  1840. * @param node node
  1841. * @param port PCIe port (relative to the node) to access
  1842. * @param bus Sub bus
  1843. * @param dev Device ID
  1844. * @param fn Device sub function
  1845. * @param reg Register to access
  1846. *
  1847. * Return: 64bit Octeon IO address
  1848. */
  1849. static uint64_t __cvmx_pcie_build_config_addr(int node, int port, int bus, int dev, int fn, int reg)
  1850. {
  1851. cvmx_pcie_address_t pcie_addr;
  1852. cvmx_pciercx_cfg006_t pciercx_cfg006;
  1853. pciercx_cfg006.u32 = cvmx_pcie_cfgx_read_node(node, port,
  1854. CVMX_PCIERCX_CFG006(port));
  1855. if (bus <= pciercx_cfg006.s.pbnum && dev != 0)
  1856. return 0;
  1857. pcie_addr.u64 = 0;
  1858. pcie_addr.config.upper = 2;
  1859. pcie_addr.config.io = 1;
  1860. pcie_addr.config.did = 3;
  1861. pcie_addr.config.subdid = 1;
  1862. pcie_addr.config.node = node;
  1863. pcie_addr.config.es = _CVMX_PCIE_ES;
  1864. pcie_addr.config.port = port;
  1865. /* Always use config type 0 */
  1866. if (pciercx_cfg006.s.pbnum == 0)
  1867. pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum + 1);
  1868. else
  1869. pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
  1870. pcie_addr.config.bus = bus;
  1871. pcie_addr.config.dev = dev;
  1872. pcie_addr.config.func = fn;
  1873. pcie_addr.config.reg = reg;
  1874. return pcie_addr.u64;
  1875. }
  1876. /**
  1877. * Read 8bits from a Device's config space
  1878. *
  1879. * @param pcie_port PCIe port the device is on
  1880. * @param bus Sub bus
  1881. * @param dev Device ID
  1882. * @param fn Device sub function
  1883. * @param reg Register to access
  1884. *
  1885. * Return: Result of the read
  1886. */
  1887. uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg)
  1888. {
  1889. u64 address;
  1890. int node = (pcie_port >> 4) & 0x3;
  1891. pcie_port &= 0x3;
  1892. address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
  1893. if (address)
  1894. return cvmx_read64_uint8(address);
  1895. else
  1896. return 0xff;
  1897. }
  1898. /**
  1899. * Read 16bits from a Device's config space
  1900. *
  1901. * @param pcie_port PCIe port the device is on
  1902. * @param bus Sub bus
  1903. * @param dev Device ID
  1904. * @param fn Device sub function
  1905. * @param reg Register to access
  1906. *
  1907. * Return: Result of the read
  1908. */
  1909. uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg)
  1910. {
  1911. u64 address;
  1912. int node = (pcie_port >> 4) & 0x3;
  1913. pcie_port &= 0x3;
  1914. address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
  1915. if (address)
  1916. return le16_to_cpu(cvmx_read64_uint16(address));
  1917. else
  1918. return 0xffff;
  1919. }
  1920. static uint32_t __cvmx_pcie_config_read32(int node, int pcie_port, int bus, int dev, int func,
  1921. int reg, int lst)
  1922. {
  1923. u64 address;
  1924. address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, func, reg);
  1925. if (lst) {
  1926. if (address && pcie_link_initialized[node][pcie_port])
  1927. return le32_to_cpu(cvmx_read64_uint32(address));
  1928. else
  1929. return 0xffffffff;
  1930. } else if (address) {
  1931. return le32_to_cpu(cvmx_read64_uint32(address));
  1932. } else {
  1933. return 0xffffffff;
  1934. }
  1935. }
  1936. /**
  1937. * Read 32bits from a Device's config space
  1938. *
  1939. * @param pcie_port PCIe port the device is on
  1940. * @param bus Sub bus
  1941. * @param dev Device ID
  1942. * @param fn Device sub function
  1943. * @param reg Register to access
  1944. *
  1945. * Return: Result of the read
  1946. */
  1947. uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg)
  1948. {
  1949. int node = (pcie_port >> 4) & 0x3;
  1950. pcie_port &= 0x3;
  1951. return __cvmx_pcie_config_read32(node, pcie_port, bus, dev, fn, reg,
  1952. pcie_link_initialized[node][pcie_port]);
  1953. }
  1954. /**
  1955. * Write 8bits to a Device's config space
  1956. *
  1957. * @param pcie_port PCIe port the device is on
  1958. * @param bus Sub bus
  1959. * @param dev Device ID
  1960. * @param fn Device sub function
  1961. * @param reg Register to access
  1962. * @param val Value to write
  1963. */
  1964. void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, uint8_t val)
  1965. {
  1966. u64 address;
  1967. int node = (pcie_port >> 4) & 0x3;
  1968. pcie_port &= 0x3;
  1969. address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
  1970. if (address)
  1971. cvmx_write64_uint8(address, val);
  1972. }
  1973. /**
  1974. * Write 16bits to a Device's config space
  1975. *
  1976. * @param pcie_port PCIe port the device is on
  1977. * @param bus Sub bus
  1978. * @param dev Device ID
  1979. * @param fn Device sub function
  1980. * @param reg Register to access
  1981. * @param val Value to write
  1982. */
  1983. void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, uint16_t val)
  1984. {
  1985. u64 address;
  1986. int node = (pcie_port >> 4) & 0x3;
  1987. pcie_port &= 0x3;
  1988. address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
  1989. if (address)
  1990. cvmx_write64_uint16(address, cpu_to_le16(val));
  1991. }
  1992. /**
  1993. * Write 32bits to a Device's config space
  1994. *
  1995. * @param pcie_port PCIe port the device is on
  1996. * @param bus Sub bus
  1997. * @param dev Device ID
  1998. * @param fn Device sub function
  1999. * @param reg Register to access
  2000. * @param val Value to write
  2001. */
  2002. void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, uint32_t val)
  2003. {
  2004. u64 address;
  2005. int node = (pcie_port >> 4) & 0x3;
  2006. pcie_port &= 0x3;
  2007. address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
  2008. if (address)
  2009. cvmx_write64_uint32(address, cpu_to_le32(val));
  2010. }
  2011. /**
  2012. * Read a PCIe config space register indirectly. This is used for
  2013. * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  2014. *
  2015. * @param pcie_port PCIe port to read from
  2016. * @param cfg_offset Address to read
  2017. *
  2018. * Return: Value read
  2019. */
  2020. uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
  2021. {
  2022. return cvmx_pcie_cfgx_read_node(0, pcie_port, cfg_offset);
  2023. }
  2024. uint32_t cvmx_pcie_cfgx_read_node(int node, int pcie_port, uint32_t cfg_offset)
  2025. {
  2026. cvmx_pemx_cfg_rd_t pemx_cfg_rd;
  2027. pemx_cfg_rd.u64 = 0;
  2028. pemx_cfg_rd.s.addr = cfg_offset;
  2029. CVMX_WRITE_CSR(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
  2030. pemx_cfg_rd.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG_RD(pcie_port));
  2031. return pemx_cfg_rd.s.data;
  2032. }
  2033. /**
  2034. * Write a PCIe config space register indirectly. This is used for
  2035. * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  2036. *
  2037. * @param pcie_port PCIe port to write to
  2038. * @param cfg_offset Address to write
  2039. * @param val Value to write
  2040. */
  2041. void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val)
  2042. {
  2043. cvmx_pcie_cfgx_write_node(0, pcie_port, cfg_offset, val);
  2044. }
  2045. void cvmx_pcie_cfgx_write_node(int node, int pcie_port, uint32_t cfg_offset, uint32_t val)
  2046. {
  2047. cvmx_pemx_cfg_wr_t pemx_cfg_wr;
  2048. pemx_cfg_wr.u64 = 0;
  2049. pemx_cfg_wr.s.addr = cfg_offset;
  2050. pemx_cfg_wr.s.data = val;
  2051. CVMX_WRITE_CSR(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
  2052. }
  2053. extern int cvmx_pcie_is_host_mode(int pcie_port);
  2054. /**
  2055. * Initialize a PCIe port for use in target(EP) mode.
  2056. *
  2057. * @param pcie_port PCIe port to initialize for a node
  2058. *
  2059. * Return: Zero on success
  2060. */
  2061. int cvmx_pcie_ep_initialize(int pcie_port)
  2062. {
  2063. int node = (pcie_port >> 4) & 0x3;
  2064. if (cvmx_pcie_is_host_mode(pcie_port))
  2065. return -1;
  2066. pcie_port &= 0x3;
  2067. /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be
  2068. * programmed
  2069. */
  2070. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
  2071. if (pcie_port) {
  2072. cvmx_ciu_qlm1_t ciu_qlm;
  2073. ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM1);
  2074. ciu_qlm.s.txbypass = 1;
  2075. ciu_qlm.s.txdeemph = 5;
  2076. ciu_qlm.s.txmargin = 0x17;
  2077. csr_wr(CVMX_CIU_QLM1, ciu_qlm.u64);
  2078. } else {
  2079. cvmx_ciu_qlm0_t ciu_qlm;
  2080. ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM0);
  2081. ciu_qlm.s.txbypass = 1;
  2082. ciu_qlm.s.txdeemph = 5;
  2083. ciu_qlm.s.txmargin = 0x17;
  2084. csr_wr(CVMX_CIU_QLM0, ciu_qlm.u64);
  2085. }
  2086. }
  2087. /* Enable bus master and memory */
  2088. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIEEPX_CFG001(pcie_port), 0x6);
  2089. /* Max Payload Size (PCIE*_CFG030[MPS]) */
  2090. /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
  2091. /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
  2092. /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
  2093. {
  2094. cvmx_pcieepx_cfg030_t pcieepx_cfg030;
  2095. pcieepx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIEEPX_CFG030(pcie_port));
  2096. pcieepx_cfg030.s.mps = MPS_CN6XXX;
  2097. pcieepx_cfg030.s.mrrs = MRRS_CN6XXX;
  2098. pcieepx_cfg030.s.ro_en = 1; /* Enable relaxed ordering. */
  2099. pcieepx_cfg030.s.ns_en = 1; /* Enable no snoop. */
  2100. pcieepx_cfg030.s.ce_en = 1; /* Correctable error reporting enable. */
  2101. pcieepx_cfg030.s.nfe_en = 1; /* Non-fatal error reporting enable. */
  2102. pcieepx_cfg030.s.fe_en = 1; /* Fatal error reporting enable. */
  2103. pcieepx_cfg030.s.ur_en = 1; /* Unsupported request reporting enable. */
  2104. CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIEEPX_CFG030(pcie_port), pcieepx_cfg030.u32);
  2105. }
  2106. /* Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
  2107. * PCIE*_CFG030[MPS]
  2108. */
  2109. /* Max Read Request Size (DPI_SLI_PRTX_CFG[MRRS]) must not
  2110. * exceed PCIE*_CFG030[MRRS]
  2111. */
  2112. cvmx_dpi_sli_prtx_cfg_t prt_cfg;
  2113. cvmx_sli_s2m_portx_ctl_t sli_s2m_portx_ctl;
  2114. prt_cfg.u64 = CVMX_READ_CSR(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
  2115. prt_cfg.s.mps = MPS_CN6XXX;
  2116. prt_cfg.s.mrrs = MRRS_CN6XXX;
  2117. /* Max outstanding load request. */
  2118. prt_cfg.s.molr = 32;
  2119. CVMX_WRITE_CSR(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
  2120. sli_s2m_portx_ctl.u64 = CVMX_READ_CSR(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
  2121. if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX) ||
  2122. OCTEON_IS_MODEL(OCTEON_CNF75XX)))
  2123. sli_s2m_portx_ctl.cn61xx.mrrs = MRRS_CN6XXX;
  2124. CVMX_WRITE_CSR(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
  2125. /* Setup Mem access SubDID 12 to access Host memory */
  2126. cvmx_sli_mem_access_subidx_t mem_access_subid;
  2127. mem_access_subid.u64 = 0;
  2128. mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
  2129. mem_access_subid.s.nmerge = 0; /* Merging is allowed in this window. */
  2130. mem_access_subid.s.esr = 0; /* Endian-swap for Reads. */
  2131. mem_access_subid.s.esw = 0; /* Endian-swap for Writes. */
  2132. mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
  2133. mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
  2134. /* PCIe Address Bits <63:34>. */
  2135. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  2136. mem_access_subid.cn68xx.ba = 0;
  2137. else
  2138. mem_access_subid.cn63xx.ba = 0;
  2139. CVMX_WRITE_CSR(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(12 + pcie_port * 4), mem_access_subid.u64);
  2140. return 0;
  2141. }
  2142. /**
  2143. * Wait for posted PCIe read/writes to reach the other side of
  2144. * the internal PCIe switch. This will insure that core
  2145. * read/writes are posted before anything after this function
  2146. * is called. This may be necessary when writing to memory that
  2147. * will later be read using the DMA/PKT engines.
  2148. *
  2149. * @param pcie_port PCIe port to wait for
  2150. */
  2151. void cvmx_pcie_wait_for_pending(int pcie_port)
  2152. {
  2153. cvmx_sli_data_out_cnt_t sli_data_out_cnt;
  2154. int a;
  2155. int b;
  2156. int c;
  2157. sli_data_out_cnt.u64 = csr_rd(CVMX_PEXP_SLI_DATA_OUT_CNT);
  2158. if (pcie_port) {
  2159. if (!sli_data_out_cnt.s.p1_fcnt)
  2160. return;
  2161. a = sli_data_out_cnt.s.p1_ucnt;
  2162. b = (a + sli_data_out_cnt.s.p1_fcnt - 1) & 0xffff;
  2163. } else {
  2164. if (!sli_data_out_cnt.s.p0_fcnt)
  2165. return;
  2166. a = sli_data_out_cnt.s.p0_ucnt;
  2167. b = (a + sli_data_out_cnt.s.p0_fcnt - 1) & 0xffff;
  2168. }
  2169. while (1) {
  2170. sli_data_out_cnt.u64 = csr_rd(CVMX_PEXP_SLI_DATA_OUT_CNT);
  2171. c = (pcie_port) ? sli_data_out_cnt.s.p1_ucnt :
  2172. sli_data_out_cnt.s.p0_ucnt;
  2173. if (a <= b) {
  2174. if (c < a || c > b)
  2175. return;
  2176. } else {
  2177. if (c > b && c < a)
  2178. return;
  2179. }
  2180. }
  2181. }
  2182. /**
  2183. * Returns if a PCIe port is in host or target mode.
  2184. *
  2185. * @param pcie_port PCIe port number (PEM number)
  2186. *
  2187. * Return: 0 if PCIe port is in target mode, !0 if in host mode.
  2188. */
  2189. int cvmx_pcie_is_host_mode(int pcie_port)
  2190. {
  2191. int node = (pcie_port >> 4) & 0x3;
  2192. cvmx_mio_rst_ctlx_t mio_rst_ctl;
  2193. pcie_port &= 0x3;
  2194. if (OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX)) {
  2195. cvmx_pemx_strap_t strap;
  2196. strap.u64 = CVMX_READ_CSR(CVMX_PEMX_STRAP(pcie_port));
  2197. return (strap.cn78xx.pimode == 3);
  2198. } else if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
  2199. cvmx_rst_ctlx_t rst_ctl;
  2200. rst_ctl.u64 = csr_rd(CVMX_RST_CTLX(pcie_port));
  2201. return !!rst_ctl.s.host_mode;
  2202. }
  2203. mio_rst_ctl.u64 = csr_rd(CVMX_MIO_RST_CTLX(pcie_port));
  2204. if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
  2205. return mio_rst_ctl.s.prtmode != 0;
  2206. else
  2207. return !!mio_rst_ctl.s.host_mode;
  2208. }