clock.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013-2020
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. /* Tegra210 Clock control functions */
  7. #include <common.h>
  8. #include <errno.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/cache.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sysctr.h>
  15. #include <asm/arch/tegra.h>
  16. #include <asm/arch-tegra/clk_rst.h>
  17. #include <asm/arch-tegra/timer.h>
  18. #include <div64.h>
  19. #include <fdtdec.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. /*
  23. * Clock types that we can use as a source. The Tegra210 has muxes for the
  24. * peripheral clocks, and in most cases there are four options for the clock
  25. * source. This gives us a clock 'type' and exploits what commonality exists
  26. * in the device.
  27. *
  28. * Letters are obvious, except for T which means CLK_M, and S which means the
  29. * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
  30. * datasheet) and PLL_M are different things. The former is the basic
  31. * clock supplied to the SOC from an external oscillator. The latter is the
  32. * memory clock PLL.
  33. *
  34. * See definitions in clock_id in the header file.
  35. */
  36. enum clock_type_id {
  37. CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
  38. CLOCK_TYPE_MCPA, /* and so on */
  39. CLOCK_TYPE_MCPT,
  40. CLOCK_TYPE_PCM,
  41. CLOCK_TYPE_PCMT,
  42. CLOCK_TYPE_PDCT,
  43. CLOCK_TYPE_ACPT,
  44. CLOCK_TYPE_ASPTE,
  45. CLOCK_TYPE_PDD2T,
  46. CLOCK_TYPE_PCST,
  47. CLOCK_TYPE_DP,
  48. CLOCK_TYPE_PC2CC3M,
  49. CLOCK_TYPE_PC2CC3S_T,
  50. CLOCK_TYPE_PC2CC3M_T,
  51. CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
  52. CLOCK_TYPE_MC2CC3P_A,
  53. CLOCK_TYPE_M,
  54. CLOCK_TYPE_MCPTM2C2C3,
  55. CLOCK_TYPE_PC2CC3T_S,
  56. CLOCK_TYPE_AC2CC3P_TS2,
  57. CLOCK_TYPE_PC01C00_C42C41TC40,
  58. CLOCK_TYPE_COUNT,
  59. CLOCK_TYPE_NONE = -1, /* invalid clock type */
  60. };
  61. enum {
  62. CLOCK_MAX_MUX = 8 /* number of source options for each clock */
  63. };
  64. /*
  65. * Clock source mux for each clock type. This just converts our enum into
  66. * a list of mux sources for use by the code.
  67. *
  68. * Note:
  69. * The extra column in each clock source array is used to store the mask
  70. * bits in its register for the source.
  71. */
  72. #define CLK(x) CLOCK_ID_ ## x
  73. static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
  74. { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
  75. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  76. MASK_BITS_31_30},
  77. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
  78. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  79. MASK_BITS_31_30},
  80. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  81. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  82. MASK_BITS_31_30},
  83. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
  84. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  85. MASK_BITS_31_30},
  86. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
  87. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  88. MASK_BITS_31_30},
  89. { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
  90. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  91. MASK_BITS_31_30},
  92. { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  93. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  94. MASK_BITS_31_30},
  95. { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
  96. CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
  97. MASK_BITS_31_29},
  98. { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE),
  99. CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
  100. MASK_BITS_31_29},
  101. { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
  102. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  103. MASK_BITS_31_28},
  104. /* CLOCK_TYPE_DP */
  105. { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  106. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  107. MASK_BITS_31_28},
  108. /* Additional clock types on Tegra114+ */
  109. /* CLOCK_TYPE_PC2CC3M */
  110. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  111. CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
  112. MASK_BITS_31_29},
  113. /* CLOCK_TYPE_PC2CC3S_T */
  114. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  115. CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
  116. MASK_BITS_31_29},
  117. /* CLOCK_TYPE_PC2CC3M_T */
  118. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  119. CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
  120. MASK_BITS_31_29},
  121. /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
  122. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  123. CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
  124. MASK_BITS_31_29},
  125. /* CLOCK_TYPE_MC2CC3P_A */
  126. { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  127. CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
  128. MASK_BITS_31_29},
  129. /* CLOCK_TYPE_M */
  130. { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
  131. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  132. MASK_BITS_31_30},
  133. /* CLOCK_TYPE_MCPTM2C2C3 */
  134. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  135. CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
  136. MASK_BITS_31_29},
  137. /* CLOCK_TYPE_PC2CC3T_S */
  138. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  139. CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
  140. MASK_BITS_31_29},
  141. /* CLOCK_TYPE_AC2CC3P_TS2 */
  142. { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  143. CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
  144. MASK_BITS_31_29},
  145. /* CLOCK_TYPE_PC01C00_C42C41TC40 */
  146. { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
  147. CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
  148. MASK_BITS_31_29},
  149. };
  150. /*
  151. * Clock type for each peripheral clock source. We put the name in each
  152. * record just so it is easy to match things up
  153. */
  154. #define TYPE(name, type) type
  155. static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
  156. /* 0x00 */
  157. TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
  158. TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
  159. TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
  160. TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
  161. TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
  162. TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
  163. TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
  164. TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
  165. /* 0x08 */
  166. TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
  167. TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
  168. TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
  169. TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
  170. TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
  171. TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
  172. TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T),
  173. TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T),
  174. /* 0x10 */
  175. TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
  176. TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
  177. TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
  178. TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
  179. TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
  180. TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
  181. TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
  182. TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
  183. /* 0x18 */
  184. TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
  185. TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
  186. TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
  187. TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
  188. TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
  189. TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
  190. TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
  191. TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
  192. /* 0x20 */
  193. TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
  194. TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
  195. TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
  196. TYPE(PERIPHC_23h, CLOCK_TYPE_NONE),
  197. TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
  198. TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
  199. TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
  200. TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
  201. /* 0x28 */
  202. TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
  203. TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
  204. TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
  205. TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
  206. TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
  207. TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
  208. TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
  209. TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
  210. /* 0x30 */
  211. TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
  212. TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
  213. TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
  214. TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
  215. TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
  216. TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
  217. TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
  218. TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
  219. /* 0x38 */
  220. TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
  221. TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
  222. TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
  223. TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
  224. TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
  225. TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
  226. TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
  227. TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
  228. /* 0x40 */
  229. TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
  230. TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
  231. TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
  232. TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
  233. TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT),
  234. TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
  235. TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
  236. TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
  237. /* 0x48 */
  238. TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
  239. TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
  240. TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE),
  241. TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE),
  242. TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE),
  243. TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
  244. TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
  245. TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
  246. /* 0x50 */
  247. TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
  248. TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
  249. TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
  250. TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
  251. TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
  252. TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
  253. TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
  254. TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
  255. /* 0x58 */
  256. TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
  257. TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
  258. TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
  259. TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
  260. TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
  261. TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
  262. TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
  263. TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
  264. /* 0x60 */
  265. TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
  266. TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
  267. TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
  268. TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
  269. TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
  270. TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
  271. TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
  272. TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
  273. /* 0x68 */
  274. TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
  275. TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
  276. TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
  277. TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
  278. TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
  279. TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
  280. TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE),
  281. TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE),
  282. /* 0x70 */
  283. TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
  284. TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
  285. TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
  286. TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
  287. TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
  288. TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
  289. TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
  290. TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
  291. /* 0x78 */
  292. TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
  293. TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
  294. TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE),
  295. TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
  296. TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE),
  297. TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE),
  298. TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
  299. TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
  300. /* 0x80 */
  301. TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE),
  302. TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE),
  303. TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE),
  304. TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE),
  305. TYPE(PERIPHC_84h, CLOCK_TYPE_NONE),
  306. TYPE(PERIPHC_85h, CLOCK_TYPE_NONE),
  307. TYPE(PERIPHC_86h, CLOCK_TYPE_NONE),
  308. TYPE(PERIPHC_87h, CLOCK_TYPE_NONE),
  309. /* 0x88 */
  310. TYPE(PERIPHC_88h, CLOCK_TYPE_NONE),
  311. TYPE(PERIPHC_89h, CLOCK_TYPE_NONE),
  312. TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
  313. TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
  314. TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
  315. TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16),
  316. TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
  317. TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
  318. /* 0x90 */
  319. TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE),
  320. TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE),
  321. };
  322. /*
  323. * This array translates a periph_id to a periphc_internal_id
  324. *
  325. * Not present/matched up:
  326. * uint vi_sensor; _VI_SENSOR_0, 0x1A8
  327. * SPDIF - which is both 0x08 and 0x0c
  328. *
  329. */
  330. #define NONE(name) (-1)
  331. #define OFFSET(name, value) PERIPHC_ ## name
  332. #define INTERNAL_ID(id) (id & 0x000000ff)
  333. static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
  334. /* Low word: 31:0 */
  335. NONE(CPU),
  336. NONE(COP),
  337. NONE(TRIGSYS),
  338. NONE(ISPB),
  339. NONE(RESERVED4),
  340. NONE(TMR),
  341. PERIPHC_UART1,
  342. PERIPHC_UART2, /* and vfir 0x68 */
  343. /* 8 */
  344. NONE(GPIO),
  345. PERIPHC_SDMMC2,
  346. PERIPHC_SPDIF_IN,
  347. PERIPHC_I2S2,
  348. PERIPHC_I2C1,
  349. NONE(RESERVED13),
  350. PERIPHC_SDMMC1,
  351. PERIPHC_SDMMC4,
  352. /* 16 */
  353. NONE(TCW),
  354. PERIPHC_PWM,
  355. PERIPHC_I2S3,
  356. NONE(RESERVED19),
  357. PERIPHC_VI,
  358. NONE(RESERVED21),
  359. NONE(USBD),
  360. NONE(ISP),
  361. /* 24 */
  362. NONE(RESERVED24),
  363. NONE(RESERVED25),
  364. PERIPHC_DISP2,
  365. PERIPHC_DISP1,
  366. PERIPHC_HOST1X,
  367. NONE(VCP),
  368. PERIPHC_I2S1,
  369. NONE(CACHE2),
  370. /* Middle word: 63:32 */
  371. NONE(MEM),
  372. NONE(AHBDMA),
  373. NONE(APBDMA),
  374. NONE(RESERVED35),
  375. NONE(RESERVED36),
  376. NONE(STAT_MON),
  377. NONE(RESERVED38),
  378. NONE(FUSE),
  379. /* 40 */
  380. NONE(KFUSE),
  381. PERIPHC_SBC1, /* SBCx = SPIx */
  382. PERIPHC_NOR,
  383. NONE(RESERVED43),
  384. PERIPHC_SBC2,
  385. NONE(XIO),
  386. PERIPHC_SBC3,
  387. PERIPHC_I2C5,
  388. /* 48 */
  389. NONE(DSI),
  390. NONE(RESERVED49),
  391. PERIPHC_HSI,
  392. NONE(RESERVED51),
  393. NONE(CSI),
  394. NONE(RESERVED53),
  395. PERIPHC_I2C2,
  396. PERIPHC_UART3,
  397. /* 56 */
  398. NONE(MIPI_CAL),
  399. PERIPHC_EMC,
  400. NONE(USB2),
  401. NONE(USB3),
  402. NONE(RESERVED60),
  403. PERIPHC_VDE,
  404. NONE(BSEA),
  405. NONE(BSEV),
  406. /* Upper word 95:64 */
  407. NONE(RESERVED64),
  408. PERIPHC_UART4,
  409. PERIPHC_UART5,
  410. PERIPHC_I2C3,
  411. PERIPHC_SBC4,
  412. PERIPHC_SDMMC3,
  413. NONE(PCIE),
  414. PERIPHC_OWR,
  415. /* 72 */
  416. NONE(AFI),
  417. PERIPHC_CSITE,
  418. NONE(PCIEXCLK),
  419. NONE(AVPUCQ),
  420. NONE(LA),
  421. NONE(TRACECLKIN),
  422. NONE(SOC_THERM),
  423. NONE(DTV),
  424. /* 80 */
  425. NONE(RESERVED80),
  426. PERIPHC_I2CSLOW,
  427. NONE(DSIB),
  428. PERIPHC_TSEC,
  429. NONE(RESERVED84),
  430. NONE(RESERVED85),
  431. NONE(RESERVED86),
  432. NONE(EMUCIF),
  433. /* 88 */
  434. NONE(RESERVED88),
  435. NONE(XUSB_HOST),
  436. NONE(RESERVED90),
  437. PERIPHC_MSENC,
  438. NONE(RESERVED92),
  439. NONE(RESERVED93),
  440. NONE(RESERVED94),
  441. NONE(XUSB_DEV),
  442. /* V word: 31:0 */
  443. NONE(CPUG),
  444. NONE(CPULP),
  445. NONE(V_RESERVED2),
  446. PERIPHC_MSELECT,
  447. NONE(V_RESERVED4),
  448. PERIPHC_I2S4,
  449. PERIPHC_I2S5,
  450. PERIPHC_I2C4,
  451. /* 104 */
  452. PERIPHC_SBC5,
  453. PERIPHC_SBC6,
  454. PERIPHC_AUDIO,
  455. NONE(APBIF),
  456. NONE(V_RESERVED12),
  457. NONE(V_RESERVED13),
  458. NONE(V_RESERVED14),
  459. PERIPHC_HDA2CODEC2X,
  460. /* 112 */
  461. NONE(ATOMICS),
  462. NONE(V_RESERVED17),
  463. NONE(V_RESERVED18),
  464. NONE(V_RESERVED19),
  465. NONE(V_RESERVED20),
  466. NONE(V_RESERVED21),
  467. NONE(V_RESERVED22),
  468. PERIPHC_ACTMON,
  469. /* 120 */
  470. NONE(EXTPERIPH1),
  471. NONE(EXTPERIPH2),
  472. NONE(EXTPERIPH3),
  473. NONE(OOB),
  474. PERIPHC_SATA,
  475. PERIPHC_HDA,
  476. NONE(TZRAM),
  477. NONE(SE),
  478. /* W word: 31:0 */
  479. NONE(HDA2HDMICODEC),
  480. NONE(SATACOLD),
  481. NONE(W_RESERVED2),
  482. NONE(W_RESERVED3),
  483. NONE(W_RESERVED4),
  484. NONE(W_RESERVED5),
  485. NONE(W_RESERVED6),
  486. NONE(W_RESERVED7),
  487. /* 136 */
  488. NONE(CEC),
  489. NONE(W_RESERVED9),
  490. NONE(W_RESERVED10),
  491. NONE(W_RESERVED11),
  492. NONE(W_RESERVED12),
  493. NONE(W_RESERVED13),
  494. NONE(XUSB_PADCTL),
  495. NONE(W_RESERVED15),
  496. /* 144 */
  497. NONE(W_RESERVED16),
  498. NONE(W_RESERVED17),
  499. NONE(W_RESERVED18),
  500. NONE(W_RESERVED19),
  501. NONE(W_RESERVED20),
  502. NONE(ENTROPY),
  503. NONE(DDS),
  504. NONE(W_RESERVED23),
  505. /* 152 */
  506. NONE(W_RESERVED24),
  507. NONE(W_RESERVED25),
  508. NONE(W_RESERVED26),
  509. NONE(DVFS),
  510. NONE(XUSB_SS),
  511. NONE(W_RESERVED29),
  512. NONE(W_RESERVED30),
  513. NONE(W_RESERVED31),
  514. /* X word: 31:0 */
  515. NONE(SPARE),
  516. NONE(X_RESERVED1),
  517. NONE(X_RESERVED2),
  518. NONE(X_RESERVED3),
  519. NONE(CAM_MCLK),
  520. NONE(CAM_MCLK2),
  521. PERIPHC_I2C6,
  522. NONE(X_RESERVED7),
  523. /* 168 */
  524. NONE(X_RESERVED8),
  525. NONE(X_RESERVED9),
  526. NONE(X_RESERVED10),
  527. NONE(VIM2_CLK),
  528. NONE(X_RESERVED12),
  529. NONE(X_RESERVED13),
  530. NONE(EMC_DLL),
  531. NONE(X_RESERVED15),
  532. /* 176 */
  533. NONE(X_RESERVED16),
  534. NONE(CLK72MHZ),
  535. NONE(VIC),
  536. NONE(X_RESERVED19),
  537. NONE(X_RESERVED20),
  538. NONE(DPAUX),
  539. NONE(SOR0),
  540. NONE(X_RESERVED23),
  541. /* 184 */
  542. NONE(GPU),
  543. NONE(X_RESERVED25),
  544. NONE(X_RESERVED26),
  545. NONE(X_RESERVED27),
  546. NONE(X_RESERVED28),
  547. NONE(X_RESERVED29),
  548. NONE(X_RESERVED30),
  549. NONE(X_RESERVED31),
  550. /* Y: 192 (192 - 223) */
  551. NONE(Y_RESERVED0),
  552. PERIPHC_SDMMC_LEGACY_TM,
  553. PERIPHC_NVDEC,
  554. PERIPHC_NVJPG,
  555. NONE(Y_RESERVED4),
  556. PERIPHC_DMIC3, /* 197 */
  557. PERIPHC_APE, /* 198 */
  558. NONE(Y_RESERVED7),
  559. /* 200 */
  560. NONE(Y_RESERVED8),
  561. NONE(Y_RESERVED9),
  562. NONE(Y_RESERVED10),
  563. NONE(Y_RESERVED11),
  564. NONE(Y_RESERVED12),
  565. NONE(Y_RESERVED13),
  566. NONE(Y_RESERVED14),
  567. NONE(Y_RESERVED15),
  568. /* 208 */
  569. PERIPHC_VI_I2C, /* 208 */
  570. NONE(Y_RESERVED17),
  571. NONE(Y_RESERVED18),
  572. PERIPHC_QSPI, /* 211 */
  573. NONE(Y_RESERVED20),
  574. NONE(Y_RESERVED21),
  575. NONE(Y_RESERVED22),
  576. NONE(Y_RESERVED23),
  577. /* 216 */
  578. NONE(Y_RESERVED24),
  579. NONE(Y_RESERVED25),
  580. NONE(Y_RESERVED26),
  581. PERIPHC_NVENC, /* 219 */
  582. NONE(Y_RESERVED28),
  583. NONE(Y_RESERVED29),
  584. NONE(Y_RESERVED30),
  585. NONE(Y_RESERVED31),
  586. };
  587. /*
  588. * PLL divider shift/mask tables for all PLL IDs.
  589. */
  590. struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
  591. /*
  592. * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.)
  593. * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.)
  594. */
  595. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  596. .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */
  597. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  598. .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
  599. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  600. .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */
  601. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  602. .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */
  603. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
  604. .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */
  605. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
  606. .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */
  607. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
  608. .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */
  609. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
  610. .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
  611. { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
  612. .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
  613. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
  614. .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
  615. };
  616. /*
  617. * Get the oscillator frequency, from the corresponding hardware configuration
  618. * field. Note that Tegra30+ support 3 new higher freqs, but we map back
  619. * to the old T20 freqs. Support for the higher oscillators is TBD.
  620. */
  621. enum clock_osc_freq clock_get_osc_freq(void)
  622. {
  623. struct clk_rst_ctlr *clkrst =
  624. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  625. u32 reg;
  626. reg = readl(&clkrst->crc_osc_ctrl);
  627. reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
  628. /*
  629. * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
  630. * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
  631. */
  632. if (reg == 5) {
  633. debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
  634. /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
  635. return 4;
  636. }
  637. /*
  638. * Map to most common (T20) freqs (except 38.4, handled above):
  639. * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
  640. */
  641. return reg >> 2;
  642. }
  643. /* Returns a pointer to the clock source register for a peripheral */
  644. u32 *get_periph_source_reg(enum periph_id periph_id)
  645. {
  646. struct clk_rst_ctlr *clkrst =
  647. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  648. enum periphc_internal_id internal_id;
  649. /* Coresight is a special case */
  650. if (periph_id == PERIPH_ID_CSI)
  651. return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
  652. assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
  653. internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
  654. assert(internal_id != -1);
  655. if (internal_id < PERIPHC_VW_FIRST)
  656. /* L, H, U */
  657. return &clkrst->crc_clk_src[internal_id];
  658. if (internal_id < PERIPHC_X_FIRST) {
  659. /* VW */
  660. internal_id -= PERIPHC_VW_FIRST;
  661. return &clkrst->crc_clk_src_vw[internal_id];
  662. }
  663. if (internal_id < PERIPHC_Y_FIRST) {
  664. /* X */
  665. internal_id -= PERIPHC_X_FIRST;
  666. return &clkrst->crc_clk_src_x[internal_id];
  667. }
  668. /* Y */
  669. internal_id -= PERIPHC_Y_FIRST;
  670. return &clkrst->crc_clk_src_y[internal_id];
  671. }
  672. int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
  673. int *divider_bits, int *type)
  674. {
  675. enum periphc_internal_id internal_id;
  676. if (!clock_periph_id_isvalid(periph_id))
  677. return -1;
  678. internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
  679. if (!periphc_internal_id_isvalid(internal_id))
  680. return -1;
  681. *type = clock_periph_type[internal_id];
  682. if (!clock_type_id_isvalid(*type))
  683. return -1;
  684. *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
  685. if (*type == CLOCK_TYPE_PC2CC3M_T16)
  686. *divider_bits = 16;
  687. else
  688. *divider_bits = 8;
  689. return 0;
  690. }
  691. enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
  692. {
  693. enum periphc_internal_id internal_id;
  694. int type;
  695. if (!clock_periph_id_isvalid(periph_id))
  696. return CLOCK_ID_NONE;
  697. internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
  698. if (!periphc_internal_id_isvalid(internal_id))
  699. return CLOCK_ID_NONE;
  700. type = clock_periph_type[internal_id];
  701. if (!clock_type_id_isvalid(type))
  702. return CLOCK_ID_NONE;
  703. return clock_source[type][source];
  704. }
  705. /**
  706. * Given a peripheral ID and the required source clock, this returns which
  707. * value should be programmed into the source mux for that peripheral.
  708. *
  709. * There is special code here to handle the one source type with 5 sources.
  710. *
  711. * @param periph_id peripheral to start
  712. * @param source PLL id of required parent clock
  713. * @param mux_bits Set to number of bits in mux register: 2 or 4
  714. * @param divider_bits Set to number of divider bits (8 or 16)
  715. * Return: mux value (0-4, or -1 if not found)
  716. */
  717. int get_periph_clock_source(enum periph_id periph_id,
  718. enum clock_id parent, int *mux_bits, int *divider_bits)
  719. {
  720. enum clock_type_id type;
  721. int mux, err;
  722. err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
  723. assert(!err);
  724. for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
  725. if (clock_source[type][mux] == parent)
  726. return mux;
  727. /* if we get here, either us or the caller has made a mistake */
  728. printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
  729. parent);
  730. return -1;
  731. }
  732. void clock_set_enable(enum periph_id periph_id, int enable)
  733. {
  734. struct clk_rst_ctlr *clkrst =
  735. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  736. u32 *clk;
  737. u32 reg;
  738. /* Enable/disable the clock to this peripheral */
  739. assert(clock_periph_id_isvalid(periph_id));
  740. if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
  741. clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
  742. else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
  743. clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
  744. else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
  745. clk = &clkrst->crc_clk_out_enb_x;
  746. else
  747. clk = &clkrst->crc_clk_out_enb_y;
  748. reg = readl(clk);
  749. if (enable)
  750. reg |= PERIPH_MASK(periph_id);
  751. else
  752. reg &= ~PERIPH_MASK(periph_id);
  753. writel(reg, clk);
  754. }
  755. void reset_set_enable(enum periph_id periph_id, int enable)
  756. {
  757. struct clk_rst_ctlr *clkrst =
  758. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  759. u32 *reset;
  760. u32 reg;
  761. /* Enable/disable reset to the peripheral */
  762. assert(clock_periph_id_isvalid(periph_id));
  763. if (periph_id < PERIPH_ID_VW_FIRST)
  764. reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
  765. else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
  766. reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
  767. else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
  768. reset = &clkrst->crc_rst_devices_x;
  769. else
  770. reset = &clkrst->crc_rst_devices_y;
  771. reg = readl(reset);
  772. if (enable)
  773. reg |= PERIPH_MASK(periph_id);
  774. else
  775. reg &= ~PERIPH_MASK(periph_id);
  776. writel(reg, reset);
  777. }
  778. #ifdef CONFIG_OF_CONTROL
  779. /*
  780. * Convert a device tree clock ID to our peripheral ID. They are mostly
  781. * the same but we are very cautious so we check that a valid clock ID is
  782. * provided.
  783. *
  784. * @param clk_id Clock ID according to tegra210 device tree binding
  785. * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
  786. */
  787. enum periph_id clk_id_to_periph_id(int clk_id)
  788. {
  789. if (clk_id > PERIPH_ID_COUNT)
  790. return PERIPH_ID_NONE;
  791. switch (clk_id) {
  792. case PERIPH_ID_RESERVED4:
  793. case PERIPH_ID_RESERVED25:
  794. case PERIPH_ID_RESERVED35:
  795. case PERIPH_ID_RESERVED36:
  796. case PERIPH_ID_RESERVED38:
  797. case PERIPH_ID_RESERVED43:
  798. case PERIPH_ID_RESERVED49:
  799. case PERIPH_ID_RESERVED53:
  800. case PERIPH_ID_RESERVED64:
  801. case PERIPH_ID_RESERVED84:
  802. case PERIPH_ID_RESERVED85:
  803. case PERIPH_ID_RESERVED86:
  804. case PERIPH_ID_RESERVED88:
  805. case PERIPH_ID_RESERVED90:
  806. case PERIPH_ID_RESERVED92:
  807. case PERIPH_ID_RESERVED93:
  808. case PERIPH_ID_RESERVED94:
  809. case PERIPH_ID_V_RESERVED2:
  810. case PERIPH_ID_V_RESERVED4:
  811. case PERIPH_ID_V_RESERVED17:
  812. case PERIPH_ID_V_RESERVED18:
  813. case PERIPH_ID_V_RESERVED19:
  814. case PERIPH_ID_V_RESERVED20:
  815. case PERIPH_ID_V_RESERVED21:
  816. case PERIPH_ID_V_RESERVED22:
  817. case PERIPH_ID_W_RESERVED2:
  818. case PERIPH_ID_W_RESERVED3:
  819. case PERIPH_ID_W_RESERVED4:
  820. case PERIPH_ID_W_RESERVED5:
  821. case PERIPH_ID_W_RESERVED6:
  822. case PERIPH_ID_W_RESERVED7:
  823. case PERIPH_ID_W_RESERVED9:
  824. case PERIPH_ID_W_RESERVED10:
  825. case PERIPH_ID_W_RESERVED11:
  826. case PERIPH_ID_W_RESERVED12:
  827. case PERIPH_ID_W_RESERVED13:
  828. case PERIPH_ID_W_RESERVED15:
  829. case PERIPH_ID_W_RESERVED16:
  830. case PERIPH_ID_W_RESERVED17:
  831. case PERIPH_ID_W_RESERVED18:
  832. case PERIPH_ID_W_RESERVED19:
  833. case PERIPH_ID_W_RESERVED20:
  834. case PERIPH_ID_W_RESERVED23:
  835. case PERIPH_ID_W_RESERVED29:
  836. case PERIPH_ID_W_RESERVED30:
  837. case PERIPH_ID_W_RESERVED31:
  838. return PERIPH_ID_NONE;
  839. default:
  840. return clk_id;
  841. }
  842. }
  843. #endif /* CONFIG_OF_CONTROL */
  844. /*
  845. * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
  846. * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
  847. */
  848. void tegra210_setup_pllp(void)
  849. {
  850. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  851. u32 reg;
  852. /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
  853. /* OUT1 */
  854. /* Assert RSTN before enable */
  855. reg = PLLP_OUT1_RSTN_EN;
  856. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  857. /* Set divisor and reenable */
  858. reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
  859. | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
  860. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  861. /* OUT3, 4 */
  862. /* Assert RSTN before enable */
  863. reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
  864. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  865. /* Set divisor and reenable */
  866. reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
  867. | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
  868. | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
  869. | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
  870. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  871. /*
  872. * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
  873. * you can change PLLP_BASE DIVP here. Currently defaults
  874. * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
  875. * See Table 13 in section 5.1.4 in T210 TRM for more info.
  876. */
  877. }
  878. void clock_early_init(void)
  879. {
  880. struct clk_rst_ctlr *clkrst =
  881. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  882. struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
  883. u32 data;
  884. tegra210_setup_pllp();
  885. /*
  886. * PLLC output frequency set to 600Mhz
  887. * PLLD output frequency set to 925Mhz
  888. */
  889. switch (clock_get_osc_freq()) {
  890. case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
  891. clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
  892. clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
  893. break;
  894. case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
  895. clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
  896. clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
  897. break;
  898. case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
  899. clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
  900. clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
  901. break;
  902. case CLOCK_OSC_FREQ_19_2:
  903. clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
  904. clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
  905. break;
  906. case CLOCK_OSC_FREQ_38_4:
  907. clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0);
  908. clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0);
  909. break;
  910. default:
  911. /*
  912. * These are not supported. It is too early to print a
  913. * message and the UART likely won't work anyway due to the
  914. * oscillator being wrong.
  915. */
  916. break;
  917. }
  918. /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
  919. clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,
  920. (1 << PLLC_IDDQ));
  921. udelay(2);
  922. /*
  923. * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps
  924. * to pll_out[1]
  925. */
  926. clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],
  927. (1 << PLLC_RESET));
  928. udelay(2);
  929. /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
  930. data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena);
  931. writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
  932. udelay(2);
  933. }
  934. unsigned int clk_m_get_rate(unsigned parent_rate)
  935. {
  936. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  937. u32 value, div;
  938. value = readl(&clkrst->crc_spare_reg0);
  939. div = ((value >> 2) & 0x3) + 1;
  940. return parent_rate / div;
  941. }
  942. void arch_timer_init(void)
  943. {
  944. struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
  945. u32 freq, val;
  946. freq = clock_get_rate(CLOCK_ID_CLK_M);
  947. debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
  948. if (current_el() == 3)
  949. asm("msr cntfrq_el0, %0\n" : : "r" (freq));
  950. /* Only Tegra114+ has the System Counter regs */
  951. debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
  952. writel(freq, &sysctr->cntfid0);
  953. val = readl(&sysctr->cntcr);
  954. val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
  955. writel(val, &sysctr->cntcr);
  956. debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
  957. }
  958. #define PLLREFE_MISC 0x4c8
  959. #define PLLREFE_MISC_LOCK BIT(27)
  960. #define PLLREFE_MISC_IDDQ BIT(24)
  961. #define PLLREFE_BASE 0x4c4
  962. #define PLLREFE_BASE_BYPASS BIT(31)
  963. #define PLLREFE_BASE_ENABLE BIT(30)
  964. #define PLLREFE_BASE_REF_DIS BIT(29)
  965. #define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27)
  966. #define PLLREFE_BASE_KVCO BIT(26)
  967. #define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16)
  968. #define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8)
  969. #define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0)
  970. static int tegra_pllref_enable(void)
  971. {
  972. u32 value;
  973. unsigned long start;
  974. /*
  975. * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
  976. * Recovery Mode or Boot from USB", sub-section "PLLREFE".
  977. */
  978. value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
  979. value &= ~PLLREFE_MISC_IDDQ;
  980. writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC);
  981. udelay(5);
  982. value = PLLREFE_BASE_ENABLE |
  983. PLLREFE_BASE_KCP(0) |
  984. PLLREFE_BASE_DIVP(0) |
  985. PLLREFE_BASE_DIVN(0x41) |
  986. PLLREFE_BASE_DIVM(4);
  987. writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE);
  988. debug("waiting for pllrefe lock\n");
  989. start = get_timer(0);
  990. while (get_timer(start) < 250) {
  991. value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
  992. if (value & PLLREFE_MISC_LOCK)
  993. break;
  994. }
  995. if (!(value & PLLREFE_MISC_LOCK)) {
  996. debug(" timeout\n");
  997. return -ETIMEDOUT;
  998. }
  999. debug(" done\n");
  1000. return 0;
  1001. }
  1002. #define PLLE_SS_CNTL 0x68
  1003. #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
  1004. #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
  1005. #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
  1006. #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
  1007. #define PLLE_SS_CNTL_SSCBYP (1 << 12)
  1008. #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
  1009. #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
  1010. #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
  1011. #define PLLE_BASE 0x0e8
  1012. #define PLLE_BASE_ENABLE (1 << 31)
  1013. #define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24)
  1014. #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
  1015. #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
  1016. #define PLLE_MISC 0x0ec
  1017. #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
  1018. #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
  1019. #define PLLE_MISC_LOCK (1 << 11)
  1020. #define PLLE_PTS (1 << 8)
  1021. #define PLLE_MISC_KCP(x) (((x) & 0x3) << 6)
  1022. #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
  1023. #define PLLE_MISC_KVCO (1 << 0)
  1024. #define PLLE_AUX 0x48c
  1025. #define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
  1026. #define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
  1027. #define PLLE_AUX_SEQ_ENABLE (1 << 24)
  1028. #define PLLE_AUX_SS_SWCTL (1 << 6)
  1029. #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
  1030. #define PLLE_AUX_USE_LOCKDET (1 << 3)
  1031. int tegra_plle_enable(void)
  1032. {
  1033. u32 value;
  1034. unsigned long start;
  1035. /* PLLREF feeds PLLE */
  1036. tegra_pllref_enable();
  1037. /*
  1038. * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
  1039. * Recovery Mode or Boot from USB", sub-section "PLLEs".
  1040. */
  1041. /* 1. Select XTAL as the source */
  1042. value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
  1043. value &= ~PLLE_AUX_REF_SEL_PLLREFE;
  1044. writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
  1045. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  1046. value &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
  1047. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  1048. /* 2. Wait 5 us */
  1049. udelay(5);
  1050. /*
  1051. * 3. Program the following registers to generate a low jitter 100MHz
  1052. * clock.
  1053. */
  1054. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  1055. value &= ~PLLE_BASE_PLDIV_CML(0x1f);
  1056. value &= ~PLLE_BASE_NDIV(0xff);
  1057. value &= ~PLLE_BASE_MDIV(0xff);
  1058. value |= PLLE_BASE_PLDIV_CML(0xe);
  1059. value |= PLLE_BASE_NDIV(0x7d);
  1060. value |= PLLE_BASE_MDIV(2);
  1061. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  1062. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  1063. value |= PLLE_PTS;
  1064. value &= ~PLLE_MISC_KCP(3);
  1065. value &= ~PLLE_MISC_VREG_CTRL(3);
  1066. value &= ~PLLE_MISC_KVCO;
  1067. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  1068. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  1069. value |= PLLE_BASE_ENABLE;
  1070. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  1071. /* 4. Wait for LOCK */
  1072. debug("waiting for plle lock\n");
  1073. start = get_timer(0);
  1074. while (get_timer(start) < 250) {
  1075. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  1076. if (value & PLLE_MISC_LOCK)
  1077. break;
  1078. }
  1079. if (!(value & PLLE_MISC_LOCK)) {
  1080. debug(" timeout\n");
  1081. return -ETIMEDOUT;
  1082. }
  1083. debug(" done\n");
  1084. /* 5. Enable SSA */
  1085. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  1086. value &= ~PLLE_SS_CNTL_SSCINC(0xff);
  1087. value |= PLLE_SS_CNTL_SSCINC(1);
  1088. value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
  1089. value |= PLLE_SS_CNTL_SSCINCINTR(0x23);
  1090. value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
  1091. value |= PLLE_SS_CNTL_SSCMAX(0x21);
  1092. value &= ~PLLE_SS_CNTL_SSCINVERT;
  1093. value &= ~PLLE_SS_CNTL_SSCCENTER;
  1094. value &= ~PLLE_SS_CNTL_BYPASS_SS;
  1095. value &= ~PLLE_SS_CNTL_SSCBYP;
  1096. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  1097. /* 6. Wait 300 ns */
  1098. udelay(1);
  1099. value &= ~PLLE_SS_CNTL_INTERP_RESET;
  1100. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  1101. return 0;
  1102. }
  1103. struct periph_clk_init periph_clk_init_table[] = {
  1104. { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
  1105. { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
  1106. { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
  1107. { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
  1108. { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
  1109. { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
  1110. { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
  1111. { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
  1112. { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
  1113. { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
  1114. { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
  1115. { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
  1116. { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
  1117. { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
  1118. { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
  1119. { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
  1120. { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
  1121. { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
  1122. { -1, },
  1123. };