emc.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. */
  5. #include <common.h>
  6. #include <fdtdec.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <asm/arch-tegra/ap.h>
  10. #include <asm/arch-tegra/apb_misc.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/emc.h>
  13. #include <asm/arch/tegra.h>
  14. /*
  15. * The EMC registers have shadow registers. When the EMC clock is updated
  16. * in the clock controller, the shadow registers are copied to the active
  17. * registers, allowing glitchless memory bus frequency changes.
  18. * This function updates the shadow registers for a new clock frequency,
  19. * and relies on the clock lock on the emc clock to avoid races between
  20. * multiple frequency changes
  21. */
  22. /*
  23. * This table defines the ordering of the registers provided to
  24. * tegra_set_mmc()
  25. * TODO: Convert to fdt version once available
  26. */
  27. static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
  28. 0x2c, /* RC */
  29. 0x30, /* RFC */
  30. 0x34, /* RAS */
  31. 0x38, /* RP */
  32. 0x3c, /* R2W */
  33. 0x40, /* W2R */
  34. 0x44, /* R2P */
  35. 0x48, /* W2P */
  36. 0x4c, /* RD_RCD */
  37. 0x50, /* WR_RCD */
  38. 0x54, /* RRD */
  39. 0x58, /* REXT */
  40. 0x5c, /* WDV */
  41. 0x60, /* QUSE */
  42. 0x64, /* QRST */
  43. 0x68, /* QSAFE */
  44. 0x6c, /* RDV */
  45. 0x70, /* REFRESH */
  46. 0x74, /* BURST_REFRESH_NUM */
  47. 0x78, /* PDEX2WR */
  48. 0x7c, /* PDEX2RD */
  49. 0x80, /* PCHG2PDEN */
  50. 0x84, /* ACT2PDEN */
  51. 0x88, /* AR2PDEN */
  52. 0x8c, /* RW2PDEN */
  53. 0x90, /* TXSR */
  54. 0x94, /* TCKE */
  55. 0x98, /* TFAW */
  56. 0x9c, /* TRPAB */
  57. 0xa0, /* TCLKSTABLE */
  58. 0xa4, /* TCLKSTOP */
  59. 0xa8, /* TREFBW */
  60. 0xac, /* QUSE_EXTRA */
  61. 0x114, /* FBIO_CFG6 */
  62. 0xb0, /* ODT_WRITE */
  63. 0xb4, /* ODT_READ */
  64. 0x104, /* FBIO_CFG5 */
  65. 0x2bc, /* CFG_DIG_DLL */
  66. 0x2c0, /* DLL_XFORM_DQS */
  67. 0x2c4, /* DLL_XFORM_QUSE */
  68. 0x2e0, /* ZCAL_REF_CNT */
  69. 0x2e4, /* ZCAL_WAIT_CNT */
  70. 0x2a8, /* AUTO_CAL_INTERVAL */
  71. 0x2d0, /* CFG_CLKTRIM_0 */
  72. 0x2d4, /* CFG_CLKTRIM_1 */
  73. 0x2d8, /* CFG_CLKTRIM_2 */
  74. };
  75. struct emc_ctlr *emc_get_controller(const void *blob)
  76. {
  77. fdt_addr_t addr;
  78. int node;
  79. node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
  80. if (node > 0) {
  81. addr = fdtdec_get_addr(blob, node, "reg");
  82. if (addr != FDT_ADDR_T_NONE)
  83. return (struct emc_ctlr *)addr;
  84. }
  85. return NULL;
  86. }
  87. /* Error codes we use */
  88. enum {
  89. ERR_NO_EMC_NODE = -10,
  90. ERR_NO_EMC_REG,
  91. ERR_NO_FREQ,
  92. ERR_FREQ_NOT_FOUND,
  93. ERR_BAD_REGS,
  94. ERR_NO_RAM_CODE,
  95. ERR_RAM_CODE_NOT_FOUND,
  96. };
  97. /**
  98. * Find EMC tables for the given ram code.
  99. *
  100. * The tegra EMC binding has two options, one using the ram code and one not.
  101. * We detect which is in use by looking for the nvidia,use-ram-code property.
  102. * If this is not present, then the EMC tables are directly below 'node',
  103. * otherwise we select the correct emc-tables subnode based on the 'ram_code'
  104. * value.
  105. *
  106. * @param blob Device tree blob
  107. * @param node EMC node (nvidia,tegra20-emc compatible string)
  108. * @param ram_code RAM code to select (0-3, or -1 if unknown)
  109. * Return: 0 if ok, otherwise a -ve ERR_ code (see enum above)
  110. */
  111. static int find_emc_tables(const void *blob, int node, int ram_code)
  112. {
  113. int need_ram_code;
  114. int depth;
  115. int offset;
  116. /* If we are using RAM codes, scan through the tables for our code */
  117. need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code");
  118. if (!need_ram_code)
  119. return node;
  120. if (ram_code == -1) {
  121. debug("%s: RAM code required but not supplied\n", __func__);
  122. return ERR_NO_RAM_CODE;
  123. }
  124. offset = node;
  125. depth = 0;
  126. do {
  127. /*
  128. * Sadly there is no compatible string so we cannot use
  129. * fdtdec_next_compatible_subnode().
  130. */
  131. offset = fdt_next_node(blob, offset, &depth);
  132. if (depth <= 0)
  133. break;
  134. /* Make sure this is a direct subnode */
  135. if (depth != 1)
  136. continue;
  137. if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))
  138. continue;
  139. if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1)
  140. == ram_code)
  141. return offset;
  142. } while (1);
  143. debug("%s: Could not find tables for RAM code %d\n", __func__,
  144. ram_code);
  145. return ERR_RAM_CODE_NOT_FOUND;
  146. }
  147. /**
  148. * Decode the EMC node of the device tree, returning a pointer to the emc
  149. * controller and the table to be used for the given rate.
  150. *
  151. * @param blob Device tree blob
  152. * @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
  153. * @param emcp Returns address of EMC controller registers
  154. * @param tablep Returns pointer to table to program into EMC. There are
  155. * TEGRA_EMC_NUM_REGS entries, destined for offsets as per the
  156. * emc_reg_addr array.
  157. * Return: 0 if ok, otherwise a -ve error code which will allow someone to
  158. * figure out roughly what went wrong by looking at this code.
  159. */
  160. static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
  161. const u32 **tablep)
  162. {
  163. struct apb_misc_pp_ctlr *pp =
  164. (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
  165. int ram_code;
  166. int depth;
  167. int node;
  168. ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK)
  169. >> RAM_CODE_SHIFT;
  170. /*
  171. * The EMC clock rate is twice the bus rate, and the bus rate is
  172. * measured in kHz
  173. */
  174. rate = rate / 2 / 1000;
  175. node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
  176. if (node < 0) {
  177. debug("%s: No EMC node found in FDT\n", __func__);
  178. return ERR_NO_EMC_NODE;
  179. }
  180. *emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg");
  181. if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) {
  182. debug("%s: No EMC node reg property\n", __func__);
  183. return ERR_NO_EMC_REG;
  184. }
  185. /* Work out the parent node which contains our EMC tables */
  186. node = find_emc_tables(blob, node, ram_code & 3);
  187. if (node < 0)
  188. return node;
  189. depth = 0;
  190. for (;;) {
  191. int node_rate;
  192. node = fdtdec_next_compatible_subnode(blob, node,
  193. COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth);
  194. if (node < 0)
  195. break;
  196. node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1);
  197. if (node_rate == -1) {
  198. debug("%s: Missing clock-frequency\n", __func__);
  199. return ERR_NO_FREQ; /* we expect this property */
  200. }
  201. if (node_rate == rate)
  202. break;
  203. }
  204. if (node < 0) {
  205. debug("%s: No node found for clock frequency %d\n", __func__,
  206. rate);
  207. return ERR_FREQ_NOT_FOUND;
  208. }
  209. *tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",
  210. TEGRA_EMC_NUM_REGS);
  211. if (!*tablep) {
  212. debug("%s: node '%s' array missing / wrong size\n", __func__,
  213. fdt_get_name(blob, node, NULL));
  214. return ERR_BAD_REGS;
  215. }
  216. /* All seems well */
  217. return 0;
  218. }
  219. int tegra_set_emc(const void *blob, unsigned rate)
  220. {
  221. struct emc_ctlr *emc;
  222. const u32 *table = NULL;
  223. int err, i;
  224. err = decode_emc(blob, rate, &emc, &table);
  225. if (err) {
  226. debug("Warning: no valid EMC (%d), memory timings unset\n",
  227. err);
  228. return err;
  229. }
  230. debug("%s: Table found, setting EMC values as follows:\n", __func__);
  231. for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) {
  232. u32 value = fdt32_to_cpu(table[i]);
  233. u32 addr = (uintptr_t)emc + emc_reg_addr[i];
  234. debug(" %#x: %#x\n", addr, value);
  235. writel(value, addr);
  236. }
  237. /* trigger emc with new settings */
  238. clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY,
  239. clock_get_rate(CLOCK_ID_MEMORY), NULL);
  240. debug("EMC clock set to %lu\n",
  241. clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY));
  242. return 0;
  243. }