dmc_init_ddr3.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DDR3 mem setup file for board based on EXYNOS5
  4. *
  5. * Copyright (C) 2012 Samsung Electronics
  6. */
  7. #include <common.h>
  8. #include <config.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/dmc.h>
  13. #include <asm/arch/power.h>
  14. #include "common_setup.h"
  15. #include "exynos5_setup.h"
  16. #include "clock_init.h"
  17. #define TIMEOUT_US 10000
  18. #define NUM_BYTE_LANES 4
  19. #define DEFAULT_DQS 8
  20. #define DEFAULT_DQS_X4 ((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
  21. || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0))
  22. #ifdef CONFIG_EXYNOS5250
  23. static void reset_phy_ctrl(void)
  24. {
  25. struct exynos5_clock *clk =
  26. (struct exynos5_clock *)samsung_get_base_clock();
  27. writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
  28. writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
  29. }
  30. int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
  31. {
  32. unsigned int val;
  33. struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
  34. struct exynos5_dmc *dmc;
  35. int i;
  36. phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
  37. phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
  38. + DMC_OFFSET);
  39. dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
  40. if (reset)
  41. reset_phy_ctrl();
  42. /* Set Impedance Output Driver */
  43. val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
  44. (mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
  45. (mem->impedance << CA_CS_DRVR_DS_OFFSET) |
  46. (mem->impedance << CA_ADR_DRVR_DS_OFFSET);
  47. writel(val, &phy0_ctrl->phy_con39);
  48. writel(val, &phy1_ctrl->phy_con39);
  49. /* Set Read Latency and Burst Length for PHY0 and PHY1 */
  50. val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
  51. (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
  52. writel(val, &phy0_ctrl->phy_con42);
  53. writel(val, &phy1_ctrl->phy_con42);
  54. /* ZQ Calibration */
  55. if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
  56. &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
  57. return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
  58. /* DQ Signal */
  59. writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
  60. writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
  61. writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
  62. | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
  63. &dmc->concontrol);
  64. update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
  65. /* DQS Signal */
  66. writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
  67. writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
  68. writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
  69. writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
  70. writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
  71. writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
  72. val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
  73. (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
  74. (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
  75. (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
  76. writel(val, &phy0_ctrl->phy_con12);
  77. writel(val, &phy1_ctrl->phy_con12);
  78. /* Start DLL locking */
  79. writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
  80. &phy0_ctrl->phy_con12);
  81. writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
  82. &phy1_ctrl->phy_con12);
  83. update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
  84. writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
  85. &dmc->concontrol);
  86. /* Memory Channel Inteleaving Size */
  87. writel(mem->iv_size, &dmc->ivcontrol);
  88. writel(mem->memconfig, &dmc->memconfig0);
  89. writel(mem->memconfig, &dmc->memconfig1);
  90. writel(mem->membaseconfig0, &dmc->membaseconfig0);
  91. writel(mem->membaseconfig1, &dmc->membaseconfig1);
  92. /* Precharge Configuration */
  93. writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
  94. &dmc->prechconfig);
  95. /* Power Down mode Configuration */
  96. writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
  97. mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
  98. &dmc->pwrdnconfig);
  99. /* TimingRow, TimingData, TimingPower and Timingaref
  100. * values as per Memory AC parameters
  101. */
  102. writel(mem->timing_ref, &dmc->timingref);
  103. writel(mem->timing_row, &dmc->timingrow);
  104. writel(mem->timing_data, &dmc->timingdata);
  105. writel(mem->timing_power, &dmc->timingpower);
  106. /* Send PALL command */
  107. dmc_config_prech(mem, &dmc->directcmd);
  108. /* Send NOP, MRS and ZQINIT commands */
  109. dmc_config_mrs(mem, &dmc->directcmd);
  110. if (mem->gate_leveling_enable) {
  111. val = PHY_CON0_RESET_VAL;
  112. val |= P0_CMD_EN;
  113. writel(val, &phy0_ctrl->phy_con0);
  114. writel(val, &phy1_ctrl->phy_con0);
  115. val = PHY_CON2_RESET_VAL;
  116. val |= INIT_DESKEW_EN;
  117. writel(val, &phy0_ctrl->phy_con2);
  118. writel(val, &phy1_ctrl->phy_con2);
  119. val = PHY_CON0_RESET_VAL;
  120. val |= P0_CMD_EN;
  121. val |= BYTE_RDLVL_EN;
  122. writel(val, &phy0_ctrl->phy_con0);
  123. writel(val, &phy1_ctrl->phy_con0);
  124. val = (mem->ctrl_start_point <<
  125. PHY_CON12_CTRL_START_POINT_SHIFT) |
  126. (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
  127. (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
  128. (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
  129. (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
  130. writel(val, &phy0_ctrl->phy_con12);
  131. writel(val, &phy1_ctrl->phy_con12);
  132. val = PHY_CON2_RESET_VAL;
  133. val |= INIT_DESKEW_EN;
  134. val |= RDLVL_GATE_EN;
  135. writel(val, &phy0_ctrl->phy_con2);
  136. writel(val, &phy1_ctrl->phy_con2);
  137. val = PHY_CON0_RESET_VAL;
  138. val |= P0_CMD_EN;
  139. val |= BYTE_RDLVL_EN;
  140. val |= CTRL_SHGATE;
  141. writel(val, &phy0_ctrl->phy_con0);
  142. writel(val, &phy1_ctrl->phy_con0);
  143. val = PHY_CON1_RESET_VAL;
  144. val &= ~(CTRL_GATEDURADJ_MASK);
  145. writel(val, &phy0_ctrl->phy_con1);
  146. writel(val, &phy1_ctrl->phy_con1);
  147. writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
  148. i = TIMEOUT_US;
  149. while ((readl(&dmc->phystatus) &
  150. (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
  151. (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
  152. /*
  153. * TODO(waihong): Comment on how long this take to
  154. * timeout
  155. */
  156. sdelay(100);
  157. i--;
  158. }
  159. if (!i)
  160. return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
  161. writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
  162. writel(0, &phy0_ctrl->phy_con14);
  163. writel(0, &phy1_ctrl->phy_con14);
  164. val = (mem->ctrl_start_point <<
  165. PHY_CON12_CTRL_START_POINT_SHIFT) |
  166. (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
  167. (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
  168. (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
  169. (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
  170. (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
  171. writel(val, &phy0_ctrl->phy_con12);
  172. writel(val, &phy1_ctrl->phy_con12);
  173. update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
  174. }
  175. /* Send PALL command */
  176. dmc_config_prech(mem, &dmc->directcmd);
  177. writel(mem->memcontrol, &dmc->memcontrol);
  178. /* Set DMC Concontrol and enable auto-refresh counter */
  179. writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
  180. | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
  181. return 0;
  182. }
  183. #endif
  184. #ifdef CONFIG_EXYNOS5420
  185. /**
  186. * RAM address to use in the test.
  187. *
  188. * We'll use 4 words at this address and 4 at this address + 0x80 (Ares
  189. * interleaves channels every 128 bytes). This will allow us to evaluate all of
  190. * the chips in a 1 chip per channel (2GB) system and half the chips in a 2
  191. * chip per channel (4GB) system. We can't test the 2nd chip since we need to
  192. * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't
  193. * critical because the 1st and 2nd chip have very similar timings (they'd
  194. * better have similar timings, since there's only a single adjustment that is
  195. * shared by both chips).
  196. */
  197. const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
  198. /* Test pattern with which RAM will be tested */
  199. static const unsigned int test_pattern[] = {
  200. 0x5a5a5a5a,
  201. 0xa5a5a5a5,
  202. 0xf0f0f0f0,
  203. 0x0f0f0f0f,
  204. };
  205. /**
  206. * This function is a test vector for sw read leveling,
  207. * it compares the read data with the written data.
  208. *
  209. * @param ch DMC channel number
  210. * @param byte_lane which DQS byte offset,
  211. * possible values are 0,1,2,3
  212. * Return: TRUE if memory was good, FALSE if not.
  213. */
  214. static bool dmc_valid_window_test_vector(int ch, int byte_lane)
  215. {
  216. unsigned int read_data;
  217. unsigned int mask;
  218. int i;
  219. mask = 0xFF << (8 * byte_lane);
  220. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  221. read_data = readl(test_addr + i * 4 + ch * 0x80);
  222. if ((read_data & mask) != (test_pattern[i] & mask))
  223. return false;
  224. }
  225. return true;
  226. }
  227. /**
  228. * This function returns current read offset value.
  229. *
  230. * @param phy_ctrl pointer to the current phy controller
  231. */
  232. static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control
  233. *phy_ctrl)
  234. {
  235. return readl(&phy_ctrl->phy_con4);
  236. }
  237. /**
  238. * This function performs resync, so that slave DLL is updated.
  239. *
  240. * @param phy_ctrl pointer to the current phy controller
  241. */
  242. static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl)
  243. {
  244. setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
  245. clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
  246. }
  247. /**
  248. * This function sets read offset value register with 'offset'.
  249. *
  250. * ...we also call call ddr_phy_set_do_resync().
  251. *
  252. * @param phy_ctrl pointer to the current phy controller
  253. * @param offset offset to read DQS
  254. */
  255. static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
  256. unsigned int offset)
  257. {
  258. writel(offset, &phy_ctrl->phy_con4);
  259. ddr_phy_set_do_resync(phy_ctrl);
  260. }
  261. /**
  262. * Convert a 2s complement byte to a byte with a sign bit.
  263. *
  264. * NOTE: you shouldn't use normal math on the number returned by this function.
  265. * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted
  266. * to do math and get the average of 10 and -10 (should be 0):
  267. * 0x8a + 0xa = 0x94 (-108)
  268. * 0x94 / 2 = 0xca (-54)
  269. * ...and 0xca = sign bit plus 0x4a, or -74
  270. *
  271. * Also note that you lose the ability to represent -128 since there are two
  272. * representations of 0.
  273. *
  274. * @param b The byte to convert in two's complement.
  275. * Return: The 7-bit value + sign bit.
  276. */
  277. unsigned char make_signed_byte(signed char b)
  278. {
  279. if (b < 0)
  280. return 0x80 | -b;
  281. else
  282. return b;
  283. }
  284. /**
  285. * Test various shifts starting at 'start' and going to 'end'.
  286. *
  287. * For each byte lane, we'll walk through shift starting at 'start' and going
  288. * to 'end' (inclusive). When we are finally able to read the test pattern
  289. * we'll store the value in the results array.
  290. *
  291. * @param phy_ctrl pointer to the current phy controller
  292. * @param ch channel number
  293. * @param start the start shift. -127 to 127
  294. * @param end the end shift. -127 to 127
  295. * @param results we'll store results for each byte lane.
  296. */
  297. void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch,
  298. int start, int end, int results[NUM_BYTE_LANES])
  299. {
  300. int incr = (start < end) ? 1 : -1;
  301. int byte_lane;
  302. for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
  303. int shift;
  304. dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4);
  305. results[byte_lane] = DEFAULT_DQS;
  306. for (shift = start; shift != (end + incr); shift += incr) {
  307. unsigned int byte_offsetr;
  308. unsigned int offsetr;
  309. byte_offsetr = make_signed_byte(shift);
  310. offsetr = dmc_get_read_offset_value(phy_ctrl);
  311. offsetr &= ~(0xFF << (8 * byte_lane));
  312. offsetr |= (byte_offsetr << (8 * byte_lane));
  313. dmc_set_read_offset_value(phy_ctrl, offsetr);
  314. if (dmc_valid_window_test_vector(ch, byte_lane)) {
  315. results[byte_lane] = shift;
  316. break;
  317. }
  318. }
  319. }
  320. }
  321. /**
  322. * This function performs SW read leveling to compensate DQ-DQS skew at
  323. * receiver it first finds the optimal read offset value on each DQS
  324. * then applies the value to PHY.
  325. *
  326. * Read offset value has its min margin and max margin. If read offset
  327. * value exceeds its min or max margin, read data will have corruption.
  328. * To avoid this we are doing sw read leveling.
  329. *
  330. * SW read leveling is:
  331. * 1> Finding offset value's left_limit and right_limit
  332. * 2> and calculate its center value
  333. * 3> finally programs that center value to PHY
  334. * 4> then PHY gets its optimal offset value.
  335. *
  336. * @param phy_ctrl pointer to the current phy controller
  337. * @param ch channel number
  338. * @param coarse_lock_val The coarse lock value read from PHY_CON13.
  339. * (0 - 0x7f)
  340. */
  341. static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl,
  342. int ch, unsigned int coarse_lock_val)
  343. {
  344. unsigned int offsetr_cent;
  345. int byte_lane;
  346. int left_limit;
  347. int right_limit;
  348. int left[NUM_BYTE_LANES];
  349. int right[NUM_BYTE_LANES];
  350. int i;
  351. /* Fill the memory with test patterns */
  352. for (i = 0; i < ARRAY_SIZE(test_pattern); i++)
  353. writel(test_pattern[i], test_addr + i * 4 + ch * 0x80);
  354. /* Figure out the limits we'll test with; keep -127 < limit < 127 */
  355. left_limit = DEFAULT_DQS - coarse_lock_val;
  356. right_limit = DEFAULT_DQS + coarse_lock_val;
  357. if (right_limit > 127)
  358. right_limit = 127;
  359. /* Fill in the location where reads were OK from left and right */
  360. test_shifts(phy_ctrl, ch, left_limit, right_limit, left);
  361. test_shifts(phy_ctrl, ch, right_limit, left_limit, right);
  362. /* Make a final value by taking the center between the left and right */
  363. offsetr_cent = 0;
  364. for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
  365. int temp_center;
  366. unsigned int vmwc;
  367. temp_center = (left[byte_lane] + right[byte_lane]) / 2;
  368. vmwc = make_signed_byte(temp_center);
  369. offsetr_cent |= vmwc << (8 * byte_lane);
  370. }
  371. dmc_set_read_offset_value(phy_ctrl, offsetr_cent);
  372. }
  373. int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
  374. {
  375. struct exynos5420_clock *clk =
  376. (struct exynos5420_clock *)samsung_get_base_clock();
  377. struct exynos5420_power *power =
  378. (struct exynos5420_power *)samsung_get_base_power();
  379. struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
  380. struct exynos5420_dmc *drex0, *drex1;
  381. struct exynos5420_tzasc *tzasc0, *tzasc1;
  382. struct exynos5_power *pmu;
  383. uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
  384. uint32_t lock0_info, lock1_info;
  385. int chip;
  386. int i;
  387. phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
  388. phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
  389. + DMC_OFFSET);
  390. drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
  391. drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
  392. + DMC_OFFSET);
  393. tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
  394. tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
  395. + DMC_OFFSET);
  396. pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
  397. if (CONFIG_NR_DRAM_BANKS > 4) {
  398. /* Need both controllers. */
  399. mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
  400. mem->chips_per_channel = 2;
  401. mem->chips_to_configure = 2;
  402. } else {
  403. /* 2GB requires a single controller */
  404. mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
  405. }
  406. /* Enable PAUSE for DREX */
  407. setbits_le32(&clk->pause, ENABLE_BIT);
  408. /* Enable BYPASS mode */
  409. setbits_le32(&clk->bpll_con1, BYPASS_EN);
  410. writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
  411. do {
  412. val = readl(&clk->mux_stat_cdrex);
  413. val &= BPLL_SEL_MASK;
  414. } while (val != FOUTBPLL);
  415. clrbits_le32(&clk->bpll_con1, BYPASS_EN);
  416. /* Specify the DDR memory type as DDR3 */
  417. val = readl(&phy0_ctrl->phy_con0);
  418. val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
  419. val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
  420. writel(val, &phy0_ctrl->phy_con0);
  421. val = readl(&phy1_ctrl->phy_con0);
  422. val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
  423. val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
  424. writel(val, &phy1_ctrl->phy_con0);
  425. /* Set Read Latency and Burst Length for PHY0 and PHY1 */
  426. val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
  427. (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
  428. writel(val, &phy0_ctrl->phy_con42);
  429. writel(val, &phy1_ctrl->phy_con42);
  430. val = readl(&phy0_ctrl->phy_con26);
  431. val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
  432. val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
  433. writel(val, &phy0_ctrl->phy_con26);
  434. val = readl(&phy1_ctrl->phy_con26);
  435. val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
  436. val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
  437. writel(val, &phy1_ctrl->phy_con26);
  438. /*
  439. * Set Driver strength for CK, CKE, CS & CA to 0x7
  440. * Set Driver strength for Data Slice 0~3 to 0x7
  441. */
  442. val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
  443. (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
  444. val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
  445. (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
  446. writel(val, &phy0_ctrl->phy_con39);
  447. writel(val, &phy1_ctrl->phy_con39);
  448. /* ZQ Calibration */
  449. if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
  450. &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
  451. return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
  452. clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
  453. clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
  454. /* DQ Signal */
  455. val = readl(&phy0_ctrl->phy_con14);
  456. val |= mem->phy0_pulld_dqs;
  457. writel(val, &phy0_ctrl->phy_con14);
  458. val = readl(&phy1_ctrl->phy_con14);
  459. val |= mem->phy1_pulld_dqs;
  460. writel(val, &phy1_ctrl->phy_con14);
  461. val = MEM_TERM_EN | PHY_TERM_EN;
  462. writel(val, &drex0->phycontrol0);
  463. writel(val, &drex1->phycontrol0);
  464. writel(mem->concontrol |
  465. (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
  466. (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
  467. &drex0->concontrol);
  468. writel(mem->concontrol |
  469. (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
  470. (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
  471. &drex1->concontrol);
  472. do {
  473. val = readl(&drex0->phystatus);
  474. } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
  475. do {
  476. val = readl(&drex1->phystatus);
  477. } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
  478. clrbits_le32(&drex0->concontrol, DFI_INIT_START);
  479. clrbits_le32(&drex1->concontrol, DFI_INIT_START);
  480. update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
  481. update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
  482. /*
  483. * Set Base Address:
  484. * 0x2000_0000 ~ 0x5FFF_FFFF
  485. * 0x6000_0000 ~ 0x9FFF_FFFF
  486. */
  487. /* MEMBASECONFIG0 */
  488. val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
  489. DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
  490. writel(val, &tzasc0->membaseconfig0);
  491. writel(val, &tzasc1->membaseconfig0);
  492. /* MEMBASECONFIG1 */
  493. val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
  494. DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
  495. writel(val, &tzasc0->membaseconfig1);
  496. writel(val, &tzasc1->membaseconfig1);
  497. /*
  498. * Memory Channel Inteleaving Size
  499. * Ares Channel interleaving = 128 bytes
  500. */
  501. /* MEMCONFIG0/1 */
  502. writel(mem->memconfig, &tzasc0->memconfig0);
  503. writel(mem->memconfig, &tzasc1->memconfig0);
  504. writel(mem->memconfig, &tzasc0->memconfig1);
  505. writel(mem->memconfig, &tzasc1->memconfig1);
  506. /* Precharge Configuration */
  507. writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
  508. &drex0->prechconfig0);
  509. writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
  510. &drex1->prechconfig0);
  511. /*
  512. * TimingRow, TimingData, TimingPower and Timingaref
  513. * values as per Memory AC parameters
  514. */
  515. writel(mem->timing_ref, &drex0->timingref);
  516. writel(mem->timing_ref, &drex1->timingref);
  517. writel(mem->timing_row, &drex0->timingrow0);
  518. writel(mem->timing_row, &drex1->timingrow0);
  519. writel(mem->timing_data, &drex0->timingdata0);
  520. writel(mem->timing_data, &drex1->timingdata0);
  521. writel(mem->timing_power, &drex0->timingpower0);
  522. writel(mem->timing_power, &drex1->timingpower0);
  523. if (reset) {
  524. /*
  525. * Send NOP, MRS and ZQINIT commands
  526. * Sending MRS command will reset the DRAM. We should not be
  527. * resetting the DRAM after resume, this will lead to memory
  528. * corruption as DRAM content is lost after DRAM reset
  529. */
  530. dmc_config_mrs(mem, &drex0->directcmd);
  531. dmc_config_mrs(mem, &drex1->directcmd);
  532. }
  533. /*
  534. * Get PHY_CON13 from both phys. Gate CLKM around reading since
  535. * PHY_CON13 is glitchy when CLKM is running. We're paranoid and
  536. * wait until we get a "fine lock", though a coarse lock is probably
  537. * OK (we only use the coarse numbers below). We try to gate the
  538. * clock for as short a time as possible in case SDRAM is somehow
  539. * sensitive. sdelay(10) in the loop is arbitrary to make sure
  540. * there is some time for PHY_CON13 to get updated. In practice
  541. * no delay appears to be needed.
  542. */
  543. val = readl(&clk->gate_bus_cdrex);
  544. while (true) {
  545. writel(val & ~0x1, &clk->gate_bus_cdrex);
  546. lock0_info = readl(&phy0_ctrl->phy_con13);
  547. writel(val, &clk->gate_bus_cdrex);
  548. if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
  549. break;
  550. sdelay(10);
  551. }
  552. while (true) {
  553. writel(val & ~0x2, &clk->gate_bus_cdrex);
  554. lock1_info = readl(&phy1_ctrl->phy_con13);
  555. writel(val, &clk->gate_bus_cdrex);
  556. if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
  557. break;
  558. sdelay(10);
  559. }
  560. if (!reset) {
  561. /*
  562. * During Suspend-Resume & S/W-Reset, as soon as PMU releases
  563. * pad retention, CKE goes high. This causes memory contents
  564. * not to be retained during DRAM initialization. Therfore,
  565. * there is a new control register(0x100431e8[28]) which lets us
  566. * release pad retention and retain the memory content until the
  567. * initialization is complete.
  568. */
  569. writel(PAD_RETENTION_DRAM_COREBLK_VAL,
  570. &power->pad_retention_dram_coreblk_option);
  571. do {
  572. val = readl(&power->pad_retention_dram_status);
  573. } while (val != 0x1);
  574. /*
  575. * CKE PAD retention disables DRAM self-refresh mode.
  576. * Send auto refresh command for DRAM refresh.
  577. */
  578. for (i = 0; i < 128; i++) {
  579. for (chip = 0; chip < mem->chips_to_configure; chip++) {
  580. writel(DIRECT_CMD_REFA |
  581. (chip << DIRECT_CMD_CHIP_SHIFT),
  582. &drex0->directcmd);
  583. writel(DIRECT_CMD_REFA |
  584. (chip << DIRECT_CMD_CHIP_SHIFT),
  585. &drex1->directcmd);
  586. }
  587. }
  588. }
  589. if (mem->gate_leveling_enable) {
  590. writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
  591. writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
  592. setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
  593. setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
  594. val = PHY_CON2_RESET_VAL;
  595. val |= INIT_DESKEW_EN;
  596. writel(val, &phy0_ctrl->phy_con2);
  597. writel(val, &phy1_ctrl->phy_con2);
  598. val = readl(&phy0_ctrl->phy_con1);
  599. val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
  600. writel(val, &phy0_ctrl->phy_con1);
  601. val = readl(&phy1_ctrl->phy_con1);
  602. val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
  603. writel(val, &phy1_ctrl->phy_con1);
  604. n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
  605. n_lock_r = readl(&phy0_ctrl->phy_con12);
  606. n_lock_r &= ~CTRL_DLL_ON;
  607. n_lock_r |= n_lock_w_phy0;
  608. writel(n_lock_r, &phy0_ctrl->phy_con12);
  609. n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
  610. n_lock_r = readl(&phy1_ctrl->phy_con12);
  611. n_lock_r &= ~CTRL_DLL_ON;
  612. n_lock_r |= n_lock_w_phy1;
  613. writel(n_lock_r, &phy1_ctrl->phy_con12);
  614. val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
  615. for (chip = 0; chip < mem->chips_to_configure; chip++) {
  616. writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
  617. &drex0->directcmd);
  618. writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
  619. &drex1->directcmd);
  620. }
  621. setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
  622. setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
  623. setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
  624. setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
  625. val = readl(&phy0_ctrl->phy_con1);
  626. val &= ~(CTRL_GATEDURADJ_MASK);
  627. writel(val, &phy0_ctrl->phy_con1);
  628. val = readl(&phy1_ctrl->phy_con1);
  629. val &= ~(CTRL_GATEDURADJ_MASK);
  630. writel(val, &phy1_ctrl->phy_con1);
  631. writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
  632. i = TIMEOUT_US;
  633. while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
  634. RDLVL_COMPLETE_CHO) && (i > 0)) {
  635. /*
  636. * TODO(waihong): Comment on how long this take to
  637. * timeout
  638. */
  639. sdelay(100);
  640. i--;
  641. }
  642. if (!i)
  643. return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
  644. writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
  645. writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
  646. i = TIMEOUT_US;
  647. while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
  648. RDLVL_COMPLETE_CHO) && (i > 0)) {
  649. /*
  650. * TODO(waihong): Comment on how long this take to
  651. * timeout
  652. */
  653. sdelay(100);
  654. i--;
  655. }
  656. if (!i)
  657. return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
  658. writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
  659. writel(0, &phy0_ctrl->phy_con14);
  660. writel(0, &phy1_ctrl->phy_con14);
  661. val = (0x3 << DIRECT_CMD_BANK_SHIFT);
  662. for (chip = 0; chip < mem->chips_to_configure; chip++) {
  663. writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
  664. &drex0->directcmd);
  665. writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
  666. &drex1->directcmd);
  667. }
  668. /* Common Settings for Leveling */
  669. val = PHY_CON12_RESET_VAL;
  670. writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
  671. writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
  672. setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
  673. setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
  674. }
  675. /*
  676. * Do software read leveling
  677. *
  678. * Do this before we turn on auto refresh since the auto refresh can
  679. * be in conflict with the resync operation that's part of setting
  680. * read leveling.
  681. */
  682. if (!reset) {
  683. /* restore calibrated value after resume */
  684. dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
  685. dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));
  686. } else {
  687. software_find_read_offset(phy0_ctrl, 0,
  688. CTRL_LOCK_COARSE(lock0_info));
  689. software_find_read_offset(phy1_ctrl, 1,
  690. CTRL_LOCK_COARSE(lock1_info));
  691. /* save calibrated value to restore after resume */
  692. writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
  693. writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);
  694. }
  695. /* Send PALL command */
  696. dmc_config_prech(mem, &drex0->directcmd);
  697. dmc_config_prech(mem, &drex1->directcmd);
  698. writel(mem->memcontrol, &drex0->memcontrol);
  699. writel(mem->memcontrol, &drex1->memcontrol);
  700. /*
  701. * Set DMC Concontrol: Enable auto-refresh counter, provide
  702. * read data fetch cycles and enable DREX auto set powerdown
  703. * for input buffer of I/O in none read memory state.
  704. */
  705. writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
  706. (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
  707. DMC_CONCONTROL_IO_PD_CON(0x2),
  708. &drex0->concontrol);
  709. writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
  710. (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
  711. DMC_CONCONTROL_IO_PD_CON(0x2),
  712. &drex1->concontrol);
  713. /*
  714. * Enable Clock Gating Control for DMC
  715. * this saves around 25 mw dmc power as compared to the power
  716. * consumption without these bits enabled
  717. */
  718. setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
  719. setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
  720. /*
  721. * As per Exynos5800 UM ver 0.00 section 17.13.2.1
  722. * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
  723. * support the PHY initiated update. And it is recommended to set
  724. * this field to 1'b1 during initialization
  725. *
  726. * When we apply PHY-initiated mode, DLL lock value is determined
  727. * once at DMC init time and not updated later when we change the MIF
  728. * voltage based on ASV group in kernel. Applying MC-initiated mode
  729. * makes sure that DLL tracing is ON so that silicon is able to
  730. * compensate the voltage variation.
  731. */
  732. val = readl(&drex0->concontrol);
  733. val |= CONCONTROL_UPDATE_MODE;
  734. writel(val, &drex0->concontrol);
  735. val = readl(&drex1->concontrol);
  736. val |= CONCONTROL_UPDATE_MODE;
  737. writel(val, &drex1->concontrol);
  738. return 0;
  739. }
  740. #endif