common_setup.h 2.6 KB

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  1. /*
  2. * Common APIs for EXYNOS based board
  3. *
  4. * Copyright (C) 2013 Samsung Electronics
  5. * Rajeshwari Shinde <rajeshwari.s@samsung.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <asm/arch/system.h>
  26. #define DMC_OFFSET 0x10000
  27. /*
  28. * Memory initialization
  29. *
  30. * @param reset Reset PHY during initialization.
  31. */
  32. void mem_ctrl_init(int reset);
  33. /* System Clock initialization */
  34. void system_clock_init(void);
  35. /*
  36. * Init subsystems according to the reset status
  37. *
  38. * Return: 0 for a normal boot, non-zero for a resume
  39. */
  40. int do_lowlevel_init(void);
  41. void sdelay(unsigned long);
  42. enum l2_cache_params {
  43. CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
  44. CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
  45. CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
  46. CACHE_DATA_RAM_SETUP = (1 << 5),
  47. CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
  48. CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
  49. CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
  50. CACHE_TAG_RAM_SETUP = (1 << 9),
  51. CACHE_ECC_AND_PARITY = (1 << 21),
  52. CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
  53. };
  54. #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
  55. /*
  56. * Configure L2CTLR to get timings that keep us from hanging/crashing.
  57. *
  58. * Must be inline here since low_power_start() is called without a
  59. * stack (!).
  60. */
  61. static inline void configure_l2_ctlr(void)
  62. {
  63. uint32_t val;
  64. mrc_l2_ctlr(val);
  65. val |= CACHE_TAG_RAM_SETUP |
  66. CACHE_DATA_RAM_SETUP |
  67. CACHE_TAG_RAM_LATENCY_2_CYCLES |
  68. CACHE_DATA_RAM_LATENCY_2_CYCLES;
  69. if (proid_is_exynos542x()) {
  70. val |= CACHE_ECC_AND_PARITY |
  71. CACHE_TAG_RAM_LATENCY_3_CYCLES |
  72. CACHE_DATA_RAM_LATENCY_3_CYCLES;
  73. }
  74. mcr_l2_ctlr(val);
  75. }
  76. /*
  77. * Configure L2ACTLR.
  78. *
  79. * Must be inline here since low_power_start() is called without a
  80. * stack (!).
  81. */
  82. static inline void configure_l2_actlr(void)
  83. {
  84. uint32_t val;
  85. if (proid_is_exynos542x()) {
  86. mrc_l2_aux_ctlr(val);
  87. val |= CACHE_ENABLE_FORCE_L2_LOGIC |
  88. CACHE_DISABLE_CLEAN_EVICT;
  89. mcr_l2_aux_ctlr(val);
  90. }
  91. }
  92. #endif