clock_init.h 3.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Clock initialization routines
  4. *
  5. * Copyright (c) 2011 The Chromium OS Authors.
  6. */
  7. #ifndef __EXYNOS_CLOCK_INIT_H
  8. #define __EXYNOS_CLOCK_INIT_H
  9. enum {
  10. #ifdef CONFIG_EXYNOS5420
  11. MEM_TIMINGS_MSR_COUNT = 5,
  12. #else
  13. MEM_TIMINGS_MSR_COUNT = 4,
  14. #endif
  15. };
  16. /* These are the ratio's for configuring ARM clock */
  17. struct arm_clk_ratios {
  18. unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
  19. unsigned apll_mdiv;
  20. unsigned apll_pdiv;
  21. unsigned apll_sdiv;
  22. unsigned arm2_ratio;
  23. unsigned apll_ratio;
  24. unsigned pclk_dbg_ratio;
  25. unsigned atb_ratio;
  26. unsigned periph_ratio;
  27. unsigned acp_ratio;
  28. unsigned cpud_ratio;
  29. unsigned arm_ratio;
  30. };
  31. /* These are the memory timings for a particular memory type and speed */
  32. struct mem_timings {
  33. enum mem_manuf mem_manuf; /* Memory manufacturer */
  34. enum ddr_mode mem_type; /* Memory type */
  35. unsigned frequency_mhz; /* Frequency of memory in MHz */
  36. /* Here follow the timing parameters for the selected memory */
  37. unsigned apll_mdiv;
  38. unsigned apll_pdiv;
  39. unsigned apll_sdiv;
  40. unsigned mpll_mdiv;
  41. unsigned mpll_pdiv;
  42. unsigned mpll_sdiv;
  43. unsigned cpll_mdiv;
  44. unsigned cpll_pdiv;
  45. unsigned cpll_sdiv;
  46. unsigned gpll_mdiv;
  47. unsigned gpll_pdiv;
  48. unsigned gpll_sdiv;
  49. unsigned epll_mdiv;
  50. unsigned epll_pdiv;
  51. unsigned epll_sdiv;
  52. unsigned vpll_mdiv;
  53. unsigned vpll_pdiv;
  54. unsigned vpll_sdiv;
  55. unsigned bpll_mdiv;
  56. unsigned bpll_pdiv;
  57. unsigned bpll_sdiv;
  58. unsigned kpll_mdiv;
  59. unsigned kpll_pdiv;
  60. unsigned kpll_sdiv;
  61. unsigned dpll_mdiv;
  62. unsigned dpll_pdiv;
  63. unsigned dpll_sdiv;
  64. unsigned ipll_mdiv;
  65. unsigned ipll_pdiv;
  66. unsigned ipll_sdiv;
  67. unsigned spll_mdiv;
  68. unsigned spll_pdiv;
  69. unsigned spll_sdiv;
  70. unsigned rpll_mdiv;
  71. unsigned rpll_pdiv;
  72. unsigned rpll_sdiv;
  73. unsigned pclk_cdrex_ratio;
  74. unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
  75. unsigned timing_ref;
  76. unsigned timing_row;
  77. unsigned timing_data;
  78. unsigned timing_power;
  79. /* DQS, DQ, DEBUG offsets */
  80. unsigned phy0_dqs;
  81. unsigned phy1_dqs;
  82. unsigned phy0_dq;
  83. unsigned phy1_dq;
  84. unsigned phy0_tFS;
  85. unsigned phy1_tFS;
  86. unsigned phy0_pulld_dqs;
  87. unsigned phy1_pulld_dqs;
  88. unsigned lpddr3_ctrl_phy_reset;
  89. unsigned ctrl_start_point;
  90. unsigned ctrl_inc;
  91. unsigned ctrl_start;
  92. unsigned ctrl_dll_on;
  93. unsigned ctrl_ref;
  94. unsigned ctrl_force;
  95. unsigned ctrl_rdlat;
  96. unsigned ctrl_bstlen;
  97. unsigned fp_resync;
  98. unsigned iv_size;
  99. unsigned dfi_init_start;
  100. unsigned aref_en;
  101. unsigned rd_fetch;
  102. unsigned zq_mode_dds;
  103. unsigned zq_mode_term;
  104. unsigned zq_mode_noterm; /* 1 to allow termination disable */
  105. unsigned memcontrol;
  106. unsigned memconfig;
  107. unsigned membaseconfig0;
  108. unsigned membaseconfig1;
  109. unsigned prechconfig_tp_cnt;
  110. unsigned dpwrdn_cyc;
  111. unsigned dsref_cyc;
  112. unsigned concontrol;
  113. /* Channel and Chip Selection */
  114. uint8_t dmc_channels; /* number of memory channels */
  115. uint8_t chips_per_channel; /* number of chips per channel */
  116. uint8_t chips_to_configure; /* number of chips to configure */
  117. uint8_t send_zq_init; /* 1 to send this command */
  118. unsigned impedance; /* drive strength impedeance */
  119. uint8_t gate_leveling_enable; /* check gate leveling is enabled */
  120. uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
  121. };
  122. /**
  123. * Get the correct memory timings for our selected memory type and speed.
  124. *
  125. * This function can be called from SPL or the main U-Boot.
  126. *
  127. * Return: pointer to the memory timings that we should use
  128. */
  129. struct mem_timings *clock_get_mem_timings(void);
  130. /*
  131. * Initialize clock for the device
  132. */
  133. void system_clock_init(void);
  134. /*
  135. * Set clock divisor value for booting from EMMC.
  136. */
  137. void emmc_boot_clk_div_set(void);
  138. #endif