warmboot.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010, 2011
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #ifndef _WARM_BOOT_H_
  7. #define _WARM_BOOT_H_
  8. #define STRAP_OPT_A_RAM_CODE_SHIFT 4
  9. #define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
  10. /* Defines the supported operating modes */
  11. enum fuse_operating_mode {
  12. MODE_PRODUCTION = 3,
  13. MODE_UNDEFINED,
  14. };
  15. /* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
  16. enum {
  17. HASH_LENGTH = 4
  18. };
  19. /* Defines the storage for a hash value (128 bits) */
  20. struct hash {
  21. u32 hash[HASH_LENGTH];
  22. };
  23. /*
  24. * Defines the code header information for the boot rom.
  25. *
  26. * The code immediately follows the code header.
  27. *
  28. * Note that the code header needs to be 16 bytes aligned to preserve
  29. * the alignment of relevant data for hash and decryption computations without
  30. * requiring extra copies to temporary memory areas.
  31. */
  32. struct wb_header {
  33. u32 length_insecure; /* length of the code header */
  34. u32 reserved[3];
  35. struct hash hash; /* hash of header+code, starts next field*/
  36. struct hash random_aes_block; /* a data block to aid security. */
  37. u32 length_secure; /* length of the code header */
  38. u32 destination; /* destination address to put the wb code */
  39. u32 entry_point; /* execution address of the wb code */
  40. u32 code_length; /* length of the code */
  41. };
  42. /*
  43. * The warm boot code needs direct access to these registers since it runs in
  44. * SRAM and cannot call other U-Boot code.
  45. */
  46. union osc_ctrl_reg {
  47. struct {
  48. u32 xoe:1;
  49. u32 xobp:1;
  50. u32 reserved0:2;
  51. u32 xofs:6;
  52. u32 reserved1:2;
  53. u32 xods:5;
  54. u32 reserved2:3;
  55. u32 oscfi_spare:8;
  56. u32 pll_ref_div:2;
  57. u32 osc_freq:2;
  58. };
  59. u32 word;
  60. };
  61. union pllx_base_reg {
  62. struct {
  63. u32 divm:5;
  64. u32 reserved0:3;
  65. u32 divn:10;
  66. u32 reserved1:2;
  67. u32 divp:3;
  68. u32 reserved2:4;
  69. u32 lock:1;
  70. u32 reserved3:1;
  71. u32 ref_dis:1;
  72. u32 enable:1;
  73. u32 bypass:1;
  74. };
  75. u32 word;
  76. };
  77. union pllx_misc_reg {
  78. struct {
  79. u32 vcocon:4;
  80. u32 lfcon:4;
  81. u32 cpcon:4;
  82. u32 lock_sel:6;
  83. u32 reserved0:1;
  84. u32 lock_enable:1;
  85. u32 reserved1:1;
  86. u32 dccon:1;
  87. u32 pts:2;
  88. u32 reserved2:6;
  89. u32 out1_div_byp:1;
  90. u32 out1_inv_clk:1;
  91. };
  92. u32 word;
  93. };
  94. /*
  95. * TODO: This register is not documented in the TRM yet. We could move this
  96. * into the EMC and give it a proper interface, but not while it is
  97. * undocumented.
  98. */
  99. union scratch3_reg {
  100. struct {
  101. u32 pllx_base_divm:5;
  102. u32 pllx_base_divn:10;
  103. u32 pllx_base_divp:3;
  104. u32 pllx_misc_lfcon:4;
  105. u32 pllx_misc_cpcon:4;
  106. };
  107. u32 word;
  108. };
  109. /**
  110. * Save warmboot memory settings for a later resume
  111. *
  112. * Return: 0 if ok, -1 on error
  113. */
  114. int warmboot_save_sdram_params(void);
  115. int warmboot_prepare_code(u32 seg_address, u32 seg_length);
  116. int sign_data_block(u8 *source, u32 length, u8 *signature);
  117. void wb_start(void); /* Start of WB assembly code */
  118. void wb_end(void); /* End of WB assembly code */
  119. #endif