wdt.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2016 Google, Inc
  4. */
  5. #ifndef _ASM_ARCH_WDT_H
  6. #define _ASM_ARCH_WDT_H
  7. #define WDT_BASE 0x1e785000
  8. /*
  9. * Special value that needs to be written to counter_restart register to
  10. * (re)start the timer
  11. */
  12. #define WDT_COUNTER_RESTART_VAL 0x4755
  13. /* Control register */
  14. #define WDT_CTRL_RESET_MODE_SHIFT 5
  15. #define WDT_CTRL_RESET_MODE_MASK 3
  16. #define WDT_CTRL_EN (1 << 0)
  17. #define WDT_CTRL_RESET (1 << 1)
  18. #define WDT_CTRL_CLK1MHZ (1 << 4)
  19. #define WDT_CTRL_2ND_BOOT (1 << 7)
  20. /* Values for Reset Mode */
  21. #define WDT_CTRL_RESET_SOC 0
  22. #define WDT_CTRL_RESET_CHIP 1
  23. #define WDT_CTRL_RESET_CPU 2
  24. #define WDT_CTRL_RESET_MASK 3
  25. /* Reset Mask register */
  26. #define WDT_RESET_ARM (1 << 0)
  27. #define WDT_RESET_COPROC (1 << 1)
  28. #define WDT_RESET_SDRAM (1 << 2)
  29. #define WDT_RESET_AHB (1 << 3)
  30. #define WDT_RESET_I2C (1 << 4)
  31. #define WDT_RESET_MAC1 (1 << 5)
  32. #define WDT_RESET_MAC2 (1 << 6)
  33. #define WDT_RESET_GCRT (1 << 7)
  34. #define WDT_RESET_USB20 (1 << 8)
  35. #define WDT_RESET_USB11_HOST (1 << 9)
  36. #define WDT_RESET_USB11_EHCI2 (1 << 10)
  37. #define WDT_RESET_VIDEO (1 << 11)
  38. #define WDT_RESET_HAC (1 << 12)
  39. #define WDT_RESET_LPC (1 << 13)
  40. #define WDT_RESET_SDSDIO (1 << 14)
  41. #define WDT_RESET_MIC (1 << 15)
  42. #define WDT_RESET_CRT2C (1 << 16)
  43. #define WDT_RESET_PWM (1 << 17)
  44. #define WDT_RESET_PECI (1 << 18)
  45. #define WDT_RESET_JTAG (1 << 19)
  46. #define WDT_RESET_ADC (1 << 20)
  47. #define WDT_RESET_GPIO (1 << 21)
  48. #define WDT_RESET_MCTP (1 << 22)
  49. #define WDT_RESET_XDMA (1 << 23)
  50. #define WDT_RESET_SPI (1 << 24)
  51. #define WDT_RESET_MISC (1 << 25)
  52. #define WDT_RESET_DEFAULT \
  53. (WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C | \
  54. WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT | \
  55. WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \
  56. WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC | \
  57. WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C | \
  58. WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG | \
  59. WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC)
  60. #ifndef __ASSEMBLY__
  61. struct ast_wdt {
  62. u32 counter_status;
  63. u32 counter_reload_val;
  64. u32 counter_restart;
  65. u32 ctrl;
  66. u32 timeout_status;
  67. u32 clr_timeout_status;
  68. u32 reset_width;
  69. /* On pre-ast2500 SoCs this register is reserved. */
  70. u32 reset_mask;
  71. };
  72. /**
  73. * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
  74. * gets Reset Mode value from it.
  75. *
  76. * @flags: flags parameter passed into wdt_reset or wdt_start
  77. * Return: Reset Mode value
  78. */
  79. u32 ast_reset_mode_from_flags(ulong flags);
  80. /**
  81. * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
  82. * gets Reset Mask value from it. Reset Mask is only supported on ast2500
  83. *
  84. * @flags: flags parameter passed into wdt_reset or wdt_start
  85. * Return: Reset Mask value
  86. */
  87. u32 ast_reset_mask_from_flags(ulong flags);
  88. /**
  89. * Given Reset Mask and Reset Mode values, converts them to flags,
  90. * suitable for passing into wdt_start or wdt_reset uclass functions.
  91. *
  92. * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
  93. * can both be packed into single 32 bits wide value.
  94. *
  95. * @reset_mode: Reset Mode
  96. * @reset_mask: Reset Mask
  97. */
  98. ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
  99. #endif /* __ASSEMBLY__ */
  100. #endif /* _ASM_ARCH_WDT_H */