scu_ast2500.h 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. */
  5. #ifndef _ASM_ARCH_SCU_AST2500_H
  6. #define _ASM_ARCH_SCU_AST2500_H
  7. #define SCU_UNLOCK_VALUE 0x1688a8a8
  8. #define SCU_HWSTRAP_VGAMEM_SHIFT 2
  9. #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT)
  10. #define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
  11. #define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
  12. #define SCU_HWSTRAP_DDR4 (1 << 24)
  13. #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23)
  14. #define SCU_MPLL_DENUM_SHIFT 0
  15. #define SCU_MPLL_DENUM_MASK 0x1f
  16. #define SCU_MPLL_NUM_SHIFT 5
  17. #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
  18. #define SCU_MPLL_POST_SHIFT 13
  19. #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
  20. #define SCU_PCLK_DIV_SHIFT 23
  21. #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
  22. #define SCU_SDCLK_DIV_SHIFT 12
  23. #define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT)
  24. #define SCU_HPLL_DENUM_SHIFT 0
  25. #define SCU_HPLL_DENUM_MASK 0x1f
  26. #define SCU_HPLL_NUM_SHIFT 5
  27. #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
  28. #define SCU_HPLL_POST_SHIFT 13
  29. #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
  30. #define SCU_MACCLK_SHIFT 16
  31. #define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT)
  32. #define SCU_MISC2_RGMII_HPLL (1 << 23)
  33. #define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
  34. #define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
  35. #define SCU_MISC2_RMII_MPLL (1 << 19)
  36. #define SCU_MISC2_RMII_CLKDIV_SHIFT 16
  37. #define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
  38. #define SCU_MISC2_UARTCLK_SHIFT 24
  39. #define SCU_MISC_D2PLL_OFF (1 << 4)
  40. #define SCU_MISC_UARTCLK_DIV13 (1 << 12)
  41. #define SCU_MISC_GCRT_USB20CLK (1 << 21)
  42. #define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0
  43. #define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
  44. << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
  45. #define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6
  46. #define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
  47. << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
  48. #define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
  49. #define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
  50. #define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
  51. #define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
  52. #define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
  53. #define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
  54. #define SCU_MICDS_RMII1_RCLKEN (1 << 29)
  55. #define SCU_MICDS_RMII2_RCLKEN (1 << 30)
  56. #define SCU_MICDS_RGMIIPLL (1 << 31)
  57. /*
  58. * SYSRESET is actually more like a Power register,
  59. * except that corresponding bit set to 1 means that
  60. * the peripheral is off.
  61. */
  62. #define SCU_SYSRESET_XDMA (1 << 25)
  63. #define SCU_SYSRESET_MCTP (1 << 24)
  64. #define SCU_SYSRESET_ADC (1 << 23)
  65. #define SCU_SYSRESET_JTAG (1 << 22)
  66. #define SCU_SYSRESET_MIC (1 << 18)
  67. #define SCU_SYSRESET_SDIO (1 << 16)
  68. #define SCU_SYSRESET_USB11HOST (1 << 15)
  69. #define SCU_SYSRESET_USBHUB (1 << 14)
  70. #define SCU_SYSRESET_CRT (1 << 13)
  71. #define SCU_SYSRESET_MAC2 (1 << 12)
  72. #define SCU_SYSRESET_MAC1 (1 << 11)
  73. #define SCU_SYSRESET_PECI (1 << 10)
  74. #define SCU_SYSRESET_PWM (1 << 9)
  75. #define SCU_SYSRESET_PCI_VGA (1 << 8)
  76. #define SCU_SYSRESET_2D (1 << 7)
  77. #define SCU_SYSRESET_VIDEO (1 << 6)
  78. #define SCU_SYSRESET_LPC (1 << 5)
  79. #define SCU_SYSRESET_HAC (1 << 4)
  80. #define SCU_SYSRESET_USBHID (1 << 3)
  81. #define SCU_SYSRESET_I2C (1 << 2)
  82. #define SCU_SYSRESET_AHB (1 << 1)
  83. #define SCU_SYSRESET_SDRAM_WDT (1 << 0)
  84. /* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
  85. #define SCU_PINMUX_CTRL5_I2C (1 << 16)
  86. /*
  87. * The values are grouped by function, not by register.
  88. * They are actually scattered across multiple loosely related registers.
  89. */
  90. #define SCU_PIN_FUN_MAC1_MDC (1 << 30)
  91. #define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
  92. #define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
  93. #define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
  94. #define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
  95. #define SCU_PIN_FUN_SCL1 (1 << 12)
  96. #define SCU_PIN_FUN_SCL2 (1 << 14)
  97. #define SCU_PIN_FUN_SDA1 (1 << 13)
  98. #define SCU_PIN_FUN_SDA2 (1 << 15)
  99. #define SCU_CLKSTOP_MAC1 (1 << 20)
  100. #define SCU_CLKSTOP_MAC2 (1 << 21)
  101. #define SCU_CLKSTOP_SDCLK (1 << 27)
  102. #define SCU_D2PLL_EXT1_OFF (1 << 0)
  103. #define SCU_D2PLL_EXT1_BYPASS (1 << 1)
  104. #define SCU_D2PLL_EXT1_RESET (1 << 2)
  105. #define SCU_D2PLL_EXT1_MODE_SHIFT 3
  106. #define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
  107. #define SCU_D2PLL_EXT1_PARAM_SHIFT 5
  108. #define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
  109. #define SCU_D2PLL_NUM_SHIFT 0
  110. #define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
  111. #define SCU_D2PLL_DENUM_SHIFT 8
  112. #define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
  113. #define SCU_D2PLL_POST_SHIFT 13
  114. #define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT)
  115. #define SCU_D2PLL_ODIV_SHIFT 19
  116. #define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT)
  117. #define SCU_D2PLL_SIC_SHIFT 22
  118. #define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT)
  119. #define SCU_D2PLL_SIP_SHIFT 27
  120. #define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT)
  121. #define SCU_CLKDUTY_DCLK_SHIFT 0
  122. #define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT)
  123. #define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8
  124. #define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT)
  125. #define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16
  126. #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
  127. #ifndef __ASSEMBLY__
  128. struct ast2500_clk_priv {
  129. struct ast2500_scu *scu;
  130. };
  131. struct ast2500_scu {
  132. u32 protection_key;
  133. u32 sysreset_ctrl1;
  134. u32 clk_sel1;
  135. u32 clk_stop_ctrl1;
  136. u32 freq_counter_ctrl;
  137. u32 freq_counter_cmp;
  138. u32 intr_ctrl;
  139. u32 d2_pll_param;
  140. u32 m_pll_param;
  141. u32 h_pll_param;
  142. u32 d_pll_param;
  143. u32 misc_ctrl1;
  144. u32 pci_config[3];
  145. u32 sysreset_status;
  146. u32 vga_handshake[2];
  147. u32 mac_clk_delay;
  148. u32 misc_ctrl2;
  149. u32 vga_scratch[8];
  150. u32 hwstrap;
  151. u32 rng_ctrl;
  152. u32 rng_data;
  153. u32 rev_id;
  154. u32 pinmux_ctrl[6];
  155. u32 reserved0;
  156. u32 extrst_sel;
  157. u32 pinmux_ctrl1[4];
  158. u32 reserved1[2];
  159. u32 mac_clk_delay_100M;
  160. u32 mac_clk_delay_10M;
  161. u32 wakeup_enable;
  162. u32 wakeup_control;
  163. u32 reserved2[3];
  164. u32 sysreset_ctrl2;
  165. u32 clk_sel2;
  166. u32 clk_stop_ctrl2;
  167. u32 freerun_counter;
  168. u32 freerun_counter_ext;
  169. u32 clk_duty_meas_ctrl;
  170. u32 clk_duty_meas_res;
  171. u32 reserved3[4];
  172. /* The next registers are not key-protected */
  173. struct ast2500_cpu2 {
  174. u32 ctrl;
  175. u32 base_addr[9];
  176. u32 cache_ctrl;
  177. } cpu2;
  178. u32 reserved4;
  179. u32 d_pll_ext_param[3];
  180. u32 d2_pll_ext_param[3];
  181. u32 mh_pll_ext_param;
  182. u32 reserved5;
  183. u32 chip_id[2];
  184. u32 reserved6[2];
  185. u32 uart_clk_ctrl;
  186. u32 reserved7[7];
  187. u32 pcie_config;
  188. u32 mmio_decode;
  189. u32 reloc_ctrl_decode[2];
  190. u32 mailbox_addr;
  191. u32 shared_sram_decode[2];
  192. u32 bmc_rev_id;
  193. u32 reserved8;
  194. u32 bmc_device_id;
  195. u32 reserved9[13];
  196. u32 clk_duty_sel;
  197. };
  198. /**
  199. * ast_get_clk() - get a pointer to Clock Driver
  200. *
  201. * @devp, OUT - pointer to Clock Driver
  202. * Return: zero on success, error code (< 0) otherwise.
  203. */
  204. int ast_get_clk(struct udevice **devp);
  205. /**
  206. * ast_get_scu() - get a pointer to SCU registers
  207. *
  208. * Return: pointer to struct ast2500_scu on success, ERR_PTR otherwise
  209. */
  210. void *ast_get_scu(void);
  211. /**
  212. * ast_scu_unlock() - unlock protected registers
  213. *
  214. * @scu, pointer to ast2500_scu
  215. */
  216. void ast_scu_unlock(struct ast2500_scu *scu);
  217. /**
  218. * ast_scu_lock() - lock protected registers
  219. *
  220. * @scu, pointer to ast2500_scu
  221. */
  222. void ast_scu_lock(struct ast2500_scu *scu);
  223. #endif /* __ASSEMBLY__ */
  224. #endif /* _ASM_ARCH_SCU_AST2500_H */