mt8183.dtsi 6.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (C) 2021 MediaTek Inc.
  4. * Copyright (C) 2021 BayLibre, SAS
  5. * Author: Ben Ho <ben.ho@mediatek.com>
  6. * Erin Lo <erin.lo@mediatek.com>
  7. * Fabien Parent <fparent@baylibre.com>
  8. */
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/clock/mt8183-clk.h>
  11. #include <dt-bindings/interrupt-controller/irq.h>
  12. #include <dt-bindings/interrupt-controller/arm-gic.h>
  13. #include <dt-bindings/phy/phy.h>
  14. / {
  15. compatible = "mediatek,mt8183";
  16. interrupt-parent = <&sysirq>;
  17. #address-cells = <2>;
  18. #size-cells = <2>;
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. cpu-map {
  23. cluster0 {
  24. core0 {
  25. cpu = <&cpu0>;
  26. };
  27. core1 {
  28. cpu = <&cpu1>;
  29. };
  30. core2 {
  31. cpu = <&cpu2>;
  32. };
  33. core3 {
  34. cpu = <&cpu3>;
  35. };
  36. };
  37. cluster1 {
  38. core0 {
  39. cpu = <&cpu4>;
  40. };
  41. core1 {
  42. cpu = <&cpu5>;
  43. };
  44. core2 {
  45. cpu = <&cpu6>;
  46. };
  47. core3 {
  48. cpu = <&cpu7>;
  49. };
  50. };
  51. };
  52. cpu0: cpu@0 {
  53. device_type = "cpu";
  54. compatible = "arm,cortex-a53";
  55. reg = <0x000>;
  56. enable-method = "psci";
  57. capacity-dmips-mhz = <741>;
  58. };
  59. cpu1: cpu@1 {
  60. device_type = "cpu";
  61. compatible = "arm,cortex-a53";
  62. reg = <0x001>;
  63. enable-method = "psci";
  64. capacity-dmips-mhz = <741>;
  65. };
  66. cpu2: cpu@2 {
  67. device_type = "cpu";
  68. compatible = "arm,cortex-a53";
  69. reg = <0x002>;
  70. enable-method = "psci";
  71. capacity-dmips-mhz = <741>;
  72. };
  73. cpu3: cpu@3 {
  74. device_type = "cpu";
  75. compatible = "arm,cortex-a53";
  76. reg = <0x003>;
  77. enable-method = "psci";
  78. capacity-dmips-mhz = <741>;
  79. };
  80. cpu4: cpu@100 {
  81. device_type = "cpu";
  82. compatible = "arm,cortex-a73";
  83. reg = <0x100>;
  84. enable-method = "psci";
  85. capacity-dmips-mhz = <1024>;
  86. };
  87. cpu5: cpu@101 {
  88. device_type = "cpu";
  89. compatible = "arm,cortex-a73";
  90. reg = <0x101>;
  91. enable-method = "psci";
  92. capacity-dmips-mhz = <1024>;
  93. };
  94. cpu6: cpu@102 {
  95. device_type = "cpu";
  96. compatible = "arm,cortex-a73";
  97. reg = <0x102>;
  98. enable-method = "psci";
  99. capacity-dmips-mhz = <1024>;
  100. };
  101. cpu7: cpu@103 {
  102. device_type = "cpu";
  103. compatible = "arm,cortex-a73";
  104. reg = <0x103>;
  105. enable-method = "psci";
  106. capacity-dmips-mhz = <1024>;
  107. };
  108. };
  109. clk26m: oscillator {
  110. compatible = "fixed-clock";
  111. #clock-cells = <0>;
  112. clock-frequency = <26000000>;
  113. clock-output-names = "clk26m";
  114. };
  115. soc {
  116. #address-cells = <2>;
  117. #size-cells = <2>;
  118. compatible = "simple-bus";
  119. ranges;
  120. watchdog: watchdog@10007000 {
  121. compatible = "mediatek,mt8183-wdt",
  122. "mediatek,wdt";
  123. reg = <0 0x10007000 0 0x100>;
  124. status = "disabled";
  125. };
  126. gic: interrupt-controller@c000000 {
  127. compatible = "arm,gic-v3";
  128. #interrupt-cells = <4>;
  129. interrupt-parent = <&gic>;
  130. interrupt-controller;
  131. reg = <0 0x0c000000 0 0x40000>, /* GICD */
  132. <0 0x0c100000 0 0x200000>, /* GICR */
  133. <0 0x0c400000 0 0x2000>, /* GICC */
  134. <0 0x0c410000 0 0x1000>, /* GICH */
  135. <0 0x0c420000 0 0x2000>; /* GICV */
  136. interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
  137. ppi-partitions {
  138. ppi_cluster0: interrupt-partition-0 {
  139. affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
  140. };
  141. ppi_cluster1: interrupt-partition-1 {
  142. affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
  143. };
  144. };
  145. };
  146. sysirq: interrupt-controller@c530a80 {
  147. compatible = "mediatek,mt8183-sysirq",
  148. "mediatek,mt6577-sysirq";
  149. interrupt-controller;
  150. #interrupt-cells = <3>;
  151. interrupt-parent = <&gic>;
  152. reg = <0 0x0c530a80 0 0x50>;
  153. };
  154. topckgen: syscon@10000000 {
  155. compatible = "mediatek,mt8183-topckgen", "syscon";
  156. reg = <0 0x10000000 0 0x1000>;
  157. #clock-cells = <1>;
  158. };
  159. infracfg: syscon@10001000 {
  160. compatible = "mediatek,mt8183-infracfg", "syscon";
  161. reg = <0 0x10001000 0 0x1000>;
  162. #clock-cells = <1>;
  163. };
  164. apmixedsys: syscon@1000c000 {
  165. compatible = "mediatek,mt8183-apmixedsys", "syscon";
  166. reg = <0 0x1000c000 0 0x1000>;
  167. #clock-cells = <1>;
  168. };
  169. uart0: serial@11002000 {
  170. compatible = "mediatek,mt8183-uart",
  171. "mediatek,hsuart";
  172. reg = <0 0x11002000 0 0x1000>;
  173. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
  174. clock-frequency = <26000000>;
  175. clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
  176. clock-names = "baud", "bus";
  177. status = "disabled";
  178. };
  179. mmc0: mmc@11230000 {
  180. compatible = "mediatek,mt8183-mmc";
  181. reg = <0 0x11230000 0 0x1000>,
  182. <0 0x11f50000 0 0x1000>;
  183. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
  184. clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
  185. <&infracfg CLK_INFRA_MSDC0>,
  186. <&infracfg CLK_INFRA_MSDC0_SCK>;
  187. clock-names = "source", "hclk", "source_cg";
  188. status = "disabled";
  189. };
  190. u3phy: usb-phy@11f40000 {
  191. compatible = "mediatek,generic-tphy-v2";
  192. #address-cells = <2>;
  193. #size-cells = <2>;
  194. ranges;
  195. status = "okay";
  196. u2port0: usb-phy2@11f40000 {
  197. reg = <0 0x11f40000 0 0x700>;
  198. clocks = <&clk26m>;
  199. clock-names = "ref";
  200. #phy-cells = <1>;
  201. status = "okay";
  202. };
  203. u3port0: usb-phy3@11f40700 {
  204. reg = <0 0x11f40700 0 0x900>;
  205. clocks = <&clk26m>;
  206. clock-names = "ref";
  207. #phy-cells = <1>;
  208. status = "okay";
  209. };
  210. };
  211. usb: usb@11200000 {
  212. compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
  213. reg = <0 0x11200000 0 0x3e00>,
  214. <0 0x11203e00 0 0x0100>;
  215. reg-names = "mac", "ippc";
  216. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
  217. phys = <&u2port0 PHY_TYPE_USB2>;
  218. clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
  219. <&infracfg CLK_INFRA_USB>;
  220. clock-names = "sys_ck", "ref_ck";
  221. #address-cells = <2>;
  222. #size-cells = <2>;
  223. ranges;
  224. status = "disabled";
  225. ssusb: ssusb@11200000 {
  226. compatible = "mediatek,ssusb";
  227. reg = <0 0x11200000 0 0x3e00>;
  228. reg-names = "mac";
  229. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
  230. status = "disabled";
  231. };
  232. usb_host: xhci@11200000 {
  233. compatible = "mediatek,mtk-xhci";
  234. reg = <0 0x11200000 0 0x1000>;
  235. reg-names = "mac";
  236. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
  237. clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
  238. <&infracfg CLK_INFRA_USB>;
  239. clock-names = "sys_ck", "ref_ck";
  240. status = "disabled";
  241. };
  242. };
  243. };
  244. };