tegra.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <fdtdec.h>
  8. #include <panel.h>
  9. #include <pwm.h>
  10. #include <video.h>
  11. #include <asm/system.h>
  12. #include <asm/gpio.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/funcmux.h>
  16. #include <asm/arch/pinmux.h>
  17. #include <asm/arch/pwm.h>
  18. #include <asm/arch/display.h>
  19. #include <asm/arch-tegra/timer.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /* Information about the display controller */
  22. struct tegra_lcd_priv {
  23. int width; /* width in pixels */
  24. int height; /* height in pixels */
  25. enum video_log2_bpp log2_bpp; /* colour depth */
  26. struct display_timing timing;
  27. struct udevice *panel;
  28. struct disp_ctlr *disp; /* Display controller to use */
  29. fdt_addr_t frame_buffer; /* Address of frame buffer */
  30. unsigned pixel_clock; /* Pixel clock in Hz */
  31. };
  32. enum {
  33. /* Maximum LCD size we support */
  34. LCD_MAX_WIDTH = 1366,
  35. LCD_MAX_HEIGHT = 768,
  36. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  37. };
  38. static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
  39. {
  40. unsigned h_dda, v_dda;
  41. unsigned long val;
  42. val = readl(&dc->cmd.disp_win_header);
  43. val |= WINDOW_A_SELECT;
  44. writel(val, &dc->cmd.disp_win_header);
  45. writel(win->fmt, &dc->win.color_depth);
  46. clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
  47. BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
  48. val = win->out_x << H_POSITION_SHIFT;
  49. val |= win->out_y << V_POSITION_SHIFT;
  50. writel(val, &dc->win.pos);
  51. val = win->out_w << H_SIZE_SHIFT;
  52. val |= win->out_h << V_SIZE_SHIFT;
  53. writel(val, &dc->win.size);
  54. val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
  55. val |= win->h << V_PRESCALED_SIZE_SHIFT;
  56. writel(val, &dc->win.prescaled_size);
  57. writel(0, &dc->win.h_initial_dda);
  58. writel(0, &dc->win.v_initial_dda);
  59. h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
  60. v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
  61. val = h_dda << H_DDA_INC_SHIFT;
  62. val |= v_dda << V_DDA_INC_SHIFT;
  63. writel(val, &dc->win.dda_increment);
  64. writel(win->stride, &dc->win.line_stride);
  65. writel(0, &dc->win.buf_stride);
  66. val = WIN_ENABLE;
  67. if (win->bpp < 24)
  68. val |= COLOR_EXPAND;
  69. writel(val, &dc->win.win_opt);
  70. writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
  71. writel(win->x, &dc->winbuf.addr_h_offset);
  72. writel(win->y, &dc->winbuf.addr_v_offset);
  73. writel(0xff00, &dc->win.blend_nokey);
  74. writel(0xff00, &dc->win.blend_1win);
  75. val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  76. val |= GENERAL_UPDATE | WIN_A_UPDATE;
  77. writel(val, &dc->cmd.state_ctrl);
  78. }
  79. static int update_display_mode(struct dc_disp_reg *disp,
  80. struct tegra_lcd_priv *priv)
  81. {
  82. struct display_timing *dt = &priv->timing;
  83. unsigned long val;
  84. unsigned long rate;
  85. unsigned long div;
  86. writel(0x0, &disp->disp_timing_opt);
  87. writel(1 | 1 << 16, &disp->ref_to_sync);
  88. writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
  89. writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
  90. &disp->back_porch);
  91. writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
  92. &disp->front_porch);
  93. writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
  94. val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
  95. val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
  96. writel(val, &disp->data_enable_opt);
  97. val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
  98. val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
  99. val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
  100. writel(val, &disp->disp_interface_ctrl);
  101. /*
  102. * The pixel clock divider is in 7.1 format (where the bottom bit
  103. * represents 0.5). Here we calculate the divider needed to get from
  104. * the display clock (typically 600MHz) to the pixel clock. We round
  105. * up or down as requried.
  106. */
  107. rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
  108. div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
  109. debug("Display clock %lu, divider %lu\n", rate, div);
  110. writel(0x00010001, &disp->shift_clk_opt);
  111. val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
  112. val |= div << SHIFT_CLK_DIVIDER_SHIFT;
  113. writel(val, &disp->disp_clk_ctrl);
  114. return 0;
  115. }
  116. /* Start up the display and turn on power to PWMs */
  117. static void basic_init(struct dc_cmd_reg *cmd)
  118. {
  119. u32 val;
  120. writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
  121. writel(0x0000011a, &cmd->cont_syncpt_vsync);
  122. writel(0x00000000, &cmd->int_type);
  123. writel(0x00000000, &cmd->int_polarity);
  124. writel(0x00000000, &cmd->int_mask);
  125. writel(0x00000000, &cmd->int_enb);
  126. val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
  127. val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
  128. val |= PM1_ENABLE;
  129. writel(val, &cmd->disp_pow_ctrl);
  130. val = readl(&cmd->disp_cmd);
  131. val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
  132. writel(val, &cmd->disp_cmd);
  133. }
  134. static void basic_init_timer(struct dc_disp_reg *disp)
  135. {
  136. writel(0x00000020, &disp->mem_high_pri);
  137. writel(0x00000001, &disp->mem_high_pri_timer);
  138. }
  139. static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
  140. 0x00000000,
  141. 0x00000000,
  142. 0x00000000,
  143. 0x00000000,
  144. };
  145. static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
  146. 0x00000000,
  147. 0x01000000,
  148. 0x00000000,
  149. 0x00000000,
  150. };
  151. static const u32 rgb_data_tab[PIN_REG_COUNT] = {
  152. 0x00000000,
  153. 0x00000000,
  154. 0x00000000,
  155. 0x00000000,
  156. };
  157. static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
  158. 0x00000000,
  159. 0x00000000,
  160. 0x00000000,
  161. 0x00000000,
  162. 0x00210222,
  163. 0x00002200,
  164. 0x00020000,
  165. };
  166. static void rgb_enable(struct dc_com_reg *com)
  167. {
  168. int i;
  169. for (i = 0; i < PIN_REG_COUNT; i++) {
  170. writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
  171. writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
  172. writel(rgb_data_tab[i], &com->pin_output_data[i]);
  173. }
  174. for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
  175. writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
  176. }
  177. static int setup_window(struct disp_ctl_win *win,
  178. struct tegra_lcd_priv *priv)
  179. {
  180. win->x = 0;
  181. win->y = 0;
  182. win->w = priv->width;
  183. win->h = priv->height;
  184. win->out_x = 0;
  185. win->out_y = 0;
  186. win->out_w = priv->width;
  187. win->out_h = priv->height;
  188. win->phys_addr = priv->frame_buffer;
  189. win->stride = priv->width * (1 << priv->log2_bpp) / 8;
  190. debug("%s: depth = %d\n", __func__, priv->log2_bpp);
  191. switch (priv->log2_bpp) {
  192. case VIDEO_BPP32:
  193. win->fmt = COLOR_DEPTH_R8G8B8A8;
  194. win->bpp = 32;
  195. break;
  196. case VIDEO_BPP16:
  197. win->fmt = COLOR_DEPTH_B5G6R5;
  198. win->bpp = 16;
  199. break;
  200. default:
  201. debug("Unsupported LCD bit depth");
  202. return -1;
  203. }
  204. return 0;
  205. }
  206. /**
  207. * Register a new display based on device tree configuration.
  208. *
  209. * The frame buffer can be positioned by U-Boot or overridden by the fdt.
  210. * You should pass in the U-Boot address here, and check the contents of
  211. * struct tegra_lcd_priv to see what was actually chosen.
  212. *
  213. * @param blob Device tree blob
  214. * @param priv Driver's private data
  215. * @param default_lcd_base Default address of LCD frame buffer
  216. * @return 0 if ok, -1 on error (unsupported bits per pixel)
  217. */
  218. static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
  219. void *default_lcd_base)
  220. {
  221. struct disp_ctl_win window;
  222. struct dc_ctlr *dc;
  223. priv->frame_buffer = (u32)default_lcd_base;
  224. dc = (struct dc_ctlr *)priv->disp;
  225. /*
  226. * A header file for clock constants was NAKed upstream.
  227. * TODO: Put this into the FDT and fdt_lcd struct when we have clock
  228. * support there
  229. */
  230. clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
  231. 144 * 1000000);
  232. clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
  233. 600 * 1000000);
  234. basic_init(&dc->cmd);
  235. basic_init_timer(&dc->disp);
  236. rgb_enable(&dc->com);
  237. if (priv->pixel_clock)
  238. update_display_mode(&dc->disp, priv);
  239. if (setup_window(&window, priv))
  240. return -1;
  241. update_window(dc, &window);
  242. return 0;
  243. }
  244. static int tegra_lcd_probe(struct udevice *dev)
  245. {
  246. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  247. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  248. struct tegra_lcd_priv *priv = dev_get_priv(dev);
  249. const void *blob = gd->fdt_blob;
  250. int ret;
  251. /* Initialize the Tegra display controller */
  252. funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
  253. if (tegra_display_probe(blob, priv, (void *)plat->base)) {
  254. printf("%s: Failed to probe display driver\n", __func__);
  255. return -1;
  256. }
  257. pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
  258. pinmux_tristate_disable(PMUX_PINGRP_GPU);
  259. ret = panel_enable_backlight(priv->panel);
  260. if (ret) {
  261. debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
  262. return ret;
  263. }
  264. mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
  265. DCACHE_WRITETHROUGH);
  266. /* Enable flushing after LCD writes if requested */
  267. video_set_flush_dcache(dev, true);
  268. uc_priv->xsize = priv->width;
  269. uc_priv->ysize = priv->height;
  270. uc_priv->bpix = priv->log2_bpp;
  271. debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
  272. plat->size);
  273. return 0;
  274. }
  275. static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
  276. {
  277. struct tegra_lcd_priv *priv = dev_get_priv(dev);
  278. const void *blob = gd->fdt_blob;
  279. struct display_timing *timing;
  280. int node = dev_of_offset(dev);
  281. int panel_node;
  282. int rgb;
  283. int ret;
  284. priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev);
  285. if (!priv->disp) {
  286. debug("%s: No display controller address\n", __func__);
  287. return -EINVAL;
  288. }
  289. rgb = fdt_subnode_offset(blob, node, "rgb");
  290. if (rgb < 0) {
  291. debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
  292. __func__, dev->name, rgb);
  293. return -EINVAL;
  294. }
  295. ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
  296. if (ret) {
  297. debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
  298. __func__, dev->name, ret);
  299. return -EINVAL;
  300. }
  301. timing = &priv->timing;
  302. priv->width = timing->hactive.typ;
  303. priv->height = timing->vactive.typ;
  304. priv->pixel_clock = timing->pixelclock.typ;
  305. priv->log2_bpp = VIDEO_BPP16;
  306. /*
  307. * Sadly the panel phandle is in an rgb subnode so we cannot use
  308. * uclass_get_device_by_phandle().
  309. */
  310. panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
  311. if (panel_node < 0) {
  312. debug("%s: Cannot find panel information\n", __func__);
  313. return -EINVAL;
  314. }
  315. ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
  316. &priv->panel);
  317. if (ret) {
  318. debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
  319. dev->name, ret);
  320. return ret;
  321. }
  322. return 0;
  323. }
  324. static int tegra_lcd_bind(struct udevice *dev)
  325. {
  326. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  327. const void *blob = gd->fdt_blob;
  328. int node = dev_of_offset(dev);
  329. int rgb;
  330. rgb = fdt_subnode_offset(blob, node, "rgb");
  331. if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
  332. return -ENODEV;
  333. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  334. (1 << LCD_MAX_LOG2_BPP) / 8;
  335. return 0;
  336. }
  337. static const struct video_ops tegra_lcd_ops = {
  338. };
  339. static const struct udevice_id tegra_lcd_ids[] = {
  340. { .compatible = "nvidia,tegra20-dc" },
  341. { }
  342. };
  343. U_BOOT_DRIVER(tegra_lcd) = {
  344. .name = "tegra_lcd",
  345. .id = UCLASS_VIDEO,
  346. .of_match = tegra_lcd_ids,
  347. .ops = &tegra_lcd_ops,
  348. .bind = tegra_lcd_bind,
  349. .probe = tegra_lcd_probe,
  350. .ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
  351. .priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),
  352. };