tda19988.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 Liviu Dudau <liviu@dudau.co.uk>
  4. *
  5. * Based on the Linux driver, (C) 2012 Texas Instruments
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <display.h>
  10. #include <i2c.h>
  11. /*
  12. * TDA19988 uses paged registers. We encode the page# in the upper
  13. * bits of the register#. It also means that reads/writes to a register
  14. * have to ensure that the register's page is selected as the current
  15. * page.
  16. */
  17. #define REG(page, addr) (((page) << 8) | (addr))
  18. #define REG2ADDR(reg) ((reg) & 0xff)
  19. #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
  20. /* register for setting current page */
  21. #define REG_CURRENT_PAGE 0xff
  22. /* Page 00h: General Control */
  23. #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
  24. #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
  25. #define MAIN_CNTRL0_SR BIT(0)
  26. #define MAIN_CNTRL0_DECS BIT(1)
  27. #define MAIN_CNTRL0_DEHS BIT(2)
  28. #define MAIN_CNTRL0_CECS BIT(3)
  29. #define MAIN_CNTRL0_CEHS BIT(4)
  30. #define MAIN_CNTRL0_SCALER BIT(7)
  31. #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
  32. #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
  33. #define SOFTRESET_AUDIO BIT(0)
  34. #define SOFTRESET_I2C_MASTER BIT(1)
  35. #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
  36. #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
  37. #define I2C_MASTER_DIS_MM BIT(0)
  38. #define I2C_MASTER_DIS_FILT BIT(1)
  39. #define I2C_MASTER_APP_STRT_LAT BIT(2)
  40. #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
  41. #define FEAT_POWERDOWN_PREFILT BIT(0)
  42. #define FEAT_POWERDOWN_CSC BIT(1)
  43. #define FEAT_POWERDOWN_SPDIF BIT(3)
  44. #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
  45. #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
  46. #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
  47. #define INT_FLAGS_2_EDID_BLK_RD BIT(1)
  48. #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
  49. #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
  50. #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
  51. #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
  52. #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
  53. #define VIP_CNTRL_0_MIRR_A BIT(7)
  54. #define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
  55. #define VIP_CNTRL_0_MIRR_B BIT(3)
  56. #define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
  57. #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
  58. #define VIP_CNTRL_1_MIRR_C BIT(7)
  59. #define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
  60. #define VIP_CNTRL_1_MIRR_D BIT(3)
  61. #define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
  62. #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
  63. #define VIP_CNTRL_2_MIRR_E BIT(7)
  64. #define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
  65. #define VIP_CNTRL_2_MIRR_F BIT(3)
  66. #define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
  67. #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
  68. #define VIP_CNTRL_3_X_TGL BIT(0)
  69. #define VIP_CNTRL_3_H_TGL BIT(1)
  70. #define VIP_CNTRL_3_V_TGL BIT(2)
  71. #define VIP_CNTRL_3_EMB BIT(3)
  72. #define VIP_CNTRL_3_SYNC_DE BIT(4)
  73. #define VIP_CNTRL_3_SYNC_HS BIT(5)
  74. #define VIP_CNTRL_3_DE_INT BIT(6)
  75. #define VIP_CNTRL_3_EDGE BIT(7)
  76. #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
  77. #define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
  78. #define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
  79. #define VIP_CNTRL_4_CCIR656 BIT(4)
  80. #define VIP_CNTRL_4_656_ALT BIT(5)
  81. #define VIP_CNTRL_4_TST_656 BIT(6)
  82. #define VIP_CNTRL_4_TST_PAT BIT(7)
  83. #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
  84. #define VIP_CNTRL_5_CKCASE BIT(0)
  85. #define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
  86. #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
  87. #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
  88. #define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
  89. #define MAT_CONTRL_MAT_BP BIT(2)
  90. #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
  91. #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
  92. #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
  93. #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
  94. #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
  95. #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
  96. #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
  97. #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
  98. #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
  99. #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
  100. #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
  101. #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
  102. #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
  103. #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
  104. #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
  105. #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
  106. #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
  107. #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
  108. #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
  109. #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
  110. #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
  111. #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
  112. #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
  113. #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
  114. #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
  115. #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
  116. #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
  117. #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
  118. #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
  119. #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
  120. #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
  121. #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
  122. #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
  123. #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
  124. #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
  125. #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
  126. #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
  127. #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
  128. #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
  129. #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
  130. #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
  131. #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
  132. #define TBG_CNTRL_0_TOP_TGL BIT(0)
  133. #define TBG_CNTRL_0_TOP_SEL BIT(1)
  134. #define TBG_CNTRL_0_DE_EXT BIT(2)
  135. #define TBG_CNTRL_0_TOP_EXT BIT(3)
  136. #define TBG_CNTRL_0_FRAME_DIS BIT(5)
  137. #define TBG_CNTRL_0_SYNC_MTHD BIT(6)
  138. #define TBG_CNTRL_0_SYNC_ONCE BIT(7)
  139. #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
  140. #define TBG_CNTRL_1_H_TGL BIT(0)
  141. #define TBG_CNTRL_1_V_TGL BIT(1)
  142. #define TBG_CNTRL_1_TGL_EN BIT(2)
  143. #define TBG_CNTRL_1_X_EXT BIT(3)
  144. #define TBG_CNTRL_1_H_EXT BIT(4)
  145. #define TBG_CNTRL_1_V_EXT BIT(5)
  146. #define TBG_CNTRL_1_DWIN_DIS BIT(6)
  147. #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
  148. #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
  149. #define HVF_CNTRL_0_SM BIT(7)
  150. #define HVF_CNTRL_0_RWB BIT(6)
  151. #define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
  152. #define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
  153. #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
  154. #define HVF_CNTRL_1_FOR BIT(0)
  155. #define HVF_CNTRL_1_YUVBLK BIT(1)
  156. #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
  157. #define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
  158. #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
  159. #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
  160. #define AIP_CLKSEL_AIP_SPDIF (0 << 3)
  161. #define AIP_CLKSEL_AIP_I2S BIT(3)
  162. #define AIP_CLKSEL_FS_ACLK (0 << 0)
  163. #define AIP_CLKSEL_FS_MCLK BIT(0)
  164. /* Page 02h: PLL settings */
  165. #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
  166. #define PLL_SERIAL_1_SRL_FDN BIT(0)
  167. #define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
  168. #define PLL_SERIAL_1_SRL_MAN_IZ BIT(6)
  169. #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
  170. #define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
  171. #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
  172. #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
  173. #define PLL_SERIAL_3_SRL_CCIR BIT(0)
  174. #define PLL_SERIAL_3_SRL_DE BIT(2)
  175. #define PLL_SERIAL_3_SRL_PXIN_SEL BIT(4)
  176. #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
  177. #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
  178. #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
  179. #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
  180. #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
  181. #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
  182. #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
  183. #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
  184. #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
  185. #define AUDIO_DIV_SERCLK_1 0
  186. #define AUDIO_DIV_SERCLK_2 1
  187. #define AUDIO_DIV_SERCLK_4 2
  188. #define AUDIO_DIV_SERCLK_8 3
  189. #define AUDIO_DIV_SERCLK_16 4
  190. #define AUDIO_DIV_SERCLK_32 5
  191. #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
  192. #define SEL_CLK_SEL_CLK1 BIT(0)
  193. #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
  194. #define SEL_CLK_ENA_SC_CLK BIT(3)
  195. #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
  196. /* Page 09h: EDID Control */
  197. #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
  198. /* next 127 successive registers are the EDID block */
  199. #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
  200. #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
  201. #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
  202. #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
  203. #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
  204. /* Page 11h: audio settings and content info packets */
  205. #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
  206. #define AIP_CNTRL_0_RST_FIFO BIT(0)
  207. #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
  208. #define ENC_CNTRL_RST_ENC BIT(0)
  209. #define ENC_CNTRL_RST_SEL BIT(1)
  210. #define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
  211. /* Page 12h: HDCP and OTP */
  212. #define REG_TX3 REG(0x12, 0x9a) /* read/write */
  213. #define REG_TX4 REG(0x12, 0x9b) /* read/write */
  214. #define TX4_PD_RAM BIT(1)
  215. #define REG_TX33 REG(0x12, 0xb8) /* read/write */
  216. #define TX33_HDMI BIT(1)
  217. /* CEC registers, not paged */
  218. #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
  219. #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS BIT(7)
  220. #define CEC_FRO_IM_CLK_CTRL_ENA_OTP BIT(6)
  221. #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL BIT(1)
  222. #define CEC_FRO_IM_CLK_CTRL_FRO_DIV BIT(0)
  223. #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
  224. #define REG_CEC_RXSHPDINT 0xfd /* read */
  225. #define CEC_RXSHPDINT_RXSENS BIT(0)
  226. #define CEC_RXSHPDINT_HPD BIT(1)
  227. #define TDA19988_CEC_ENAMODS 0xff /* read/write */
  228. #define CEC_ENAMODS_EN_RXSENS BIT(2)
  229. #define CEC_ENAMODS_EN_HDMI BIT(1)
  230. #define CEC_ENAMODS_EN_CEC BIT(0)
  231. /* Device versions */
  232. #define TDA9989N2 0x0101
  233. #define TDA19989 0x0201
  234. #define TDA19989N2 0x0202
  235. #define TDA19988 0x0301
  236. struct tda19988_priv {
  237. struct udevice *chip;
  238. struct udevice *cec_chip;
  239. u16 revision;
  240. u8 current_page;
  241. };
  242. static void tda19988_register_set(struct tda19988_priv *priv, u16 reg, u8 val)
  243. {
  244. u8 old_val, page = REG2PAGE(reg);
  245. if (priv->current_page != page) {
  246. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  247. priv->current_page = page;
  248. }
  249. old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
  250. old_val |= val;
  251. dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
  252. }
  253. static void tda19988_register_clear(struct tda19988_priv *priv, u16 reg, u8 val)
  254. {
  255. u8 old_val, page = REG2PAGE(reg);
  256. if (priv->current_page != page) {
  257. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  258. priv->current_page = page;
  259. }
  260. old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
  261. old_val &= ~val;
  262. dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
  263. }
  264. static void tda19988_register_write(struct tda19988_priv *priv, u16 reg, u8 val)
  265. {
  266. u8 page = REG2PAGE(reg);
  267. if (priv->current_page != page) {
  268. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  269. priv->current_page = page;
  270. }
  271. dm_i2c_reg_write(priv->chip, REG2ADDR(reg), val);
  272. }
  273. static int tda19988_register_read(struct tda19988_priv *priv, u16 reg)
  274. {
  275. u8 page = REG2PAGE(reg);
  276. if (priv->current_page != page) {
  277. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  278. priv->current_page = page;
  279. }
  280. return dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
  281. }
  282. static void tda19988_register_write16(struct tda19988_priv *priv,
  283. u16 reg, u16 val)
  284. {
  285. u8 buf[] = { val >> 8, val }, page = REG2PAGE(reg);
  286. if (priv->current_page != page) {
  287. dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
  288. priv->current_page = page;
  289. }
  290. dm_i2c_write(priv->chip, REG2ADDR(reg), buf, 2);
  291. }
  292. static int tda19988_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  293. {
  294. struct tda19988_priv *priv = dev_get_priv(dev);
  295. int i, val = 0, offset = 0;
  296. /*
  297. * The TDA998x has a problem when trying to read the EDID close to a
  298. * HPD assertion: it needs a delay of 100ms to avoid timing out while
  299. * trying to read EDID data.
  300. */
  301. mdelay(120);
  302. if (priv->revision == TDA19988)
  303. tda19988_register_clear(priv, REG_TX4, TX4_PD_RAM);
  304. while (offset < buf_size) {
  305. tda19988_register_write(priv, REG_DDC_ADDR, 0xa0);
  306. tda19988_register_write(priv, REG_DDC_OFFS, offset);
  307. tda19988_register_write(priv, REG_DDC_SEGM_ADDR, 0x60);
  308. tda19988_register_write(priv, REG_DDC_SEGM, 0);
  309. /* enable reading EDID */
  310. tda19988_register_write(priv, REG_EDID_CTRL, 1);
  311. /* flags must be cleared by software */
  312. tda19988_register_write(priv, REG_EDID_CTRL, 0);
  313. /* wait for block read to complete */
  314. for (i = 300; i > 0; i--) {
  315. mdelay(1);
  316. val = tda19988_register_read(priv, REG_INT_FLAGS_2);
  317. if (val < 0)
  318. return val;
  319. if (val & INT_FLAGS_2_EDID_BLK_RD)
  320. break;
  321. }
  322. if (i == 0)
  323. return -ETIMEDOUT;
  324. priv->current_page = REG2PAGE(REG_EDID_DATA_0);
  325. dm_i2c_reg_write(priv->chip,
  326. REG_CURRENT_PAGE, REG2PAGE(REG_EDID_DATA_0));
  327. val = dm_i2c_read(priv->chip,
  328. REG2ADDR(REG_EDID_DATA_0), buf + offset, 128);
  329. offset += 128;
  330. }
  331. if (priv->revision == TDA19988)
  332. tda19988_register_set(priv, REG_TX4, TX4_PD_RAM);
  333. return offset;
  334. }
  335. static int tda19988_enable(struct udevice *dev, int panel_bpp,
  336. const struct display_timing *timing)
  337. {
  338. struct tda19988_priv *priv = dev_get_priv(dev);
  339. u8 div = 148500000 / timing->pixelclock.typ, reg;
  340. u16 line_clocks, lines;
  341. if (dev != 0) {
  342. div--;
  343. if (div > 3)
  344. div = 3;
  345. }
  346. /* first disable the video ports */
  347. tda19988_register_write(priv, REG_ENA_VP_0, 0);
  348. tda19988_register_write(priv, REG_ENA_VP_1, 0);
  349. tda19988_register_write(priv, REG_ENA_VP_2, 0);
  350. /* shutdown audio */
  351. tda19988_register_write(priv, REG_ENA_AP, 0);
  352. line_clocks = timing->hsync_len.typ + timing->hback_porch.typ +
  353. timing->hactive.typ + timing->hfront_porch.typ;
  354. lines = timing->vsync_len.typ + timing->vback_porch.typ +
  355. timing->vactive.typ + timing->vfront_porch.typ;
  356. /* mute the audio FIFO */
  357. tda19988_register_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
  358. /* HDMI HDCP: off */
  359. tda19988_register_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
  360. tda19988_register_clear(priv, REG_TX33, TX33_HDMI);
  361. tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
  362. /* no pre-filter or interpolator */
  363. tda19988_register_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
  364. HVF_CNTRL_0_INTPOL(0));
  365. tda19988_register_set(priv, REG_FEAT_POWERDOWN,
  366. FEAT_POWERDOWN_PREFILT);
  367. tda19988_register_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
  368. tda19988_register_write(priv, REG_VIP_CNTRL_4,
  369. VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0) |
  370. VIP_CNTRL_4_TST_PAT);
  371. tda19988_register_clear(priv, REG_PLL_SERIAL_1,
  372. PLL_SERIAL_1_SRL_MAN_IZ);
  373. tda19988_register_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
  374. PLL_SERIAL_3_SRL_DE);
  375. tda19988_register_write(priv, REG_SERIALIZER, 0);
  376. tda19988_register_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
  377. tda19988_register_write(priv, REG_RPT_CNTRL, 0);
  378. tda19988_register_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
  379. SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
  380. tda19988_register_write(priv, REG_PLL_SERIAL_2,
  381. PLL_SERIAL_2_SRL_NOSC(div) |
  382. PLL_SERIAL_2_SRL_PR(0));
  383. /* set color matrix bypass flag: */
  384. tda19988_register_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
  385. MAT_CONTRL_MAT_SC(1));
  386. tda19988_register_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
  387. /* set BIAS tmds value: */
  388. tda19988_register_write(priv, REG_ANA_GENERAL, 0x09);
  389. /*
  390. * Sync on rising HSYNC/VSYNC
  391. */
  392. reg = VIP_CNTRL_3_SYNC_HS;
  393. /*
  394. * TDA19988 requires high-active sync at input stage,
  395. * so invert low-active sync provided by master encoder here
  396. */
  397. if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
  398. reg |= VIP_CNTRL_3_H_TGL;
  399. if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
  400. reg |= VIP_CNTRL_3_V_TGL;
  401. tda19988_register_write(priv, REG_VIP_CNTRL_3, reg);
  402. tda19988_register_write(priv, REG_VIDFORMAT, 0x00);
  403. tda19988_register_write16(priv, REG_REFPIX_MSB,
  404. timing->hfront_porch.typ + 3);
  405. tda19988_register_write16(priv, REG_REFLINE_MSB,
  406. timing->vfront_porch.typ + 1);
  407. tda19988_register_write16(priv, REG_NPIX_MSB, line_clocks);
  408. tda19988_register_write16(priv, REG_NLINE_MSB, lines);
  409. tda19988_register_write16(priv, REG_VS_LINE_STRT_1_MSB,
  410. timing->vfront_porch.typ);
  411. tda19988_register_write16(priv, REG_VS_PIX_STRT_1_MSB,
  412. timing->hfront_porch.typ);
  413. tda19988_register_write16(priv, REG_VS_LINE_END_1_MSB,
  414. timing->vfront_porch.typ +
  415. timing->vsync_len.typ);
  416. tda19988_register_write16(priv, REG_VS_PIX_END_1_MSB,
  417. timing->hfront_porch.typ);
  418. tda19988_register_write16(priv, REG_VS_LINE_STRT_2_MSB, 0);
  419. tda19988_register_write16(priv, REG_VS_PIX_STRT_2_MSB, 0);
  420. tda19988_register_write16(priv, REG_VS_LINE_END_2_MSB, 0);
  421. tda19988_register_write16(priv, REG_VS_PIX_END_2_MSB, 0);
  422. tda19988_register_write16(priv, REG_HS_PIX_START_MSB,
  423. timing->hfront_porch.typ);
  424. tda19988_register_write16(priv, REG_HS_PIX_STOP_MSB,
  425. timing->hfront_porch.typ +
  426. timing->hsync_len.typ);
  427. tda19988_register_write16(priv, REG_VWIN_START_1_MSB,
  428. lines - timing->vactive.typ - 1);
  429. tda19988_register_write16(priv, REG_VWIN_END_1_MSB, lines - 1);
  430. tda19988_register_write16(priv, REG_VWIN_START_2_MSB, 0);
  431. tda19988_register_write16(priv, REG_VWIN_END_2_MSB, 0);
  432. tda19988_register_write16(priv, REG_DE_START_MSB,
  433. line_clocks - timing->hactive.typ);
  434. tda19988_register_write16(priv, REG_DE_STOP_MSB, line_clocks);
  435. if (priv->revision == TDA19988) {
  436. /* let incoming pixels fill the active space (if any) */
  437. tda19988_register_write(priv, REG_ENABLE_SPACE, 0x00);
  438. }
  439. /*
  440. * Always generate sync polarity relative to input sync and
  441. * revert input stage toggled sync at output stage
  442. */
  443. reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
  444. if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
  445. reg |= TBG_CNTRL_1_H_TGL;
  446. if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
  447. reg |= TBG_CNTRL_1_V_TGL;
  448. tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
  449. /* must be last register set: */
  450. tda19988_register_write(priv, REG_TBG_CNTRL_0, 0);
  451. /* turn on HDMI HDCP */
  452. reg &= ~TBG_CNTRL_1_DWIN_DIS;
  453. tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
  454. tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
  455. tda19988_register_set(priv, REG_TX33, TX33_HDMI);
  456. mdelay(400);
  457. /* enable video ports */
  458. tda19988_register_write(priv, REG_ENA_VP_0, 0xff);
  459. tda19988_register_write(priv, REG_ENA_VP_1, 0xff);
  460. tda19988_register_write(priv, REG_ENA_VP_2, 0xff);
  461. /* set muxing after enabling ports: */
  462. tda19988_register_write(priv, REG_VIP_CNTRL_0,
  463. VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3));
  464. tda19988_register_write(priv, REG_VIP_CNTRL_1,
  465. VIP_CNTRL_1_SWAP_C(4) | VIP_CNTRL_1_SWAP_D(5));
  466. tda19988_register_write(priv, REG_VIP_CNTRL_2,
  467. VIP_CNTRL_2_SWAP_E(0) | VIP_CNTRL_2_SWAP_F(1));
  468. return 0;
  469. }
  470. struct dm_display_ops tda19988_ops = {
  471. .read_edid = tda19988_read_edid,
  472. .enable = tda19988_enable,
  473. };
  474. static const struct udevice_id tda19988_ids[] = {
  475. { .compatible = "nxp,tda998x" },
  476. { }
  477. };
  478. static int tda19988_probe(struct udevice *dev)
  479. {
  480. u8 cec_addr, chip_addr, rev_lo, rev_hi;
  481. int err;
  482. struct tda19988_priv *priv = dev_get_priv(dev);
  483. chip_addr = dev_read_addr(dev);
  484. /* CEC I2C address is using TDA19988 I2C address configuration pins */
  485. cec_addr = 0x34 + (chip_addr & 0x03);
  486. err = i2c_get_chip_for_busnum(0, cec_addr, 1, &priv->cec_chip);
  487. if (err) {
  488. printf("cec i2c_get_chip_for_busnum returned %d\n", err);
  489. return err;
  490. }
  491. err = i2c_get_chip_for_busnum(0, chip_addr, 1, &priv->chip);
  492. if (err) {
  493. printf("i2c_get_chip_for_busnum returned %d\n", err);
  494. return err;
  495. }
  496. priv->current_page = 0xff;
  497. /* wake up device */
  498. dm_i2c_reg_write(priv->cec_chip, TDA19988_CEC_ENAMODS,
  499. CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
  500. /* reset audio and I2C master */
  501. tda19988_register_write(priv, REG_SOFTRESET,
  502. SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
  503. mdelay(50);
  504. tda19988_register_write(priv, REG_SOFTRESET, 0);
  505. mdelay(50);
  506. /* reset transmitter */
  507. tda19988_register_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
  508. tda19988_register_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
  509. /* PLL registers common configuration */
  510. tda19988_register_write(priv, REG_PLL_SERIAL_1, 0x00);
  511. tda19988_register_write(priv, REG_PLL_SERIAL_2,
  512. PLL_SERIAL_2_SRL_NOSC(1));
  513. tda19988_register_write(priv, REG_PLL_SERIAL_3, 0x00);
  514. tda19988_register_write(priv, REG_SERIALIZER, 0x00);
  515. tda19988_register_write(priv, REG_BUFFER_OUT, 0x00);
  516. tda19988_register_write(priv, REG_PLL_SCG1, 0x00);
  517. tda19988_register_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
  518. tda19988_register_write(priv, REG_SEL_CLK,
  519. SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
  520. tda19988_register_write(priv, REG_PLL_SCGN1, 0xfa);
  521. tda19988_register_write(priv, REG_PLL_SCGN2, 0x00);
  522. tda19988_register_write(priv, REG_PLL_SCGR1, 0x5b);
  523. tda19988_register_write(priv, REG_PLL_SCGR2, 0x00);
  524. tda19988_register_write(priv, REG_PLL_SCG2, 0x10);
  525. /* Write the default value MUX register */
  526. tda19988_register_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
  527. /* read version */
  528. rev_lo = dm_i2c_reg_read(priv->chip, REG_VERSION_LSB);
  529. rev_hi = dm_i2c_reg_read(priv->chip, REG_VERSION_MSB);
  530. /* mask off feature bits */
  531. priv->revision = ((rev_hi << 8) | rev_lo) & ~0x30;
  532. printf("HDMI: ");
  533. switch (priv->revision) {
  534. case TDA9989N2:
  535. printf("TDA9989 n2\n");
  536. break;
  537. case TDA19989:
  538. printf("TDA19989\n");
  539. break;
  540. case TDA19989N2:
  541. printf("TDA19989 n2\n");
  542. break;
  543. case TDA19988:
  544. printf("TDA19988\n");
  545. break;
  546. default:
  547. printf("unknown TDA device: 0x%04x\n", priv->revision);
  548. return -ENXIO;
  549. }
  550. /* after reset, enable DDC */
  551. tda19988_register_write(priv, REG_DDC_DISABLE, 0x00);
  552. /* set clock on DDC channel */
  553. tda19988_register_write(priv, REG_TX3, 39);
  554. /* if necessary, disable multi-master */
  555. if (priv->revision == TDA19989)
  556. tda19988_register_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
  557. dm_i2c_reg_write(priv->cec_chip, REG_CEC_FRO_IM_CLK_CTRL,
  558. CEC_FRO_IM_CLK_CTRL_GHOST_DIS |
  559. CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
  560. /* ensure interrupts are disabled */
  561. dm_i2c_reg_write(priv->cec_chip, REG_CEC_RXSHPDINTENA, 0);
  562. /* clear pending interrupts */
  563. dm_i2c_reg_read(priv->cec_chip, REG_CEC_RXSHPDINT);
  564. tda19988_register_read(priv, REG_INT_FLAGS_0);
  565. tda19988_register_read(priv, REG_INT_FLAGS_1);
  566. tda19988_register_read(priv, REG_INT_FLAGS_2);
  567. /* enable EDID read irq */
  568. tda19988_register_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
  569. return 0;
  570. }
  571. U_BOOT_DRIVER(tda19988) = {
  572. .name = "tda19988",
  573. .id = UCLASS_DISPLAY,
  574. .of_match = tda19988_ids,
  575. .ops = &tda19988_ops,
  576. .probe = tda19988_probe,
  577. .priv_auto_alloc_size = sizeof(struct tda19988_priv),
  578. };