ssd2828.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
  4. */
  5. /*
  6. * Support for the SSD2828 bridge chip, which can take pixel data coming
  7. * from a parallel LCD interface and translate it on the flight into MIPI DSI
  8. * interface for driving a MIPI compatible TFT display.
  9. */
  10. #include <common.h>
  11. #include <malloc.h>
  12. #include <mipi_display.h>
  13. #include <asm/arch/gpio.h>
  14. #include <asm/gpio.h>
  15. #include "videomodes.h"
  16. #include "ssd2828.h"
  17. #define SSD2828_DIR 0xB0
  18. #define SSD2828_VICR1 0xB1
  19. #define SSD2828_VICR2 0xB2
  20. #define SSD2828_VICR3 0xB3
  21. #define SSD2828_VICR4 0xB4
  22. #define SSD2828_VICR5 0xB5
  23. #define SSD2828_VICR6 0xB6
  24. #define SSD2828_CFGR 0xB7
  25. #define SSD2828_VCR 0xB8
  26. #define SSD2828_PCR 0xB9
  27. #define SSD2828_PLCR 0xBA
  28. #define SSD2828_CCR 0xBB
  29. #define SSD2828_PSCR1 0xBC
  30. #define SSD2828_PSCR2 0xBD
  31. #define SSD2828_PSCR3 0xBE
  32. #define SSD2828_PDR 0xBF
  33. #define SSD2828_OCR 0xC0
  34. #define SSD2828_MRSR 0xC1
  35. #define SSD2828_RDCR 0xC2
  36. #define SSD2828_ARSR 0xC3
  37. #define SSD2828_LCR 0xC4
  38. #define SSD2828_ICR 0xC5
  39. #define SSD2828_ISR 0xC6
  40. #define SSD2828_ESR 0xC7
  41. #define SSD2828_DAR1 0xC9
  42. #define SSD2828_DAR2 0xCA
  43. #define SSD2828_DAR3 0xCB
  44. #define SSD2828_DAR4 0xCC
  45. #define SSD2828_DAR5 0xCD
  46. #define SSD2828_DAR6 0xCE
  47. #define SSD2828_HTTR1 0xCF
  48. #define SSD2828_HTTR2 0xD0
  49. #define SSD2828_LRTR1 0xD1
  50. #define SSD2828_LRTR2 0xD2
  51. #define SSD2828_TSR 0xD3
  52. #define SSD2828_LRR 0xD4
  53. #define SSD2828_PLLR 0xD5
  54. #define SSD2828_TR 0xD6
  55. #define SSD2828_TECR 0xD7
  56. #define SSD2828_ACR1 0xD8
  57. #define SSD2828_ACR2 0xD9
  58. #define SSD2828_ACR3 0xDA
  59. #define SSD2828_ACR4 0xDB
  60. #define SSD2828_IOCR 0xDC
  61. #define SSD2828_VICR7 0xDD
  62. #define SSD2828_LCFR 0xDE
  63. #define SSD2828_DAR7 0xDF
  64. #define SSD2828_PUCR1 0xE0
  65. #define SSD2828_PUCR2 0xE1
  66. #define SSD2828_PUCR3 0xE2
  67. #define SSD2828_CBCR1 0xE9
  68. #define SSD2828_CBCR2 0xEA
  69. #define SSD2828_CBSR 0xEB
  70. #define SSD2828_ECR 0xEC
  71. #define SSD2828_VSDR 0xED
  72. #define SSD2828_TMR 0xEE
  73. #define SSD2828_GPIO1 0xEF
  74. #define SSD2828_GPIO2 0xF0
  75. #define SSD2828_DLYA01 0xF1
  76. #define SSD2828_DLYA23 0xF2
  77. #define SSD2828_DLYB01 0xF3
  78. #define SSD2828_DLYB23 0xF4
  79. #define SSD2828_DLYC01 0xF5
  80. #define SSD2828_DLYC23 0xF6
  81. #define SSD2828_ACR5 0xF7
  82. #define SSD2828_RR 0xFF
  83. #define SSD2828_CFGR_HS (1 << 0)
  84. #define SSD2828_CFGR_CKE (1 << 1)
  85. #define SSD2828_CFGR_SLP (1 << 2)
  86. #define SSD2828_CFGR_VEN (1 << 3)
  87. #define SSD2828_CFGR_HCLK (1 << 4)
  88. #define SSD2828_CFGR_CSS (1 << 5)
  89. #define SSD2828_CFGR_DCS (1 << 6)
  90. #define SSD2828_CFGR_REN (1 << 7)
  91. #define SSD2828_CFGR_ECD (1 << 8)
  92. #define SSD2828_CFGR_EOT (1 << 9)
  93. #define SSD2828_CFGR_LPE (1 << 10)
  94. #define SSD2828_CFGR_TXD (1 << 11)
  95. #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2)
  96. #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2)
  97. #define SSD2828_VIDEO_MODE_BURST (2 << 2)
  98. #define SSD2828_VIDEO_PIXEL_FORMAT_16BPP 0
  99. #define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED 1
  100. #define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED 2
  101. #define SSD2828_VIDEO_PIXEL_FORMAT_24BPP 3
  102. #define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F)
  103. /*
  104. * SPI transfer, using the "24-bit 3 wire" mode (that's how it is called in
  105. * the SSD2828 documentation). The 'dout' input parameter specifies 24-bits
  106. * of data to be written to SSD2828. Returns the lowest 16-bits of data,
  107. * that is received back.
  108. */
  109. static u32 soft_spi_xfer_24bit_3wire(const struct ssd2828_config *drv, u32 dout)
  110. {
  111. int j, bitlen = 24;
  112. u32 tmpdin = 0;
  113. /*
  114. * According to the "24 Bit 3 Wire SPI Interface Timing Characteristics"
  115. * and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet,
  116. * the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs
  117. * at 1/8 of that after reset. So using 1 microsecond delays is safe in
  118. * the main loop. But the delays around chip select pin manipulations
  119. * need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in
  120. * the worst case).
  121. */
  122. const int spi_delay_us = 1;
  123. const int spi_cs_delay_us = 2;
  124. gpio_set_value(drv->csx_pin, 0);
  125. udelay(spi_cs_delay_us);
  126. for (j = bitlen - 1; j >= 0; j--) {
  127. gpio_set_value(drv->sck_pin, 0);
  128. gpio_set_value(drv->sdi_pin, (dout & (1 << j)) != 0);
  129. udelay(spi_delay_us);
  130. if (drv->sdo_pin != -1)
  131. tmpdin = (tmpdin << 1) | gpio_get_value(drv->sdo_pin);
  132. gpio_set_value(drv->sck_pin, 1);
  133. udelay(spi_delay_us);
  134. }
  135. udelay(spi_cs_delay_us);
  136. gpio_set_value(drv->csx_pin, 1);
  137. udelay(spi_cs_delay_us);
  138. return tmpdin & 0xFFFF;
  139. }
  140. /*
  141. * Read from a SSD2828 hardware register (regnum >= 0xB0)
  142. */
  143. static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum)
  144. {
  145. soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
  146. return soft_spi_xfer_24bit_3wire(cfg, 0x730000);
  147. }
  148. /*
  149. * Write to a SSD2828 hardware register (regnum >= 0xB0)
  150. */
  151. static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum,
  152. u16 val)
  153. {
  154. soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
  155. soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val);
  156. }
  157. /*
  158. * Send MIPI command to the LCD panel (cmdnum < 0xB0)
  159. */
  160. static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum)
  161. {
  162. /* Set packet size to 1 (a single command with no parameters) */
  163. write_hw_register(cfg, SSD2828_PSCR1, 1);
  164. /* Send the command */
  165. write_hw_register(cfg, SSD2828_PDR, cmdnum);
  166. }
  167. /*
  168. * Reset SSD2828
  169. */
  170. static void ssd2828_reset(const struct ssd2828_config *cfg)
  171. {
  172. /* RESET needs 10 milliseconds according to the datasheet */
  173. gpio_set_value(cfg->reset_pin, 0);
  174. mdelay(10);
  175. gpio_set_value(cfg->reset_pin, 1);
  176. mdelay(10);
  177. }
  178. static int ssd2828_enable_gpio(const struct ssd2828_config *cfg)
  179. {
  180. if (gpio_request(cfg->csx_pin, "ssd2828_csx")) {
  181. printf("SSD2828: request for 'ssd2828_csx' pin failed\n");
  182. return 1;
  183. }
  184. if (gpio_request(cfg->sck_pin, "ssd2828_sck")) {
  185. gpio_free(cfg->csx_pin);
  186. printf("SSD2828: request for 'ssd2828_sck' pin failed\n");
  187. return 1;
  188. }
  189. if (gpio_request(cfg->sdi_pin, "ssd2828_sdi")) {
  190. gpio_free(cfg->csx_pin);
  191. gpio_free(cfg->sck_pin);
  192. printf("SSD2828: request for 'ssd2828_sdi' pin failed\n");
  193. return 1;
  194. }
  195. if (gpio_request(cfg->reset_pin, "ssd2828_reset")) {
  196. gpio_free(cfg->csx_pin);
  197. gpio_free(cfg->sck_pin);
  198. gpio_free(cfg->sdi_pin);
  199. printf("SSD2828: request for 'ssd2828_reset' pin failed\n");
  200. return 1;
  201. }
  202. if (cfg->sdo_pin != -1 && gpio_request(cfg->sdo_pin, "ssd2828_sdo")) {
  203. gpio_free(cfg->csx_pin);
  204. gpio_free(cfg->sck_pin);
  205. gpio_free(cfg->sdi_pin);
  206. gpio_free(cfg->reset_pin);
  207. printf("SSD2828: request for 'ssd2828_sdo' pin failed\n");
  208. return 1;
  209. }
  210. gpio_direction_output(cfg->reset_pin, 0);
  211. gpio_direction_output(cfg->csx_pin, 1);
  212. gpio_direction_output(cfg->sck_pin, 1);
  213. gpio_direction_output(cfg->sdi_pin, 1);
  214. if (cfg->sdo_pin != -1)
  215. gpio_direction_input(cfg->sdo_pin);
  216. return 0;
  217. }
  218. static int ssd2828_free_gpio(const struct ssd2828_config *cfg)
  219. {
  220. gpio_free(cfg->csx_pin);
  221. gpio_free(cfg->sck_pin);
  222. gpio_free(cfg->sdi_pin);
  223. gpio_free(cfg->reset_pin);
  224. if (cfg->sdo_pin != -1)
  225. gpio_free(cfg->sdo_pin);
  226. return 1;
  227. }
  228. /*
  229. * PLL configuration register settings.
  230. *
  231. * See the "PLL Configuration Register Description" in the SSD2828 datasheet.
  232. */
  233. static u32 construct_pll_config(u32 desired_pll_freq_kbps,
  234. u32 reference_freq_khz)
  235. {
  236. u32 div_factor = 1, mul_factor, fr = 0;
  237. u32 output_freq_kbps;
  238. /* The intermediate clock after division can't be less than 5MHz */
  239. while (reference_freq_khz / (div_factor + 1) >= 5000)
  240. div_factor++;
  241. if (div_factor > 31)
  242. div_factor = 31;
  243. mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
  244. reference_freq_khz);
  245. output_freq_kbps = reference_freq_khz * mul_factor / div_factor;
  246. if (output_freq_kbps >= 501000)
  247. fr = 3;
  248. else if (output_freq_kbps >= 251000)
  249. fr = 2;
  250. else if (output_freq_kbps >= 126000)
  251. fr = 1;
  252. return (fr << 14) | (div_factor << 8) | mul_factor;
  253. }
  254. static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz)
  255. {
  256. u32 mul_factor = pll_config & 0xFF;
  257. u32 div_factor = (pll_config >> 8) & 0x1F;
  258. if (mul_factor == 0)
  259. mul_factor = 1;
  260. if (div_factor == 0)
  261. div_factor = 1;
  262. return reference_freq_khz * mul_factor / div_factor;
  263. }
  264. static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg,
  265. const struct ctfb_res_modes *mode)
  266. {
  267. u32 val;
  268. /* RGB Interface Control Register 1 */
  269. write_hw_register(cfg, SSD2828_VICR1, (mode->vsync_len << 8) |
  270. (mode->hsync_len));
  271. /* RGB Interface Control Register 2 */
  272. u32 vbp = mode->vsync_len + mode->upper_margin;
  273. u32 hbp = mode->hsync_len + mode->left_margin;
  274. write_hw_register(cfg, SSD2828_VICR2, (vbp << 8) | hbp);
  275. /* RGB Interface Control Register 3 */
  276. write_hw_register(cfg, SSD2828_VICR3, (mode->lower_margin << 8) |
  277. (mode->right_margin));
  278. /* RGB Interface Control Register 4 */
  279. write_hw_register(cfg, SSD2828_VICR4, mode->xres);
  280. /* RGB Interface Control Register 5 */
  281. write_hw_register(cfg, SSD2828_VICR5, mode->yres);
  282. /* RGB Interface Control Register 6 */
  283. val = SSD2828_VIDEO_MODE_BURST;
  284. switch (cfg->ssd2828_color_depth) {
  285. case 16:
  286. val |= SSD2828_VIDEO_PIXEL_FORMAT_16BPP;
  287. break;
  288. case 18:
  289. val |= cfg->mipi_dsi_loosely_packed_pixel_format ?
  290. SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED :
  291. SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED;
  292. break;
  293. case 24:
  294. val |= SSD2828_VIDEO_PIXEL_FORMAT_24BPP;
  295. break;
  296. default:
  297. printf("SSD2828: unsupported color depth\n");
  298. return 1;
  299. }
  300. write_hw_register(cfg, SSD2828_VICR6, val);
  301. /* Lane Configuration Register */
  302. write_hw_register(cfg, SSD2828_LCFR,
  303. cfg->mipi_dsi_number_of_data_lanes - 1);
  304. return 0;
  305. }
  306. int ssd2828_init(const struct ssd2828_config *cfg,
  307. const struct ctfb_res_modes *mode)
  308. {
  309. u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config;
  310. /* The LP clock speed is limited by 10MHz */
  311. const u32 mipi_dsi_low_power_clk_khz = 10000;
  312. /*
  313. * This is just the reset default value of CFGR register (0x301).
  314. * Because we are not always able to read back from SPI, have
  315. * it initialized here.
  316. */
  317. u32 cfgr_reg = SSD2828_CFGR_EOT | /* EOT Packet Enable */
  318. SSD2828_CFGR_ECD | /* Disable ECC and CRC */
  319. SSD2828_CFGR_HS; /* Data lanes are in HS mode */
  320. /* Initialize the pins */
  321. if (ssd2828_enable_gpio(cfg) != 0)
  322. return 1;
  323. /* Reset the chip */
  324. ssd2828_reset(cfg);
  325. /*
  326. * If there is a pin to read data back from SPI, then we are lucky. Try
  327. * to check if SPI is configured correctly and SSD2828 is actually able
  328. * to talk back.
  329. */
  330. if (cfg->sdo_pin != -1) {
  331. if (read_hw_register(cfg, SSD2828_DIR) != 0x2828 ||
  332. read_hw_register(cfg, SSD2828_CFGR) != cfgr_reg) {
  333. printf("SSD2828: SPI communication failed.\n");
  334. ssd2828_free_gpio(cfg);
  335. return 1;
  336. }
  337. }
  338. /*
  339. * Pick the reference clock for PLL. If we know the exact 'tx_clk'
  340. * clock speed, then everything is good. If not, then we can fallback
  341. * to 'pclk' (pixel clock from the parallel LCD interface). In the
  342. * case of using this fallback, it is necessary to have parallel LCD
  343. * already initialized and running at this point.
  344. */
  345. reference_freq_khz = cfg->ssd2828_tx_clk_khz;
  346. if (reference_freq_khz == 0) {
  347. reference_freq_khz = mode->pixclock_khz;
  348. /* Use 'pclk' as the reference clock for PLL */
  349. cfgr_reg |= SSD2828_CFGR_CSS;
  350. }
  351. /*
  352. * Setup the parallel LCD timings in the appropriate registers.
  353. */
  354. if (ssd2828_configure_video_interface(cfg, mode) != 0) {
  355. ssd2828_free_gpio(cfg);
  356. return 1;
  357. }
  358. /* Configuration Register */
  359. cfgr_reg &= ~SSD2828_CFGR_HS; /* Data lanes are in LP mode */
  360. cfgr_reg |= SSD2828_CFGR_CKE; /* Clock lane is in HS mode */
  361. cfgr_reg |= SSD2828_CFGR_DCS; /* Only use DCS packets */
  362. write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
  363. /* PLL Configuration Register */
  364. pll_config = construct_pll_config(
  365. cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000,
  366. reference_freq_khz);
  367. write_hw_register(cfg, SSD2828_PLCR, pll_config);
  368. pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz);
  369. lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8);
  370. /* VC Control Register */
  371. write_hw_register(cfg, SSD2828_VCR, 0);
  372. /* Clock Control Register */
  373. write_hw_register(cfg, SSD2828_CCR, SSD2828_LP_CLOCK_DIVIDER(lp_div));
  374. /* PLL Control Register */
  375. write_hw_register(cfg, SSD2828_PCR, 1); /* Enable PLL */
  376. /* Wait for PLL lock */
  377. udelay(500);
  378. send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE);
  379. mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms);
  380. send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON);
  381. mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms);
  382. cfgr_reg |= SSD2828_CFGR_HS; /* Enable HS mode for data lanes */
  383. cfgr_reg |= SSD2828_CFGR_VEN; /* Enable video pipeline */
  384. write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
  385. return 0;
  386. }